Synopsys Design Constraints

SDC
Synopsys Design Constraints

SDC
Basically constraints are the instructions which designer apply during various stages .
In general timing, power,area constraints are defined by SDC .
It is an output file from synthesis and the same can be used in STA and PNR flows as well
It is supported by tools like DC,ICC,PT
SDC contains
● Version
● Units
● System Interface
● Design Constraints
● Timing constraints
● Timing exceptions
● Logical constraints
● Area constraints
Version :
Will have the version of the sdc
Example : set sdc_version <1.9|2.0|2.1>
Units :
Used to define the units for time , Voltage, Resistance,Cap,
Example:
set_units -time ns -resistance Kohm -capacitance pF -voltage V -current mA

System Interface :
Set_driving_cell
If the i/p port is driving from a cell , in order to get accurate external delay for
timing calculation , the i/p port should get the load from the driving cell . To get the
external delay on the input port from the driving cell usig this .
Ex :
Set_driving_cell -lib_cell <driving_cell> [get_ports input_port]
Set_load
Used to define the capacitance load on the output_port
Ex: set_load <cap_value> [get_ports output_port]
DRC - Design Rule Constraints
From where we get the DRC values ?
Liberty file (.lib)
Can we override these DRC values and how ?
Yes , we can tighter the constraints instead of relaxing .
What are the DRC ?
● Max fanout
● Max tran
● Max/Min cap
Transition time : Time taken by the driver pin and net to change the logic .
Syntax :
Set_max_transition <value> [object_list] -[clcok_path|data_path]
Object_list - clocks | i/p pin | port | design
Fanout :
Defines the max no.of.inputs that a drive can handle .
If the fanout is more than the max ,then the output voltage degrade and the gates
will slow down .
Syntax:
Set_max_fanout <value> [i/p ports|design]
Cap :
Max_cap : Max load that the output pin can drive
Min cap : Min load that the output pin should drive
If the load is higher than max value - charging and discharging of cell will take time
so delay if the cell becomes high also chances of X-talk_noise violation
Syntax :
● Set_max_capacitance <value> object_list -[clock_path | data_path]

● Set_min_capacitance<value> object_list -[clock_path | data_path]
Object_list [clock| o/p port | pin ]

Timing Constraints
Defining clocks , gen_clocks and the relationships b/w different clocks .
Create_clock :
Used to define the clock with the required period on the required port or pin .
Ex:
● create_clock -name <name of the clock> -period <value> -waveform { 0 5}

Create_gen_clock :
Derived from master clock
Ex:
● Create_generated_clock <name> -source <master_definition_point>
-divide_by <value> -master_clock <name of the master clock>
<gen_clock_point>
● Create_generated_clock <name> -source <master_definition_point> -edges
{1 3 5} -master_clock <name of the master clock> <gen_clock_point>
Virtual Clock
Clocks are defined without sources
Ex:
● Create_clock -name V_CLK -period 10
Clock_groups
Defines the relation b/w the clocks whether async | logically_exclusive | physically_exclusive
Example :
Async to all clocks
● Set_clock_group -name g1 -group clk1 -async
Clk and clk3 are async to each other:
● Set_clock_group -name g2 -group clk -group clk3 -asyn
Clk2 and clk4 present in the design but functionally no paths exists b/w . example scen : clocks defined at
mux i/p pins
● set_clock_group -name g3 -group clk2 -group clk4 -logically_exclusive
Clocks defined on the same pin but doesn’t coexists . Ex : func clock and scan clock defined on the same
clock port but they wont coexist at the same time .
● set_clock_group -name g4 -group clk5 -group clk1 -physically_exclusive

Set_clock_latency
Delay b/w external clk source and definition pin of clk .
● set_clock_latency 2.35 -source [get_pins <pin_hier>]
Set_clock_uncertainty
Uncertainty is a window within which a clock edge can occur .
Uncertainty = jitter (deviation of clock from ideal position) + additional margins + skew
Pre_cts Setup uncertainty : jitter + skew + extra setup margin
Post_cts setup uncertainty : jitter + extra setup margin
Pre_cts Hold Uncertainty : skew + extra hold margin
Post_cts Hold margin : Extra hold margin
● set_clock_uncertainty 2 -from [get_clocks CLKB] -to [get_clocks CLKA] - setup | hold

Set_clock_transition
To specify the transition time of register clock pins , here we can specify only clocks with ideal latency .
This will be discarded once clock trees were built actual transition values will be used .
● Set_clock_transition –rise/fall 0.05 [get_clocks test_clock]
Set_disable_timing
If there is a combo loop will get reported in the check_timing reports in PT . To break the loop and to perform
STA disable_timing is used
● Set_disable_timing -from <from_pin> -to <to_pin>

Set_timing_derate:
In OCV , all nets and cells in clock_path and data_path will be added with fixed derate values .
Setup :
Max : Data path and launch clock path
Min : Capture clock path
Hold
Max : Capture clock path
Min : Data path and launch clock path
Ex : This derate value applied for both cell and net and applied to both clock and data paths
● set_timing_derate -early 0.95
● set_timing_derate -late 1.05

Set_input_delay
Input_delay is used where the start point is from the input port and the end point is D of the FF
Input delay is the delay from the CK pin of the flop to the input_port (which is in Design Under Analysis)
● Set_input_delay 1.1 -add_delay -max -clock v_clk1 {input_port1}
Set_output_delay
output_delay is used where the start point is from the CK of FF and the end point is output_port
Output delay is the delay from output_port (which is in Design Under Analysis) to D pin of F/F which is outside
the design under analysis
● Set_output_delay 1.1 -add_delay -max -clock v_clk1 {output_port1}

Timing Exceptions
Set_multicycle_path
Used when the timing is not met in the single clock cycle (only for valid paths)
B/w same clocks
● set_multicycle_path 3 -from [start_point] -to [end_point] -end

● Set_multicycle_path 2 -from [start_point] -to [end_point] -hold -start
MCP contd…
MCP b/w SLOW to FAST clock
● Set_multicycle_path 2 -from clk1 -to clk2 -end

● Set_multicycle_path 1-from clk1 -to clk2 -end
MCP b/w FAST to SLOW clock
● Set_multicycle_path 2 -from c1 -to c2 -start

● Set_multicycle_path 1-from c1 -to c2 -start
Set_max_delay & set_min_delay
Here F1 nd F2 flops are valid clock domain crossing paths , here we can’t apply false path so using
max_delay just to time this path
Used to constrain the IO paths
Ex :
● Set_max_delay 150 -from [get_clock c1] -to [get_clock c2]

● Set_min_delay 150 -from [get_clock c1] -to [get_clock c2]
False_path
Used when there is a timing violation occurred in invalid paths like b/w async clocks or the scan signals .
● Set_false_path -from <startpoint> -to <end_point>
Set_case_analysis
To define the value for the select pin of the mux to select A or B pin (i.e test or func)
Syntax :
● Set_case_analysis <value 1 | 0> <pin_name>
To read and write sdc :
Write : write_sdc -output <name.sdc>
Read : read_sdc <path of the file>

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SDC

Synopsys Design Constraints

Will have the version of the sdc

Example : set sdc_version <1.9|2.0|2.1>

Used to define the units for time , Voltage, Resistance,Cap,

set_units -time ns -resistance Kohm -capacitance pF -voltage V -current mA

● Set_max_capacitance <value> object_list -[clock_path | data_path]

Object_list [clock| o/p port | pin ]

Defining clocks , gen_clocks and the relationships b/w different clocks .

● create_clock -name <name of the clock> -period <value> -waveform { 0 5}

Async to all clocks

● Set_clock_group -name g1 -group clk1 -async

Clk and clk3 are async to each other:

● Set_clock_group -name g2 -group clk -group clk3 -asyn

● set_clock_group -name g3 -group clk2 -group clk4 -logically_exclusive

● set_clock_group -name g4 -group clk5 -group clk1 -physically_exclusive

Delay b/w external clk source and definition pin of clk .

● set_clock_latency 2.35 -source [get_pins <pin_hier>]

Uncertainty is a window within which a clock edge can occur .

Pre_cts Setup uncertainty : jitter + skew + extra setup margin

Post_cts setup uncertainty : jitter + extra setup margin

Pre_cts Hold Uncertainty : skew + extra hold margin

Post_cts Hold margin : Extra hold margin

● set_clock_uncertainty 2 -from [get_clocks CLKB] -to [get_clocks CLKA] - setup | hold

● Set_clock_transition –rise/fall 0.05 [get_clocks test_clock]

● Set_disable_timing -from <from_pin> -to <to_pin>

Max : Data path and launch clock path

Min : Capture clock path

Max : Capture clock path

Min : Data path and launch clock path

● set_timing_derate -early 0.95

● set_timing_derate -late 1.05

● Set_input_delay 1.1 -add_delay -max -clock v_clk1 {input_port1}

● Set_output_delay 1.1 -add_delay -max -clock v_clk1 {output_port1}

● set_multicycle_path 3 -from [start_point] -to [end_point] -end

● Set_multicycle_path 2 -from clk1 -to clk2 -end

● Set_multicycle_path 2 -from c1 -to c2 -start

Used to constrain the IO paths

● Set_max_delay 150 -from [get_clock c1] -to [get_clock c2]

● Set_false_path -from <startpoint> -to <end_point>

● Set_case_analysis <value 1 | 0> <pin_name>

To read and write sdc :

Write : write_sdc -output <name.sdc>

Read : read_sdc <path of the file>

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