Digital Design and Synthesis

with

Verilog HDL
Eli Sternheim, Ph.D. interHDL, Inc. Rajvir Singh interHDL, Inc. Rajeev Madhavan Cadence Design System,Inc. Yatin Trivedi YT Associates

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Chapter 1
Why hardware description languages?
Evolutionary trends in design methods.
The use of hardware description languages (HDLs) for logic design has greatly expanded in the last few years. Engineering managers no longer face the dilemma of whether to design with an HDL or not.

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Designing with Verilog HDL

Verilog HDL is simple and elegant. It provides constructs to describe hardware elements in a succinet and readable form. A comparable description, for example in VHDL, can be twice as long as a Verilog description.

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Designing with Verilog HDL

In Verilog, a designer needs to learn only one language for all aspects of logic design. Simulation of a design, at least, requires functional models, hierarchical structures, test vectors, and man/machine interaction. In Verilog, all of these are achieved by one language. Almost every statement that can be written in procedural code can also be issued in an interactive session from the terminal.

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Designing with Verilog HDL

Verilog is not only concise and uniform, but also is easy to learn. It is very similar to the C programming language. Since C is one of the most widely used programming languages, most designers should be familiar with it and may, therefore, find it easy to learn Verilog.

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Chapter 2
Anatomy of the Verilog HDL
In this chapter we introduce the Verilog hardware description language through a sequence of examples. A more complete specification of the language can be found in the Language Reference Manual and in the Condensed Reference Manual in Appendix A.

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Anatomy of the Verilog HDL

A module definition example, structural style.

//structural module AND2 (in1, in2, out); input in1; input in2; output out; wire in1, in2, out; and u1 (out, in1, in2); endmodule

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Anatomy of the Verilog HDL

A module definition example, data flow style.
//data flow module AND2 (in1, in2, out); input in1; input in2;

output out;
wire in1, in2, out; assign out = in1 & in2; endmodule

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Anatomy of the Verilog HDL

A module definition example, behavioral style
//behavioral module AND2 (in1, in2, out); input in1; input in2; output out;

wire in1, in2;

reg out; always @ (in1 or in2) out= in1 & in2; endmodule

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Anatomy of the Verilog HDL

Test Fixture for and2 module
module test_and2; reg i1, i2; wire o; AND2 u2 (i1,i2,o); initial begin i1=0; i2=0; #1 $display (i1=%b, i2=%b, o=%b, i1, i2, o ); i1=0; i2=1; #1 $display (i1=%b, i2=%b, o=%b, i1, i2, o ); i1=1; i2=0; #1 $display (i1=%b, i2=%b, o=%b, i1, i2, o ); i1=1; i2=1; #1 $display (i1=%b, i2=%b, o=%b, i1, i2, o ); end endmodule

Test results
i1=0, i2=0, o=0 i1=0, i2=1, o=0 i1=1, i2=0, o=0 i1=1, i2=1, o=1

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Anatomy of the Verilog HDL

Structural and_or module example.
module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; wire tmp and #10 u1 (tmp, in1, in2 ) , u2 (undec, in3, in4 ); or #20 (out, tmp, undec ); endmodule

Data flow and_or example.

module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; wire tmp; assign #10 tmp= in1 & in2; wire #10 tmp1= in3 & in4; assign #20 out= tmp | tmp1; // The three assignments could be condensed //into one: //assign #30 out=(in1 & in2) | (in3 &in4); endmodule

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Anatomy of the Verilog HDL

Behavioral and_or example.
module and_or (in1, in2, in3, in4, out ); input in1, in2, in3, in4; output out; reg out; always @ (in1 or in2 or in3 or in4) begin if (in1 & in2 ) out = #30 1; else out = #30 (in3 & in4); end endmodule

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Anatomy of the Verilog HDL

Test fixture for and_or module.
module test_and_or; reg r1, r2, r3, r4; wire o; and_or u2 (.in2(r2), .in1(r1), .in3(r3), .in4(r4), .out(o)); initial begin : bl reg [4:0] i1234; for (i1234 =0; i1234<16; i1234= i1234+1) begin (r1, r2, r3, r4) = i1234 [3:0]; #31 $display (r1r2r3r4 = %b%b%b%b , o=%b, r1, r2, r3, r4,o ); end end endmodule

And_or simulation results

r1r2r3r4 = 0000 r1r2r3r4 = 0001 r1r2r3r4 = 0010 r1r2r3r4 = 0011 r1r2r3r4 = 0100 r1r2r3r4 = 0101 r1r2r3r4 = 0110 r1r2r3r4 = 0111 r1r2r3r4 = 1000 r1r2r3r4 = 1001 r1r2r3r4 = 1010 r1r2r3r4 = 1011 r1r2r3r4 = 1100 r1r2r3r4 = 1101 r1r2r3r4 = 1110 r1r2r3r4 = 1111 , , , , , , , , , , , , , , , , o =0 o=0 o=0 o=1 o=0 o=0 o=0 o=1 o=0 o=0 o=0 o=1 o=1 o=1 o=1 o=1

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Anatomy of the Verilog HDL

Basic Operators and Expressions
integer i, j ; real f, d; wire [7:0] bus; reg [0:15] word; reg arr [0:15]; reg [7:0] mem[0:127]; event trigger, clock_high; time t_setup, t_hold; parameter width= 8; parameter width2= width*2; wire [width-1:0] ww; //the following are illegal: wire w[0:15]; wire [3:0] a, [7:0]b; //two integers //two real numbers //8-bits wide bus //16-bits wide word //array of 16 one-bit reg`s //array of 128 bytes //two events //t1, t2

//wires cannot be in arrays //only one width specification per declaration

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Anatomy of the Verilog HDL

Summary of Verilog Operators
+ - * / > >= < <= ! && || == != ? : {} % === !== ~ & | << >> //arithmetic //relational //logical //logical equality //conditional //concatenate //modulus //case equality //bit-wise //shift

Operator Precedence
* / % Highest precedence + << >> < <= > >= = = != = = = != = & ^ ^~ | && Lowest precedence

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Anatomy of the Verilog HDL

Difference between = = and = = =
module equequ; initial begin $display ( `bx = = `bx is %b, `bx = = `bx); $display ( `bx = = = `bx is %b, `bx = = = `bx); $display ( `bz ! = `bx is %b, `bz ! = `bx); $display ( `bz ! = = `bx is %b, `bz ! = = `bx); end endmodule

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Anatomy of the Verilog HDL

Concatenation and replication
module concat_replicate (swap, signextend ); input swap, signextend; reg [15:0] word; reg [31:0] double; reg [ 7:0] byte1, byte2; initial begin byte1=5; byte2=7; if (swap) word = {byte2, byte1}; else word = {byte1, byte2}; if (signextend) double = { {16 {word[15]}} , word}; else double = word; end endmodule

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Anatomy of the Verilog HDL

A for statement
module for_loop; integer i; initial for ( i=0; i<4; i=i+1 ) begin $display ( i =%0d ( %b binary) ,i ,i ); end endmodule

Results of for_loop execution

i = 0 ( 0 binary ) i = 1 ( 1 binary ) i = 2 ( 10 binary ) i = 3 ( 11 binary )

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Anatomy of the Verilog HDL

A while_loop statement
module while_loop; integer i; initial begin i=0; while ( i<4 ) begin $display ( i =%d ( %b binary) ,i ,i ); i=i+1; end end endmodule

A case statement
module case _statement; integer i; initial i=0; always begin $display ( i= %0d, i); case ( i ) 0: i = i + 2; 1: i = i + 7; 2: i = i + 1; default: $stop; endcase end endmodule

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Anatomy of the Verilog HDL

A repeat loop
module repeat_loop ( clock ) input clock; initial begin repeat ( 5 ) @ ( posedge clock); $stop; end endmodule

A forever loop
module forever_statement ( a, b, c ); input a, b, c; initial forever begin @( a or b or c ) if ( a + b = = c ) begin $display (a( %d) + b( %d) = c(%d),a ,b, c); $stop; end end endmodule

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Anatomy of the Verilog HDL

The axis of time
current time t1 Event 0 Event 1 Event 2 t2 Event 3 t3 Event 4 Event 5

Multiple behavioral instances

module event_control; reg [4:0] r; initial begin $display ( First initial block, line 1.); $display ( First initial block, line 2.); end initial for ( r = 0; r <= 3; r = r + 1) &display ( r = %0b, r ); endmodule

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Anatomy of the Verilog HDL

#expression @event-expression wait (expression)

Example of time control

module time_control; reg [1:0] r; initial #70 $stop; initial begin : b1 //Note a named block, b1 #10 r =1; //wait for 10 time units #20 r =1; //wait for 20 time units #30 r =1; //wait for 30 time units end initial begin : b2 //Note a named block, b2 # 5 r =2; //wait for 5 time units #20 r =2; //wait for 20 time units #30 r =2; //wait for 30 time units end always @r begin $display ( r =%0d at time %0d, r, $time ); end endmodule

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Anatomy of the Verilog HDL

Example of event control
module event_control; event e1, e2; initial @e1 begin $display ( I`am in the middle. ); ->e2; end initial @e2 $display ( I`am supposed to execute last. ); initial begin $display ( I`am the first. ); ->e1; end endmodule

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Anatomy of the Verilog HDL

Example of parallel processes
module fork_join; event a, b; initial fork @a; @b; join endmodule

Example of disable
module disable_block; event a, b; //Block name is needed fork : block @a disable block 1; @b disable block 1; join endmodule

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Anatomy of the Verilog HDL

Simulating break and continue statements
begin : breakloop for ( i=0; i<1000; i=i+1 ) begin : continue if ( a[i] = = 0 ) disable continue; // i.e continue if ( b[i] = = a[i] ) disable break; // break $display ( a[ , i , ]= , a[i] ); end end

Example of a task
task tsk; input i1, i2; output o1, o2; $display ( Task tsk, i1=%0b, i2=%0b , i1, i2 ); #1 o1 = i1 & i2; #2 o2 = i1 | i2; endtask

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Anatomy of the Verilog HDL

Example of a function
function [7:0] func; input i1; integer i1; reg [7:0] rg; begin rg = 1; for ( i = 1; i <= i1; i = i +1 ) rg =rg + 1; func = rg; end endfunction

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Anatomy of the Verilog HDL

Behavioral description of a 4-bit adder
module adder4 ( in1, in2 , sum, zero ) input [3:0] in1; input [3:0] in2; output [4:0] sum; output zero; reg [4:0] sum; reg zero; initial begin sum = 0; zero = 1; end always @( in1 or in2 ) begin sum = in1 + in2; if ( sum = = 0 ) zero = 1; else zero = 0; end endmodule

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Anatomy of the Verilog HDL

Using an initial forever assignments
initial begin forever @( in1 or in2 ) begin sum = in1 + in2; if ( sum = = 0 ) zero = 1; else zero = 0; end end

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Anatomy of the Verilog HDL

Using a continuous assignment
module adder4 ( in1, in2 , sum, zero ) input [3:0] in1; input [3:0] in2; output [4:0] sum; reg [4:0] sum; output zero; assign zero = ( sum = = 0 ) ? 1 : 0; initial sum = 0; always @( in1 or in2 ) sum = in1 + in2; endmodule

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Anatomy of the Verilog HDL

Structural description of 4-bit adder
module adder4 ( in1, in2, s, zero ) input [3:0] in1; input [3:0] in2; output [4:0] s; output zero; fulladd u1 ( in1[0], in2[0], 0, s[0], c0 ); fulladd u2 ( in1[1], in2[1], c0, s[1], c1 ); fulladd u3 ( in1[2], in2[2], c1, s[2], c2 ); fulladd u4 ( in1[3], in2[3], c2, s[3], s4 ); nor u5 ( zero, s[0], s[1], s[2], s[3], s[4] ); endmodule

Behavior of a 1-bit full adder

module fulladd ( in1, in2, carryin, sum, carryout ); input in1, in2, carryin; output sum, carryout; assign { carryout, sum } = in1 + in2 + carryin; endmodule

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Anatomy of the Verilog HDL

Mixed mode representation
module adder4 ( in1, in2 , sum, zero ) input [3:0] in1; input [3:0] in2; output [4:0] sum; output zero; reg zero; fulladd u1 ( in1[0], in2[0], 0, sum[0], c0 ); fulladd u2 ( in1[1], in2[1], c0, sum[1], c1 ); fulladd u3 ( in1[2], in2[2], c1, sum[2], c2 ); fulladd u4 ( in1[3], in2[3], c2, sum[3], sum4 ); always @( sum ) if ( sum = = 0 ) zero = 1; else zero = 0; endmodule

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Chapter 3
Modeling a Pipelined Processor
In this chapter we take the specification of a 32-bit processor and develop a functional model for it through various stages of successive refinement. First we implement an instruction set model, then we describe a register transfer level (RTL) model. In the next chapter we arrive at a structural model that maps the processor to various building blocks. In the process, we explain modeling of such concepts as pipelining, concurrency, instruction execution, functional partitioning, and creation of test vectors.
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Modeling a Pipelined Processor

The emphasis here is on the process of modeling as opposed to describing the architecture of a processor. It is not our intention to explain the detailed functionality of any commercial microprocessor or architecture. Some discussion on processor architecture is presented to explain the concepts and process of modeling.

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Chapter 4
Modeling System Blocks
In the previous chapter we saw how to model a processor at the instruction set level and its function at the behavioral level. In this chapter we present a structural model of the SISC processor and show how to model its various building blocks. We begin with the block diagram of the SISC processor and present its corresponding structural model to show the interconnections of its building blocks. In subsequent sections we develop functional models for these blocks, namely, the datapath, the memory elements, the clock generator and the control unit.
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Chapter 5
Modeling Cache Memories
In this chapter we examine the process of designing a simple cache system in Verilog HDL. The description can be synthesized to obtain a gate level implementation. At the end of this chapter we consider ways to improve the basic design.

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Modeling Cache Memories

A cache in a computer system is a small, fast, local memory that stores data from the most frequently accessed addresses. The cache is always small compared to main memory because cache RAMs are more expensive then the slower dynamic RAMs used for main memory. As a result, only a small portion of the main memory can be stored in the cache. The efficiency of a cache is measured by the cache hit ratio, i.e., the number of times data is accessed from the cache over the total number of memory accesses. Typical hit ratios are in the range of eighty to one hundred percent.

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Chapter 6
Modeling Asynchronous I/O: UART
In this chapter we present an example of modeling an asynchronous peripheral device, a dual Universal Asynchronous Receiver Transmitter (UART) chip. We develop two models of the chip. The first model is a high-level abstraction which describes the functionality of the chip and emphasizes simplicity, readability and ease of change. The second model is oriented toward gate-level implementation. This model is partitioned so that a logic synthesizer can be used to automatically implement the chip with library components.
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Chapter 7
Verilog HDL for Synthesis
In the previous chapters we introduced Verilog HDL and showed how it can be used in different ways to support top-down hierarchical design. In this chapter we cover the basics of synthesis, discuss how Verilog may be used for synthesis and describe how modeling for synthesis affects the coding style, the design organization and partitioning.

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Chapter 8
Modeling a Floppy Disk Subsystem
In this chapter we provide a complete example of a floppy disk subsystem (FDS) model in Verilog. Such a model may be needed when you perform a full system simulation and want to simulate the execution of code which accesses the disk. The FDS model would typically be used to perform a full functional simulation during the development of a CPU board. This example demonstrates the modeling of asynchronous systems, I/O buses, timing constraints, and other techniques of writing large models.
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Chapter 9
Useful Modeling and Debugging Techniques
Learning to design and simulate in Verilog is more then just learning the syntax and semantics of the language. As in every learning process, the best way to learn is by doing. As you start using the language, you will develop your own style of design, and you will discover techniques for modeling in Verilog. In this chapter we present some tips and techniques that we hope will help you in developing your own techniques on the way to mastering Verilog.

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