IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO.

4, APRIL 2014 1269

A– -dBm Dual-Channel UHF Passive CMOS

RFID Tag Design
Chia-Yu Yao, Member, IEEE, and Wei-Chun Hsia, Student Member, IEEE

Abstract—Previous research results showed that UHF passive consists of voltage doubler cells and a voltage doubler cell is
CMOS RFID tags had difficulty to achieve sensitivity less than composed of diodes and capacitors [3]. In a charge pump, if the
. This paper presents a dual-channel 15-bit UHF passive number of voltage doubler stages increases, the power transfer
CMOS RFID tag prototype that can work at sensitivity lower than
. The proposed tag chip harvests energy and backscat- efficiency will decrease [1]. Thus, it is impossible to convert RF
ters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) power to dc voltage without limitation. Therefore, the output
channel and receives downlink data at 433-MHz channel. Conse- supply voltage level is confined, especially when the received
quently, the downlink data transmission does not interrupt our tag RF power is weak; i.e., when the tag is distantly away from the
from harvesting RF energy. To use the harvested energy efficiently, reader.
we design a tag chip that includes neither a regulator nor a VCO
such that the harvested energy is completely used in receiving, pro- Some researchers improved their tags’ receiving sensitivity
cessing, and backscattering data. Without a regulator, our tag uses to increase the communication range to the readers in the past
as few active analog circuits as possible in the receiver front-end. decade. Curty [4] designed a 3-bit RFID tag prototype using
Instead, our tag uses a novel digital circuit to decode the received 0.5- silicon-on-insulator (SOI) technology. Since the SOI
data. Without a VCO, the design of our tag can extract the required chip has an extremely low-loss substrate, the SOI tag chip in
clock signal from the downlink data. Measurement result shows
that the sensitivity of the proposed passive tag chip can reach down [4] can achieve -dBm sensitivity at 2.45 GHz. Karthaus
to . Such result corresponds to a 19.6-m reader-to-tag [5] and Lee [6] used Schottky diodes in their charge pumps
distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The because the Schottky diode has a low turn-on voltage and a high
chip was fabricated in TSMC 0.18- CMOS process. The die saturation current. The achieved sensitivities of [5], [6] were
area is 0.958 mm . and , respectively. Baghaei-Nejad
Index Terms—Charge-pump circuit, Dickson rectifier, passive [7] designed a dual-channel, oscillator-less tag chip to achieve
RFID tag, pulse-interval encoding (PIE), pulse-interval encoding -dBm sensitivity. The uplink transmission in [7] used
(PIE)-to-binary decoder. the ultra wide band (UWB) technology. Radiom [8] further
advanced the sensitivity of the dual-channel tag design to
at 900 MHz. It is noted that, in contrast to the
I. INTRODUCTION
expensive SOI tag, none of the reported passive CMOS RFID
tags can achieve -dBm sensitivity. The other researchers

T HE passive RFID technology finds more and more appli- used multiple tag antennas to increase the communication
cations in many fields recently, such as collecting traffic distance between readers and tags [9], [10]. The increased
tolls, handling baggages, and monitoring environment [1], [2]. reader-tag distance in [9] by using dual antennas is around 2
Among various passive RFID systems using different RF bands, m at charge-pump output power. On the other hand,
the UHF RFID is the most promising passive RFID technology the increased reader-tag distance in [10] by evaluating the
because the UHF RFID system works with smaller antenna size backscattered antenna’s radar cross section is around 0.5 m.
than the other RFID technologies do. Since a passive RFID tag Because the harvested RF energy is so precious, the passive
has no battery, the main challenge an engineer faces is to design tag chip should use the harvested energy efficiently. Looking
a method for the tag not only to harvest energy effectively but into the tag chip reported in [6], we see that the regulator and
also to use energy efficiently from weak electromagnetic (EM) the voltage-controlled oscillator (VCO) are two power hungry
radiation. components. The function of a regulator is to provide stable
The most important component for energy harvesting in an supply and bias voltages to analog active circuits. The function
RFID tag chip is the charge pump. The charge pump circuit of a VCO is to generate the clock signal. If the tag has no analog
active circuit and needs not generate clock by itself, then we can
remove these two power hungry components. Hence, this work
Manuscript received April 30, 2013, revised August 26, 2013; accepted
September 13, 2013. Date of publication November 01, 2013; date of current (and its premature version [11]) designed a regulator-less, VCO-
version March 25, 2014.This work was supported by the National Science less, dual-channel UHF RFID tag chip to raise the efficiency of
Council of Taiwan, under Grant NSC 100-2221-E-011-095. This paper was
energy usage and to increase the communication distance from
recommended by Associate Editor J. Kim.
The authors are with the Department of Electrical Engineering, National the reader to the tag. Notably, a dual-channel frequency plan
Taiwan University of Science and Technology, Taipei, 106, Taiwan (e-mail: is a reasonable (perhaps the best) choice for an RFID system
chyao@mail.ntust.edu.tw).
employing VCO-less tags [7].
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Although the proposed RFID system also employs a dual-
Digital Object Identifier 10.1109/TCSI.2013.2285911 channel design, the mechanism of our system is different from

1549-8328 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1270 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 4, APRIL 2014

that of [7]. In [7], the downlink power transfer and the data trans-
mission used a narrow-band 900-MHz channel and the uplink
data transmission employed the UWB channel. Since the up-
link power is already very low in a passive tag and the UWB
signal suffers from more serious path loss than the 900-MHz
signal, designing the reader for the tag of [7] will be a big chal-
lenge to engineers. In [11], we use the 2.4-GHz band to transmit
the downlink data. Since the path loss of the 2.4-GHz signal
is severe, the communication range of the tag in [11] is only
around ten meters. In this work, the downlink data transmission
employs the low-band channel (433 MHz), and the downlink
power transfer and the uplink backscattered data transmission
use the high-band channel (866.4 MHz for ETSI compliance
or 925 MHz for FCC compliance). Notably, the communication
distance of the conventional UHF RFID system is limited by the
reader-to-tag power link. In this work, the downlink data trans- Fig. 1. Proposed RFID transponder system architecture.
mission does not interrupt our tag from harvesting RF power,
so the tag can be charged continuously during the period of re-
ceiving the downlink data. On the other hand, designing the
reader for the proposed tag will be easier than that for the tag
of [7].
The measurement results of this work showed that the pro-
posed tag at the high-band channel can achieve -dBm
sensitivity. At the low-band channel, the proposed tag can
achieve -dBm sensitivity. Compared with our previous tag
[11] whose communication distance is limited by the downlink
2.4-GHz signal, the communication distance of this new tag is
now limited by the 900-MHz power link. Hence, our new tag
extends the communication distance to 19.6 meters.
This paper is organized as follows: Section II presents the
system architecture and the timing diagram of our design. Sec- Fig. 2. Timing diagram of the proposed dual-channel RFID system.
tion III describes all detail building blocks of the tag circuit. Sec-
tion IV shows the experiment setup and measurement results of
the tag. Section IV also compares the results between our work high-band continuous wave (CW) to VDD. Because the tag has
and some recently published papers. Finally, Section V summa- no regulator, we employ a limiter to prevent the tag from over-
rizes the conclusions of this paper. charging when the charging CW power is too strong. After VDD
is sufficiently high, the power-on-reset (POR) circuit issues a
POR signal to clear all flip-flops in the tag chip. Later, the reader
II. ARCHITECTURE OF THE PROPOSED TAG
sends the amplitude-shift-keying (ASK) PIE signal to the tag via
In this work, the proposed tag has no VCO nor a regulator. the low-band channel. The tag’s passive envelope detector de-
With no VCO, our tag cannot generate the required clock signal modulates the received ASK signal to the baseband PIE signal.
by itself. Since the RFID downlink pulse-interval encoding Next, the PIE-to-binary decoder directly decodes the PIE signal
(PIE) signal is self-timing, the proposed tag chip extracts the to binary waveform without the need of an analog amplifier. The
required clock signal from the downlink PIE signal. On the baseband processing unit (BPU) processes the binary data and
other hand, with no regulator, the generated supply voltage determines whether the tag should respond to the reader. Upon
(VDD) in the proposed tag can never be a good dc source. BPU’s positive decision, the bi-phase-space (FM0) encoder en-
This situation is harsh for active analog circuits. Therefore, codes the data for transmission. Finally, the FM0 code controls
the proposed tag chip only uses a simple passive envelope the gate voltage of a shunt NMOS transistor in the backscatter
detector at the receiver front-end. We then design a novel circuit. If the gate voltage is low, then the NMOS transistor is
digital PIE-to-binary decoder, which is less sensitive to the off and the impedance of the 925-MHz port matches with that
power, voltage, and temperature (PVT) variations than the of the high-band antenna, so the charge pump can convert the
active analog circuit is, to decode the received data. received CW power effectively. If the gate voltage is high, the
Fig. 1 shows the system block diagram of the proposed UHF NMOS transistor is on and the impedance of the 925-MHz port
RFID tag and Fig. 2 shows the corresponding system timing di- mismatches with that of the high-band antenna, so the tag can
agram. Since the proposed RFID system uses dual bands, the reflect the CW power to the reader. Once the CW power is re-
passive tag has two antennas, one for the high-band channel flected, the tag can not obtain the high-band CW power effec-
(866.4 MHz or 925 MHz) and the other for the low-band channel tively. Thus, the received CW shows some dips after the tag
(433 MHz). The charge pump circuit transduces the received starts to respond to the reader.
YAO AND HSIA: – -DBM DUAL-CHANNEL UHF PASSIVE CMOS RFID TAG DESIGN 1271

Fig. 3. Proposed tag prototype and two antennas.

The intended application of the proposed prototype is the in-

door passive UHF RFID positioning system used in a ware-
house. Such an application requires passive RFID tags with long
reading range. The readers for the intended application detect
the time of arrival (TOA) instead of the received signal-strength Fig. 4. Measured radiation pattern of the 925-MHz microstrip antenna for the
tag.
index (RSSI) because the distance-RSSI profile in the indoor
environment is not precise [12]. The details of the intended ap-
plication is beyond the scope of this paper. Nevertheless, we
employ a simple protocol to verify the tag’s functionality and
the link effectiveness from the reader to the tag. In this work,
we define that the PIE ‘0’ has one Tari duration [13] and the
PIE ‘1’ has two Tari duration. The tag has a 15-bit ID code. The
reader sends 15-bit PIE data. The tag compares the received data
with its ID code. If they match, the tag responds to the reader.
It is noted that the downlink 15-bit PIE data sent to the tag can
serve as the clock signal for the tag. After the reader complete
sending the 15-bit data, the reader continuously sends another Fig. 5. (a) Measured of the 925-MHz microstrip antenna. (b) Measured
33 PIE ‘0’ symbols as the required clock signal for the tag. The of the 433-MHz chip antenna.
detail of this part is discussed in the next section.
It is noted that although some parts of our design refer to EPC
Class-1 Gen-2’s recommendations, this tag prototype and its in- [14]. Both antennas possess nearly omnidirectional radiation
tended application are not compliant with EPC Class-1 Gen-2 patterns. Figs. 5(a) and 5(b) show the measured return losses of
UHF RFID system. the 925-MHz antenna and the 433-MHz antenna, respectively.

III. DETAIL BUILDING BLOCKS B. Charge Pump, Limiter, and Power-on-Reset Circuits
Fig. 6 shows the charge-pump circuit, the limiter, and the
A. Antennas power-on-reset (POR) circuit of the proposed tag chip. The
Because 866.4 MHz and 925 MHz are close enough, this charge-pump circuit is composed of eight Dickson rectifiers [3]
paper only shows the experimental result of using 925 MHz as to convert the received ac power to the dc voltage. In order to
the power-link channel. It is noted that the tag still works well have a low forward voltage drop across the diode-connected
if we use a 866.4-MHz as the power-link channel. NMOS transistor, we use native NMOS transistors with the
We design a microstrip antenna printed on an FR4 PCB as minimal in the Dickson rectifier. We first simulated
the high-band antenna. On the other hand, since the 433-MHz the power transferring efficiency of the charge-pump circuit
microstrip antenna on an FR4 PCB will occupy too much area using different transistor ratios [15] with -dBm RF
that is not suitable for an RFID tag, we employ the low temper- input power at different corners and temperature. The load re-
ature co-fired ceramic (LTCC) chip antenna by YAGEO as the sistance in this simulation is . Fig. 7 shows the simulation
low-band antenna [14]. Fig. 3 shows the tag prototype for the results. We see that the efficiency is poor at the FF corner, so
over-the-air (OTA) test. In Fig. 3, the antenna on the left side we take only the TT and SS corners into account in deciding the
is the 925-MHz microstrip antenna and the antenna on the right transistor size. The optimal ratio at TT is around
side is the 433-MHz chip antenna. 10. However, to have better tolerance over the PVT variations,
The 925-MHz microstrip antenna that we design for the we employ in our charge-pump circuit.
tag possesses 0.4-dBi average gain. Fig. 4 shows its measured The limiter circuit works as follows: If the tag receives a
radiation pattern. The 433-MHz chip antenna for the tag has strong high-band CW signal, the node voltages V1 through V8
-dBi average gain. Its radiation pattern can be found in may be charged too high. The limiter monitors the middle node
1272 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 4, APRIL 2014

Fig. 6. Charge-pump, the limiter, and the POR circuits.

Fig. 8. (a)Post-layout simulation waveforms of VDD, MIR1, and START in

Fig. 6 at -dBm input RF power. (b) The post-layout simulation of VDD
and POR signal at 10-dBm input RF power with and without the limiter.

Fig. 7. Simulated efficiency of the charge-pump circuit using different tran-

sistor ratios with -dBm RF input power.

V5. If V5 is sufficiently high, it will turn on , , and Fig. 9. Envelope detector circuit.
. The current in the – branch starts to flow first.
It can slow down the upclimbing VDD. When V5 goes higher,
the voltage difference between VDD and node MIR1 becomes
larger. Therefore, and starts to drain currents; thus,
the limiter can further slows down the upclimbing VDD.
The operation of the POR circuit is as follows. In the begin-
ning, the MIR1 node voltage rises along with VDD. When the
voltage of V5 goes sufficiently high, the voltage at node MIR1
will drop. After two inverters, the signal ‘POR’ experiences a
low-high-low variation. Thus, it is used as the reset signal for
all D flip-flops (DFFs) in the digital block of the tag.
Fig. 8(a) shows the post-layout simulation waveforms of
VDD, MIR1, and POR at -dBm input RF power. We
can see that the upclimbing VDD is eventually confined by
Fig. 10. PIE-to-binary decoder and the illustrated timing diagram of a PIE
the limiter. The simulation result also verifies the operation of signals.
the POR circuit. Fig. 8(b) shows the post-layout simulations
of VDD and the POR signal at 10-dBm input RF power with
and without the limiter, respectively. We can see that VDD is (CLK shown in Fig. 10) by simply delaying the PIE signal a cer-
over-charged to an unreasonably high voltage if there is no tain amount of time. We then use the extracted CLK to sample
limiter circuit. We also see that the POR works well at 10-dBm the PIE signal to obtain the binary data, as shown in Fig. 10. It
RF input power. is noted that the PIE symbol ‘1’ is longer than the PIE symbol
‘0’. Therefore the decoded binary waveform has longer ‘high’
C. Demodulator and PIE-to-Binary Decoder than ‘low’.
Fig. 9 shows the envelope detector that demodulates the The definition of the PIE symbols that an RFID system adopts
433-MHz ASK-modulated PIE signal. The envelope detector is is used to determine the amount of delay time that the pro-
composed of three Dickson rectifiers, a small diode-connected posed decoder should provide. In this work, we refer to the EPC
NMOS transistor , and two inverters. is used to Class-1 Gen-2 regulations [13]. We let one Tari possess .
replace the large resistor in a conventional envelope detector Thus, it is easy to determine that the amount of delay for dupli-
because the area of a small transistor is less than the area of a cating the PIE signal to the CLK signal should be in the range
large resistor. of to and the best amount of delay time is
Fig. 10 shows a novel PIE-to-binary decoder. Since PIE sig- . To have such a long delay, we design a delay line pos-
naling is a self-timing encoding scheme, we can extract the sessing 27 delay elements and each delay element is composed
timing information hidden in the PIE signal as the clock signal of six cascaded transmission gates and two inverters, as shown
YAO AND HSIA: – -DBM DUAL-CHANNEL UHF PASSIVE CMOS RFID TAG DESIGN 1273

Fig. 11. BPU of the proposed tag.

in Fig. 10. From Fig. 7, we know that the FF native NMOS tran- with tag’s 15-bit ID code. If they are the same, the BPU will
sistors in the charge pump do not work efficiently. Thus, we send the ID code to the FM0 encoder and then the FM0 encoder
simulate the SS and TT situations. Simulation results show that will encode the ID code into FM0 form. Now the reader con-
the delay amount of the delay line is for RF tinuously sends the PIE 0 signal to the tag as the clock signal.
input power at the SS- corner and is for 0-dBm RF Since the FM0 signaling requires a nearly 50% duty cycle wave-
input power at the TT- corner. It is noted that the proposed form [13], we divide the clock rate by two to obtain the 50%-
decoder with 4.6875- delay line can, theoretically, decode the duty-cycle backscatter clock. Finally the FM0 signal controls
PIE signal having a 4.6875- Tari to 9.375- Tari, which cor- the backscatter circuit to respond to the reader.
responds to having 142.2-kbps to 71.1-kbps average data rate if In Fig. 11, the POR signal comes from the POR circuit. When
the PIE symbol ‘0’ and the PIE symbol ‘1’ are equally probable. POR is high, it resets all DFFs in the BPU and the FM0 encoder.
We call this range, (71.1 kbps, 142.2 kbps), a nominal data-rate The ‘Data_in’ signal comes from the output of the PIE-to-binary
range. decoder. The ‘CLK’ input is the PIE signal from the envelope
Since the simulated delay amount of the delay line in the Fig. detector.
10 decoder is for the RF input power at the The detail operation of the BPU is described as follows. In
SS- corner, the data-rate range decreases to (56.2 kbps, the beginning, the ‘check’ signal is low. All three multiplexors
112.4 kbps). On the other hand, for the 0-dBm RF input power (MUXs) deliver their upper inputs to their outputs. Now, the
at the TT- corner, the simulated delay amount is . ‘same’ signal is high and the ‘CLK_new’ is equal to the CLK
Thus, the data-rate range increases to (86.6 kbps, 173.2 kbps). input signal. The Data_in pin receives the binary data from
Recall that we let one Tari possess in our design, which the PIE-to-binary decoder. These data are right shifted into the
corresponds to having a data rate of 106.7 kbps. This data rate 15-bit register and are compared with the 15-bit tag ID code
is within either the nominal data-rate range or the other two next. If they match, the high-to-low ‘same’ signal triggers the
data-rate ranges. check signal to high and the 5-bit counter on the top of Fig. 11
In order not to lengthen the paper, the simulation results are starts to count from 0 to 16. After ‘check’ becomes high, all
not shown here. Instead, we directly show the measured wave- three MUXs deliver their lower inputs to their outputs. Next, the
forms in the next section. stored 15-bit data and an extra ‘dummy 1’ are right shifted to the
FM0 encoder at the clock rate a half of CLK’s rate. Therefore,
D. Baseband Processing Unit (BPU) the tag backscatters 16 bits of data to the reader. (The dummy
Fig. 11 shows the baseband processing unit (BPU) of the 1 is recommended by [13] as the FM0 end of signaling.) When
proposed tag. Because this work only demonstrates the supe- the top counter counts up to 16, all 16-bit data have been shifted
rior sensitivity performance that the proposed VCO-less, regu- to the FM0 encoder. The rightmost DFF of the top counter out-
lator-less, RFID tag can achieve, the protocol of this prototype puts a short logic ‘1’. This short logic ‘1’ resets all DFFs in the
is simple. The BPU compares the received 15-bit binary data digital block and the ‘check’ signal is low again.
1274 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 4, APRIL 2014

Fig. 12. (a) FM0 symbols and sequences (b) FM0 generator state diagram (c)
Schematic view of the FM0 encoder.
Fig. 13. Illustrated waveforms of the FM0 encoder for (a) leading bit equal to
0 (ID15=0), and (b) leading bit equal to 1 (ID15=1).

E. FM0 Encoder

The FM0 signaling defines that its symbol 0 has a logic

high-low or logic low-high transition at the symbol’s midpoint,
while its symbol 1 maintains logic high or logic low in one
symbol duration. It also defines that the adjacent symbols must
not have the same logic value across the symbol boundary.
Fig. 12(a) shows the FM0 symbols and FM0 sequences.
Fig. 12(b) shows the state diagram for generating the FM0
sequence.
Fig. 12(c) shows the circuit schematic of the FM0 encoder.
The Q15 is the output of BPU. When ‘check’ is low, Q15 is
always low. The Q14 is the output of the second right-most DFF
of the BPU. Assume that the leading bit of the received data
has been shifted to Q14. At the next rising edge of CLK_new,
Q14 is loaded into the DFF in the FM0 encoder and into the
right-most DFF in the BPU simultaneously. If the comparing
result in the BPU is positive, then ‘check’ becomes high and we
have exactly two same bits XOR together, which yields D = 0.
Now, CLK_new is high and the leading bit equals ID15. When
the leading bit is 0, FM0_OUT is equal to . Later, after Fig. 14. (a) Backscatter circuit. (b) Measured for matched and unmatched
CLK_new goes low, FM0_OUT is equal to 0 because D is 0. cases.
This process yields the FM0 ‘0’ symbol with high-low transition
when the leading bit is 0. On the other hand, when the leading bit
is 1 and when CLK_new is high, FM0_OUT is equal to . . Therefore, the uplink data rate is around 53.3 kbps to
Later, after CLK_new goes low, FM0_OUT is still equal to 1 106.7 kbps.
because D is 0. This process yields the FM0 ‘1’ symbol with
logic high when the leading bit is 1. It is noted that the Fig. F. Backscatter Circuit
12(c) encoder always generate the first symbol of FM0 starting
from logic high. After the first symbol, ‘check’ remains high Fig. 14(a) shows the backscatter transistor shunted
and the encoder operates following the state diagram shown in across the input of the charge-pump and the ground node. The
the Fig. 12(b). Fig. 13 shows two sets of illustration waveforms FM0 signal controls the gate of . If the FM0 signal is high,
of the FM0 encoder for the received leading bit equal to 0 and charge pump’s input impedance will not match the antenna’s
1, respectively. impedance and the high-band CW wave will be reflected.
The uplink data rate can be derived as follows. Since the clock On the other hand, if the FM0 signal is low, charge pump’s
rate for backscattering is a half of the rate of the downlink PIE input impedance will match the antenna’s impedance and the
0, one FM0 symbol duration is in the range from to high-band CW power can charge the tag up effectively.
YAO AND HSIA: – -DBM DUAL-CHANNEL UHF PASSIVE CMOS RFID TAG DESIGN 1275

TABLE I
PVT VARIATION PASS/FAIL RESULTS OF THE FULL CHIP SIMULATIONS.

The measured return loss of the charge pump circuit is shown

in Fig. 14(b). At 925-MHz, the matched return loss is less than
, while the unmatched return loss is around .
Fig. 15. Die photograph of the proposed tag IC.
G. Full-Chip Simulations for PVT Variations
Table I summarizes the full-chip simulation results at dif-
work, one Tari is . Fig. 16 shows the setup for the
ferent process corners and at different power levels of the power
tag IC sensitivity test. Two Agilent’s E4438C ESG vector
link. First, we consider the SS and TT corners because the FF na-
signal generators were employed. The bottom one generates
tive NMOS devices in the charge pump do not work efficiently.
the 433-MHz ASK-modulated 15-bit PIE signal. The top one
Above the room temperature, the proposed tag works well with
generates the 925-MHz CW power link signal. They are con-
power link levels varying from to 10 dBm in simula-
nected to the corresponding input ports of the tag under
tions. At , the power link levels that the tag can work vary
test (TUT) via coaxial cables. The tag’s FM0 output signal
from to 0 dBm.
is connected to the oscilloscope such that we can observe
Next, we also simulate the FF situations. Since the delay
whether the tag’s function is correct or not.
amount of the delay line in the PIE-to-binary decoder is not
Fig. 16(a) shows the low power case for measuring the sen-
sufficient at the FF- corner, the power-link levels that the
sitivity. The output power shown on the top signal generator is
tag can work are within a narrow range from to
. Since the cable loss is 0.7 dB at 925 MHz, the
only. On the other hand, at the FF- corner, the
power level at the tag’s 925-MHz port is . On the
delay amount of the delay line increases such that the working
other hand, the output power shown on the bottom signal gener-
power-link range of the tag is widened. However, because the
ator is . Taking the cable loss (0.5 dB at 433 MHz)
efficiency of the charge pump with the FF native devices is
into account, we can determine that the power level at the tag’s
poor, the lower bound of the working power-link range is only
433-MHz port is . Fig. 16(b) shows the high power
.
case for investigating the maximum received power that our tag
At the FF corner, the tag performs not so good as the tag at
can work. The output power shown on the top signal generator
the other corners. Fortunately, TSMC’s 0.18- CMOS process
is 10.5 dBm. Thus, the power level at the tag’s 925-MHz port
is a matured technology. The characteristics of the transistors
is 9.8 dBm. On the other hand, the output power shown on the
in most dies are close to the TT case. In the next section, the
bottom signal generator is . Thus, the power level at
measurement results show that the tags work well at the room
the tag’s 433-MHz port is . It is noted that the mea-
temperature with the power-link range from to 9.8
sured high power case for the 925-MHz port is 0.2 dB worse
dBm.
than the simulation result shown in Fig. 8(b) where 10-dBm RF
input power is assumed. Since the intended application is the
IV. MEASUREMENT RESULTS AND DISCUSSIONS indoor positioning system using passive RFID. We don’t really
Fig. 15 shows the die photo of the proposed tag IC which is worry about the nearly 10-dBm high power limitation in such
realized in TSMC 0.18- CMOS process. The building blocks applications.
of the tag mentioned in the previous section are located in the Fig. 17 shows some signals measured at the tag’s output pins,
upper part of the chip. In the lower part of the chip, we put a where ‘ ’ is the inverted demodulated PIE signal, ‘Binary’
78.5-pF on-chip capacitor as a part of the storage capacitor. is the decoded binary waveform, and ‘ ’ is the FM0 control
First, we measured the sensitivity of the proposed tag by signal. The tag’s FM0 output waveform is exactly the same as
directly connecting the test equipment to the tag. In this the code we use to modulate the 433-MHz signal.
1276 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 4, APRIL 2014

Fig. 17. (a) Measured results at -dBm RF charging power and -dBm
data link signal power. The 15-bit tag ID is . (b) Mea-
sured results with different leading bit of the tag ID: .

TABLE II
POWER CONSUMPTIONS OF ALL BUILDING BLOCKS OF THE PROPOSED TAG BY
POST-LAYOUT SIMULATION.

the voltage across the VR had a similar VDD value (around 0.76
V) as the tag VDD value in the previous sensitivity experiment.
Next, the resistance value of the VR was measured and its value
was . Thus, the power delivered to the VR is .
Since the input power is at –21.2-dBm , the efficiency
Fig. 16. (a) Measurement of the sensitivity for the proposed tag when one
Tari is . (b) Measurement of the maximum input power that the
is 43.26%.
proposed tag can work when one Tari is . Next, we employed the post-layout simulation results to
estimate the power consumption of the tag’s core circuit.
Table II shows the power consumptions of all building blocks
Next, we measured the efficiency of the charge pump circuit. at -dBm 925-MHz CW input power. The simulated total
We removed the off-chip capacitor and connected a variable re- power consumption of the core circuit is .
sistor (VR) across the charge pump output pins (VDD pin and Fig. 18 shows the limiter output (VDD) of the proposed tag
GND pin). The 433-MHz port of the tag was terminated such for different 925-MHz input power levels. The VDD is around
that the tag was shut down except the charge pump, limiter, 0.76 V at -dBm received power. The VDD is around 1.34
and POR circuit. The 925-MHz port was connected to the Ag- V at 9.8-dBm received power. We see that our tag can work in
ilent’s E4438C ESG vector signal generator. The output power a wide VDD range at room temperature.
level of the signal generator was set to . Taking the Finally, we proceeded with the OTA test. The setup is shown
0.7 dB cable loss into account, the 925-MHz port of the tag re- in Fig. 19. The TUT was stuck on the white cylinder in an
ceived -dBm power. We then adjusted the VR such that anechoic chamber. A horn antenna on the right side transmitted
YAO AND HSIA: – -DBM DUAL-CHANNEL UHF PASSIVE CMOS RFID TAG DESIGN 1277

TABLE III
OTA TEST RESULTS.

are different. Nevertheless, the OTA test results are close to the
directly connected measured results.
Fig. 18. Measured VDD of the proposed tag for different 925-MHz input Table IV shows the comparison of performance between the
power levels. proposed tag and the tags reported in the recent literatures. Since
the downlink data is of PIE form, the symbol ‘1’ and symbol
‘0’ have different time duration. Hence, it is hard to define the
downlink data rate. Because [13] specifies that the duration of
a PIE symbol ‘0’ should be in the range of to ,
[7], [8], [16] take inverse of the above two numbers to obtain
the downlink data rate of their tags as 40 kbps to 160 kbps.
In this paper, we assume that symbol ‘0’ and symbol ‘1’ are
equally probable. The downlink data rate of our tag is derived
in Section III-C. If we employ the same convention used in [7],
[8], [16], the downlink data rate of our tag will be 106.7 kbps
to 160 kbps. On the other hand, the backscattered uplink of the
proposed tag uses narrow-band ASK. Since the clock rate for
the uplink operation is a half of the rate of the downlink PIE
symbol ‘0’, the uplink data rate of the proposed tag is lower
than the uplink data rate given in [7], [8], [16].
The sensitivity, the corresponding distance, and the power ef-
ficiency of the tags are also summarized in Table IV. The pro-
Fig. 19. Setup for the OTA test of the proposed tag.
posed tag outperforms the other CMOS tags in terms of the
receiver sensitivity. The distance is calculated by employing
36-dBm EIRP and 0.4-dBi receiver antenna gain in the path-loss
the 925-MHz CW signal to charge the tag up. A standard DB4 formula. On the other hand, the power efficiency of the proposed
433-MHz antenna on the left side transmitted the ASK-mod- tag is higher than the other tags whose efficiency data are avail-
ulated PIE signal to the tag. Two Agilent’s E4438C ESG able in the literature.
vector signal generators were employed as the 925-MHZ and
433-MHz transmitters, respectively. The distance between the
A. Estimated Sensitivity of the Reader for the Proposed Tag
antennas and the TUT was 2.05 m, which was longer than the
433-MHz far field distance (1.38 m). The tag’s output signals Having the power link measurement result, we can estimate
were measured by a digital phosphor oscilloscope (DPO). The the required reader sensitivity for our tag. Assume that the EIRP
transmitting powers of both 925-MHz CW signal and 433-MHz of the reader’s 925-MHz transmitter is 36 dBm. Since the tag’s
ASK-modulated signal were carefully increased from 0 dBm sensitivity is , the difference is . We em-
until the tag’s outputs measured by the DPO were correct. ploy to estimate the loss of modulation efficiency. This
Since the distance, the EIRP of the transmitter, and the value was recommended in Fig. 3.23 of [1]. We assume that the
antenna gain of TUT are known, we can use the free-space distance between the reader and the tag remains unchanged in a
path loss formula to calculate the received signal strength at short period of time; i.e., the uplink suffers from the same path
the TUT, which corresponds to the OTA sensitivity of the loss as the downlink. Thus, we subtract 57.2 dB from our result
tag. The OTA experimental results are shown in Table III. and obtain that the reader’s sensitivity requirement is around
We obtain -dBm sensitivity for the 433-MHz band . Fig. 20 shows the link budget calculation for esti-
and -dBm sensitivity for the 925-MHz band. The OTA mating the required reader sensitivity.
test results are slightly different from the directly connected It is noted that the state-of-the-art Impinj R2000 reader chip
measured results. The reasons are twofold. First, the antenna can achieve sensitivity [17]. Our estimation of the
beam alignment is not perfect. Second, the TUT’s matching required reader sensitivity for the proposed tag is around 10 dB
circuit to the antennas for the OTA test and the TUT’s matching higher than that of the R2000 chip. Therefore, the design of the
circuit to for the directly connected measurement are corresponding reader chip will be easier than the design of the
different. Thus, the losses introduced into the two experiments R2000 chip.
1278 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 4, APRIL 2014

TABLE IV
PERFORMANCE COMPARISON WITH RECENTLY PUBLISHED RESULTS

at the 925-MHz CW channel and at the

433-MHz downlink data channel. This result outperforms the
existing passive UHF CMOS tags reported recently. The max-
imal received power that our tag can work is 9.8 dBm. Although
this power level is lower than 20 dBm specified in the EPC stan-
dard, it won’t trouble us in the intended application that is not
covered by the EPC standard. The power efficiency of the pro-
posed tag is 43.26% at -dBm CW input power level. The
simulated core circuit power consumption is , also at
-dBm CW input power level. The OTA test was also done
in this work. The OTA test results are close to those in the di-
rectly connected measurement.

ACKNOWLEDGMENT
Fig. 20. Link budget calculation for estimating the required reader sensitivity.
The authors would like to thank the Chip Implementation
Center (CIC) of Taiwan, for fabricating the tag chips used in
this work.
V. CONCLUSIONS
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is working toward the Ph.D. degree in electrical en-
gineering at National Taiwan University of Science
and Technology, Taipei, Taiwan.
During 2000–2002, he served in the Taiwanese
Navy. From 2004 to 2008, he was with Quanta
Technology Corporation and Asus Corporation as an RF Design Engineer. His
research interest is CMOS RFIC design.