NOR Latch Reprt

A Project Report on
NOR LATCH
Backend design of NOR Latch using Synopsys Tools
2021-2025
Submitted By:
21WH1A0461 - E. Amulya
21WH1A0465 - P. Varshitha
21WH1A0467 - A. Sreeja
Submitted To
Dr. T. Thammi Reddy
Associate Professor
ECE Department
BVRIT HYDERABAD College of Engineering for Women

Plot No. 8-5/4, Rajiv Gandhi Nagar Colony, Nizampet Rd,
Bachupally,
Hyderabad-500090
ACKNOWLEDGEMENT
We would like to express our sincere gratitude to all those who have contributed
to design the NOR latch.
First and foremost, we extend our heartfelt thanks to our supervisor, Dr.T.
Thammi Reddy, for their invaluable guidance, support, and mentorship
throughout the duration of this project. Their expertise and encouragement have
been instrumental in shaping the direction of our research and ensuring its
successful completion.
I would also like to thank BVRIT HYDERABAD College of Engineering

for Women for providing the necessary resources and a conducive environment
for conducting this project. The access to Synopsys tools and the support from
the technical staff were pivotal in the smooth progression of the design and
implementation phases.
Furthermore, we would like to acknowledge the contributions of our
teammates and collaborators who provided assistance and encouragement at
various stages of this project. Their collaboration and camaraderie have been
essential in overcoming challenges and achieving our goals.
This project would not have been possible without the collective efforts and
support of all those mentioned above.
ABSTRACT
This report details the comprehensive process of designing and

physically implementing an SR (Set-Reset) latch using NOR gates,
leveraging the capabilities of Synopsys Custom Compiler. The SR latch is a
fundamental bistable multivibrator circuit, pivotal in digital electronics for
storing binary information. The project's primary objective was to design a
robust and optimized SR latch that meets industry standards for
performance, power consumption, and area efficiency.
The project commenced with the design and schematic capture of

the SR latch at the transistor level. The schematic, consisting of two cross-
coupled NOR gates, was created using CMOS technology with PMOS and
NMOS transistors. Pre-layout simulations were conducted to verify the
latch’s functional correctness, ensuring that the latch sets and resets
accurately in response to the S (Set) and R (Reset) inputs.
Following the successful verification of the schematic, the project

progressed to the physical design phase. The layout design involved
strategic placement and routing of transistors to minimize parasitic effects
while adhering to strict design rules. Critical steps in this phase included
Design Rule Check (DRC) and Layout Versus Schematic (LVS) to ensure
manufacturability and accurate representation of the schematic.
In conclusion, the project demonstrates the successful physical

design of an SR latch using NOR gates, utilizing Synopsys Custom
Compiler. The final design meets the performance criteria, making it a
viable component for digital systems. Future work could focus on further
optimization, temperature variation analysis, and scalability across
different technology nodes to enhance performance and integration
capabilities.
Table of contents:
1.Introduction
2.Project Description
3.Methodology
4.Design and Implementation
5.Results
6.Conclusion
7.References
1.Introduction
The Set-Reset (SR) latch is a fundamental storage element

in digital electronics, used to store a single bit of data. This
project focuses on the physical design of an SR latch using NOR
gates, implemented and optimized with Synopsys Custom
Compiler. The report details the entire design process, from
schematic capture to layout and optimization, including the use
of analog simulations to validate the performance and
functionality of the SR latch.
The S-R NOR latch has two inputs: S and R (SET and RESET) and two
outputs: Q and not Q. The Q is the normal output and not Q is the
complemented output.
Any latch has two states: SET and RESET (CLEAR). When Q = 1, we say the
latch is in the SET state. When Q = 0, the latch is in the RESET state.
Figure 11.1 shows the construction of a NOR latch.
The truth table below (Table 11.1) describes the characteristics of this NOR
latch.
A NOR latch has active-high inputs. When both inputs are low (S=0, R=0), the
output will not change. It is “latched”. Normally, one of the inputs in it could be
set to high to “set” or “clear” the latch. Yet if both inputs are high (S=1 and
R=1),
both outputs will be low, which is not valid since Q and not-Q should be
opposites.
2.Project Description
The primary goals of this project are to:
 Design an SR latch using NOR gates at the transistor level.

 Verify the functional correctness of the SR latch through pre-layout
simulations.
 Perform the physical design, including the placement of transistors,
routing of interconnections, and verification of the layout.
 Conduct post-layout simulations to ensure that the design meets
performance criteria under real-world conditions.
 Optimize the design to balance speed, power consumption, and area
efficiency.
The significance of this project lies in its comprehensive

approach to the physical design process. By meticulously
following each step from schematic capture to layout and
optimization, the project aims to produce a high-quality SR
latch that can serve as a reliable component in larger digital
systems. This report documents the detailed methodology,
results, and challenges encountered during the design process,
providing insights into the complexities and trade-offs involved
in modern IC design.
3.METHODOLOGY
3.1.Circuit Design and Schematic Capture
The SR latch is designed using two cross-coupled NOR gates. Each NOR
gate is implemented using CMOS technology with PMOS and NMOS
transistors. The schematic is captured in the Synopsys Custom Compiler
environment.
3.2 Pre-Layout Simulation
Before layout generation, the schematic undergoes pre-layout simulations to

verify the SR latch’s correct operation. These simulations ensure the latch sets
and resets as expected, responding accurately to S (Set) and R (Reset) inputs .
4.Design and Implementation

CMOS based NOR Latch
Step 1: Design specs
NOR Latch circuit for simulation

Step 2: Schematic Capture
Inverter symbol creation

Step 3: Symbol Creation
Inverter simulation setup
Step 4: Schematic simulation
5.RESULT
The waveform below shows the operation of SR Latch
based NOR
gates.
6.Conclusion
The project successfully demonstrates the physical design
of an SR latch using NOR gates, utilizing Synopsys Custom
Compiler for schematic capture and layout design. The design
meets the required performance criteria, making it suitable for
integration into digital systems. The iterative optimization
process ensures a balance between speed, power, and area
efficiency.
7.References
 Synopsys Custom Compiler Documentation

 "CMOS VLSI Design: A Circuits and Systems Perspective" by Neil H.E.
Weste and David Harris
 "Digital Integrated Circuits: A Design Perspective" by Jan M. Rabaey
This detailed report outlines the comprehensive process of designing and

implementing an SR latch using NOR gates, from schematic capture to physical
layout and optimization. The successful implementation highlights the
importance of iterative design and validation in developing high-performance
digital circuits.

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A Project Report on

Backend design of NOR Latch using Synopsys Tools

BVRIT HYDERABAD College of Engineering for Women

I would also like to thank BVRIT HYDERABAD College of Engineering

This report details the comprehensive process of designing and

The project commenced with the design and schematic capture of

Following the successful verification of the schematic, the project

In conclusion, the project demonstrates the successful physical

4.Design and Implementation

The Set-Reset (SR) latch is a fundamental storage element

 Design an SR latch using NOR gates at the transistor level.

The significance of this project lies in its comprehensive

Before layout generation, the schematic undergoes pre-layout simulations to

4.Design and Implementation

NOR Latch circuit for simulation

Inverter symbol creation

 Synopsys Custom Compiler Documentation

This detailed report outlines the comprehensive process of designing and

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