AT24C16C Data Sheet 20006051A

AT24C16C
I²C-Compatible (2-Wire) Serial EEPROM 16‑Kbit (2,048 x 8)
Features
• Low-Voltage Operation:
– VCC = 1.7V to 5.5V
• Internally Organized as 2,048 x 8 (16K)
• Industrial Temperature Range: -40°C to +85°C
• I2C-Compatible (2-Wire) Serial Interface:
– 100 kHz Standard mode, 1.7V to 5.5V
– 400 kHz Fast mode, 1.7V to 5.5V
– 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• Write-Protect Pin for Full Array Hardware Data Protection
• Ultra Low Active Current (3 mA maximum) and Standby Current (6 μA maximum)
• 16-Byte Page Write Mode:
– Partial page writes allowed
• Random and Sequential Read Modes
• Self-Timed Write Cycle within 5 ms Maximum
• ESD Protection > 4,000V
• High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
• Green Package Options (Lead-free/Halide-free/RoHS compliant)
• Die Sale Options: Wafer Form
Packages
• 8-Lead PDIP, 8-Lead SOIC, 5-Lead SOT23, 8-Lead TSSOP, 8-Pad UDFN, 8-Pad XDFN
and 8‑Ball VFBGA
© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 1

AT24C16C
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Descriptions.........................................................................................................5
2.1. Ground......................................................................................................................................... 5
2.2. Serial Data (SDA).........................................................................................................................5
2.3. Serial Clock (SCL)........................................................................................................................5
2.4. Write-Protect (WP)....................................................................................................................... 5
2.5. Device Power Supply................................................................................................................... 6
3. Description.................................................................................................................7
3.1. System Configuration Using 2-Wire Serial EEPROMs.................................................................7
3.2. Block Diagram.............................................................................................................................. 8
4. Electrical Characteristics........................................................................................... 9
4.1. Absolute Maximum Ratings..........................................................................................................9
4.2. DC and AC Operating Range.......................................................................................................9
4.3. DC Characteristics....................................................................................................................... 9
4.4. AC Characteristics......................................................................................................................10
4.5. Electrical Specifications..............................................................................................................11
5. Device Operation and Communication....................................................................13

5.1. Clock and Data Transition Requirements...................................................................................13
5.2. Start and Stop Conditions.......................................................................................................... 13
5.3. Acknowledge and No-Acknowledge...........................................................................................14
5.4. Standby Mode............................................................................................................................ 14
5.5. Software Reset...........................................................................................................................15
6. Memory Organization.............................................................................................. 16
6.1. Device Addressing..................................................................................................................... 16
7. Write Operations......................................................................................................17
7.1. Byte Write...................................................................................................................................17
7.2. Page Write..................................................................................................................................17
7.3. Acknowledge Polling.................................................................................................................. 18
7.4. Write Cycle Timing..................................................................................................................... 18
7.5. Write Protection..........................................................................................................................19
8. Read Operations..................................................................................................... 20
8.1. Current Address Read................................................................................................................20
8.2. Random Read............................................................................................................................ 20
8.3. Sequential Read.........................................................................................................................21

AT24C16C
9. Device Default Condition from Microchip................................................................ 22
10. Packaging Information.............................................................................................23

10.1. Package Marking Information.....................................................................................................23
11. Revision History.......................................................................................................37
The Microchip Web Site................................................................................................ 38
Customer Change Notification Service..........................................................................38
Customer Support......................................................................................................... 38
Product Identification System........................................................................................ 39
Microchip Devices Code Protection Feature................................................................. 39
Legal Notice...................................................................................................................40
Trademarks................................................................................................................... 40
Quality Management System Certified by DNV.............................................................41
Worldwide Sales and Service........................................................................................42

AT24C16C
Package Types (not to scale)
1. Package Types (not to scale)

8-Lead PDIP/SOIC/TSSOP
(Top View)
5-Lead SOT23
NC 1 8 Vcc (Top View)
NC 2 7 WP SCL 1 5 WP
NC 3 6 SCL GND 2
GND 4 5 SDA SDA 3 4 Vcc
8-Ball VFBGA
(Top View) 8-Pad UDFN/XDFN
(Top View)
NC 1 8 Vcc
NC 1 8 Vcc
NC 2 7 WP
NC 2 7 WP
NC 3 6 SCL NC 3 6 SCL
GND 4 5 SDA GND 4 5 SDA

AT24C16C
Pin Descriptions
2. Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name 8-Lead 8-Lead 8-Lead 5-Lead 8-Pad 8-Ball 8-Pad Function
PDIP SOIC TSSOP SOT23 UDFN(1) VFBGA XDFN
NC 1 1 1 － 1 1 1 No Connect
GND 4 4 4 2 4 4 4 Ground
SDA 5 5 5 3 5 5 5 Serial Data
SCL 6 6 6 1 6 6 6 Serial Clock
WP(2) 7 7 7 5 7 7 7 Write-Protect
VCC 8 8 8 4 8 8 8 Device Power
Supply
Note:
1. The exposed pad on this package can be connected to GND or left floating.
2. If the WP pin is not driven, it is internally pulled down to GND. In order to operate in a wide variety
of application environments, the pull-down mechanism is intentionally designed to be somewhat
strong. Once this pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down
mechanism disengages. Microchip recommends connecting this pin to a known state whenever
possible.
2.1 Ground
The ground reference for the power supply. GND should be connected to the system ground.
2.2 Serial Data (SDA)

The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the
device. The SDA pin must be pulled-high using an external pull-up resistor (not to exceed 10 kΩ in value)
and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on
the same bus.
2.3 Serial Clock (SCL)

The SCL pin is used to provide a clock to the device and to control the flow of data to and from the
device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL,
while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be
forced high when the serial bus is idle or pulled high using an external pull-up resistor.
2.4 Write-Protect (WP)

The write-protect input, when connected to GND, allows normal write operations. When the WP pin is
connected directly to VCC, all write operations to the protected memory are inhibited.

AT24C16C
Pin Descriptions
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive
coupling that may appear in customer applications, Microchip recommends always connecting the WP
pin to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
Table 2-2. Write-Protect
WP Pin Status Part of the Array Protected

At VCC Full Array
At GND Normal Write Operations
2.5 Device Power Supply

The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may
produce spurious results and should not be attempted.

AT24C16C
Description
3. Description
The AT24C16C provides 16,384 bits of Serial Electrically Erasable and Programmable Read-Only
Memory (EEPROM) organized as 2,048 words of 8 bits each. This device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operations are essential. The
device is available in space-saving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, 5-lead
SOT23, 8-ball VFBGA and 8-pad XDFN packages. All packages operate from 1.7V to 5.5V.
3.1 System Configuration Using 2-Wire Serial EEPROMs

VCC
tR(max)
RPUP(max) =
0.8473 x CL
V - VOL(max)
VCC RPUP(min) = CC
IOL
SCL
SDA
WP
I2C Bus Master:

Microcontroller
NC VCC
NC Slave WP
NC AT24Cxxx SDA
GND SCL
GND

AT24C16C
Description
3.2 Block Diagram
Memory POR
Generator VCC
System Control
Module
High-Voltage
Generation Circuit
Write
Protection WP
Row Decoder
Control
EEPROM Array
Address Register
1 page and Counter
Column Decoder
SCL
Data Register
Start
Stop
Data & ACK Detector
DOUT Input/Output Control
DIN
GND SDA

AT24C16C
Electrical Characteristics
4. Electrical Characteristics
4.1 Absolute Maximum Ratings

Temperature under bias -55°C to +125°C
Storage temperature -65°C to +150°C
VCC 6.25V
Voltage on any pin with respect to ground -1.0V to +7.0V
DC output current 5.0 mA
ESD protection >4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification are not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range
AT24C16C
Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C
VCC Power Supply Low Voltage Grade 1.7V to 5.5V
4.3 DC Characteristics
Table 4-2. DC Characteristics
Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions

Supply VCC 1.7 — 5.5 V
Voltage
Supply ICC1 — 0.4 1.0 mA VCC = 5.0V, Read at
Current 100 kHz
Supply ICC2 — 2.0 3.0 mA VCC = 5.0V, Write at
Current 100 kHz
Standby ISB — — 1.0 μA VCC = 1.7V, VIN = VCC or
Current GND
— — 6.0 μA VCC = 5.5V, VIN = VCC or
GND

AT24C16C
Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions

Input ILI — 0.10 3.0 μA VIN = VCC or GND
Leakage
Current
Output ILO — 0.05 3.0 μA VOUT = VCC or GND
Leakage
Current
Input Low VIL -0.6 — VCC x 0.3 V Note 2
Level
Input High VIH VCC x 0.7 — VCC + 0.5 V Note 2
Level
Output Low VOL1 — — 0.2 V VCC = 1.7V, IOL = 0.15 mA
Level
Output Low VOL2 — — 0.4 V VCC = 3.0V, IOL = 2.1 mA
Level
Note:
1. Typical values characterized at TA = +25°C unless otherwise noted.
2. This parameter is characterized but is not 100% tested in production.
4.4 AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter Symbol 1.7V 2.5V, 2.7V, 5.0V Units
Min. Max. Min. Max.
Clock Frequency, fSCL — 400 — 1000 kHz
SCL
Clock Pulse Width tLOW 1,200 — 500 — ns
Low
Clock Pulse Width tHIGH 600 — 400 — ns
High
Input Filter Spike tI — 100 — 50 ns
Suppression
Clock Low to Data tAA 100 900 50 450 ns
Out Valid
Bus Free Time tBUF 1,200 — 500 — ns
between Stop and
Start
Start Hold Time tHD.STA 600 — 250 — ns
Start Set-Up Time tSU.STA 600 — 250 — ns
Data In Hold Time tHD.DAT 0 — 0 — ns
Data In Set-up tSU.DAT 100 — 100 — ns
Time

AT24C16C
Parameter Symbol 1.7V 2.5V, 2.7V, 5.0V Units

Min. Max. Min. Max.
Inputs Rise Time(2) tR — 300 — 300 ns
Inputs Fall Time(2) tF — 300 — 100 ns
Stop Set-Up Time tSU.STO 600 — 250 — ns
Data Out Hold tDH 50 — 50 — ns
Time
Write Cycle Time tWR — 5 — 5 ms
Note:
1. AC measurement conditions:
– CL: 100 pF
– RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz),
10 kΩ (100 kHz)
– Input rise and fall times: ≤50 ns
– Input and output timing reference voltages: 0.5 x VCC
2. These parameters are determined through product characterization and are not 100% tested in
production.
Figure 4-1. Bus Timing
tHIGH
tF tR
tLOW
SCL
tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO
SDA In
tAA tBUF
tDH
SDA Out
4.5 Electrical Specifications
4.5.1 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT24C16C should monotonically rise from GND to
the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.5.1.1 Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT24C16C includes a Power-on Reset (POR) circuit. Upon power-up, the device will not
respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the
device out of Reset and into Standby mode.

AT24C16C
The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the
first command to the device. See Table 4-4 for the values associated with these power-up parameters.
Table 4-4. Power-up Conditions(1)
Symbol Parameter Min. Max. Units

tPUP Time required after VCC is stable before the device can accept commands 100 － µs
VPOR Power-on Reset Threshold Voltage — 1.5 V
tPOFF Minimum time at VCC = 0V between power cycles 500 — ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C16C drops below the
maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first
driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up
sequence in compliance with the requirements defined in this section.
4.5.2 Pin Capacitance

Table 4-5. Pin Capacitance(1)
Symbol Test Condition Max. Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (SCL) 6 pF VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
4.5.3 EEPROM Cell Performance Characteristics

Table 4-6. EEPROM Cell Performance Characteristics
Operation Test Condition Min. Max. Units

Write Endurance(1) TA = 25°C, VCC = 3.3V, 1,000,000 — Write Cycles
Page Write mode
Data Retention(1) TA = 55°C 100 — Years
Note:
1. Performance is determined through characterization and the qualification process.

AT24C16C
Device Operation and Communication
5. Device Operation and Communication

The AT24C16C operates as a slave device and utilizes a simple I2C-compatible 2-wire digital serial
interface to communicate with a host controller, commonly referred to as the bus master. The master
initiates and controls all read and write operations to the slave devices on the serial bus, and both the
master and the slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA).
The SCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used to
receive command and data information from the master as well as to send data back to the master. Data
is always latched into the AT24C16C on the rising edge of SCL and always output from the device on the
falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and
Schmitt Triggers to minimize the effects of input spikes and bus noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have
been transferred, the receiving device must respond with either an Acknowledge (ACK) or a
No-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by
the master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no
unused clock cycles during any read or write operation, so there must not be any interruptions or breaks
in the data stream during each data byte transfer and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain
stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop
condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication
between the master and the slave devices. The number of data bytes transferred between a Start and a
Stop condition is not limited and is determined by the master. In order for the serial bus to be idle, both
the SCL and SDA pins must be in the logic-high state at the same time.
5.1 Clock and Data Transition Requirements

The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor.
SCL is an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on
the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will
indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters with
respect to SCL and SDA for the AT24C16C are shown in the timing waveform in Figure 4-1. The AC
timing characteristics and specifications are outlined in 4.4 AC Characteristics.
5.2 Start and Stop Conditions
5.2.1 Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a
stable logic ‘1’ state and will bring the device out of Standby mode. The master uses a Start condition to
initiate any data transfer sequence; therefore, every command must begin with a Start condition. The
device will continuously monitor the SDA and SCL pins for a Start condition but will not respond unless
one is detected. Refer to Figure 5-1 for more details.
5.2.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable
in the logic ‘1’ state.

AT24C16C
The master can use the Stop condition to end a data transfer sequence with the AT24C16C, which will
subsequently return to Standby mode. The master can also utilize a repeated Start condition instead of a
Stop condition to end the current data transfer if the master will perform another operation. Refer to
Figure 5-1 for more details.
5.3 Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it
has successfully received the data byte by responding with what is known as an Acknowledge (ACK). An
ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the
eighth clock cycle followed by the receiving device responding with a logic ‘0’ during the entire high period
of the ninth clock cycle.
When the AT24C16C is transmitting data to the master, the master can indicate that it is done receiving
data and wants to end the operation by sending a logic ‘1’ response to the AT24C16C instead of an ACK
response during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished
by the master sending a logic ‘1’ during the ninth clock cycle, at which point the AT24C16C will release
the SDA line so the master can then generate a Stop condition.
The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line
at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’
to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth
clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in
Figure 5-1 to better illustrate these requirements.
Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge
SDA SDA
Must Be Must Be
Acknowledge Window
Stable Stable
1 2 8 9
SCL
SDA
Acknowledge Stop
Start Valid Condition
Condition The transmitting device (Master or Slave) The receiver (Master or Slave)
SDA SDA must release the SDA line at this point to allow must release the SDA line at
Change Change the receiving device (Master or Slave) to drive the this point to allow the transmitter
Allowed Allowed SDA line low to ACK the previous 8-bit word. to continue sending new data.
5.4 Standby Mode

The AT24C16C features a low-power Standby mode that is enabled when any one of the following
occurs:
• A valid power-up sequence is performed (see 4.5.1 Power-Up Requirements and Reset Behavior).
• A Stop condition is received by the device unless it initiates an internal write cycle (see 7. Write
Operations).
• At the completion of an internal write cycle (see 7. Write Operations).

AT24C16C
5.5 Software Reset

After an interruption in protocol, power loss or system Reset, any 2‑wire device can be protocol reset by
clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA
is released by the EEPROM will vary. The software Reset sequence should not take more than nine
dummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to the
device by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.
Figure 5-2. Software Reset
Dummy Clock Cycles
SCL 1 2 3 8 9
SDA Released Device is

by EEPROM Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must
be used to reset the device (see 4.5.1 Power-Up Requirements and Reset Behavior).

AT24C16C
Memory Organization
6. Memory Organization
The AT24C16C is internally organized as 128 pages of 16 bytes each.
6.1 Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the
device for a read or write operation.
The Most Significant four bits of the device address byte is referred to as the device type identifier. The
device type identifier '1010' (Ah) is required in bits 7 through 4 of the device address byte (see Table 6-1).
Following the 4-bit device type identifier in the bit 3, bit 2 and bit 1 position of the device address byte are
bits A10, A9 and A8 which are the three Most Significant bits of the memory array word address.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24C16C will return an ACK. If a valid
comparison is not made, the device will NACK.
Table 6-1. Device Address Byte
Package Device Type Identifier Most Significant Bits R/W Select

of the Word Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All Package Types 1 0 1 0 A10 A9 A8 R/W
For all operations except the current address read, a word address byte must be transmitted to the device
immediately following the device address byte. The word address byte consists of the remaining eight bits
of the 11-bit memory array word address, and is used to specify which byte location in the EEPROM to
start reading or writing. Refer to Table 6-2 to review these bit positions.
Table 6-2. Word Address Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A7 A6 A5 A4 A3 A2 A1 A0

AT24C16C
Write Operations
7. Write Operations
All write operations for the AT24C16C begin with the master sending a Start condition, followed by a
device address byte with the R/W bit set to logic '0', and then by the word address byte. The data value(s)
to be written to the device immediately follow the word address byte.
7.1 Byte Write

The AT24C16C supports the writing of a single 8-bit byte. Selecting a data word in the AT24C16C
requires an 11-bit word address.
Upon receipt of the proper device address and the word address bytes, the EEPROM will send an
Acknowledge. The device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit
data word, the EEPROM will respond with an ACK. The addressing device, such as a bus master, must
then terminate the write operation with a Stop condition. At that time, the EEPROM will enter an internally
self-timed write cycle, which will be completed within tWR, while the data word is being programmed into
the nonvolatile EEPROM. All inputs are disabled during this write cycle, and the EEPROM will not
respond until the write is complete.
Figure 7-1. Byte Write
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
Device Address Byte Word Address Byte Data Word
SDA 1 0 1 0 A10 A9 A8 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB MSB MSB
Start Stop
ACK ACK ACK
by by
from from from
Master Master
Slave Slave Slave
7.2 Page Write

A page write operation allows up to 16 bytes to be written in the same write cycle, provided all bytes are
in the same row of the memory array (where address bits A10 through A4 are the same). Partial page
writes of less than 16 bytes are also allowed.
A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data
word, the bus master can transmit up to fifteen additional data words. The EEPROM will respond with an
ACK after each data word is received. Once all data to be written has been sent to the device, the bus
master must issue a Stop condition (see Figure 7-2) at which time the internally self-timed write cycle will
begin.
The lower four bits of the word address are internally incremented following the receipt of each data word.
The higher order address bits are not incremented and retain the memory page row location. Page write
operations are limited to writing bytes within a single physical page, regardless of the number of bytes
actually being written. When the incremented word address reaches the page boundary, the address
counter will roll-over to the beginning of the same page. Nevertheless, creating a roll-over event should
be avoided as previously loaded data in the page could become unintentionally altered.

AT24C16C
Write Operations
Figure 7-2. Page Write

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
Device Address Byte Word Address Byte
SDA 1 0 1 0 A10 A9 A8 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0
MSB MSB
Start
by ACK ACK
Master from from
Slave Slave
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Data Word (n) Data Word (n+x), max of 16 without rollover
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB MSB
Stop
ACK ACK by
from from Master
Slave Slave
7.3 Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would
prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know
immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be
started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated.
This involves repeatedly sending a Start condition followed by a valid device address byte with the R/W
bit set at logic ‘0’. The device will not respond with an ACK while the write cycle is ongoing. Once the
internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or write
operation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustrate
this technique.
Figure 7-3. Acknowledge Polling Flowchart
Send Send Start

Send any Stop condition followed Did Proceed to
YES next Read or
Write condition by a valid the device
protocol. to initiate the Device Address ACK? Write operation.
Write cycle. byte with R/W = 0.
NO
7.4 Write Cycle Timing

The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that
begins the internal write cycle to the Start condition of the first device address byte sent to the AT24C16C
that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement.

AT24C16C
Write Operations
During the internally self-timed write cycle, any attempts to read from or write to the memory array will not
be processed.
Figure 7-4. Write Cycle Timing
SCL 8 9 9
Data Word n
SDA D0 ACK ACK
First Acknowledge from the device

to a valid device address sequence after
tWR write cycle is initiated. The minimum tWR
can only be determined through
Stop Start the use of an ACK Polling routine. Stop
Condition Condition Condition
7.5 Write Protection

The AT24C16C utilizes a hardware data protection scheme that allows the user to write-protect the entire
memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin
is at GND or left floating.
Table 7-1. AT24C16C Write-Protect Behavior
WP Pin Voltage Part of the Array Protected

VCC Full Array
GND None － Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation
prior to the start of an internally self-timed write cycle. Changing the WP pin state after the Stop condition
has been sent will not alter or interrupt the execution of the write cycle.
If an attempt is made to write to the device while the WP pin has been asserted, the device will
acknowledge the device address, word address and data bytes, but no write cycle will occur when the
Stop condition is issued. The device will immediately be ready to accept a new read or write command.

AT24C16C
Read Operations
8. Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write
Select bit in the device address byte must be a logic ‘1’. There are three read operations:
• Current Address Read
• Random Address Read
• Sequential Read
8.1 Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the VCC is
maintained to the part. The address roll-over during a read is from the last byte of the last page to the first
byte of the first page of the memory.
A current address read operation will output data according to the location of the internal data word
address counter. This is initiated with a Start condition, followed by a valid device address byte with the
R/W bit set to logic ’1’. The device will ACK this sequence and the current address data word is serially
clocked out on the SDA line. All types of read operations will be terminated if the bus master does not
respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may
send a Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.
Figure 8-1. Current Address Read
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
Device Address Byte Data Word (n)
SDA 1 0 1 0 A10 A9 A8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB
Start Stop
by ACK NACK by
Master from from Master
Slave Master
8.2 Random Read

A random read begins in the same way as a byte write operation does to load in a new data word
address. This is known as a “dummy write” sequence; however, the data byte and the Stop condition of
the byte write must be omitted to prevent the part from entering an internal write cycle. Once the device
address and word address are clocked in and acknowledged by the EEPROM, the bus master must
generate another Start condition. The bus master now initiates a current address read by sending a Start
condition, followed by a valid device address byte with the R/W bit set to logic ’1’. In this second device
address byte, the bit positions usually reserved for the Most Significant bits of the word address (bit 3, 2
and 1) are "don’t care" bits since the address that will be read from is determined only by what was sent
in the dummy write portion of the sequence. The EEPROM will ACK the device address and serially clock
out the data word on the SDA line. All types of read operations will be terminated if the bus master does
not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master
may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.

AT24C16C
Read Operations
Figure 8-2. Random Read

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
Device Address Byte Word Address Byte
SDA 1 0 1 0 A10 A9 A8 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0
MSB MSB
Start ACK ACK

by from from
Master Slave Slave
Dummy Write
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 0 1 0 X X X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB
Start ACK NACK Stop
by from from by
Master Slave Master Master
8.3 Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus master
receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will
continue to increment the word address and serially clock out sequential data words. When the maximum
memory address is reached, the data word address will roll-over and the sequential read will continue
from the beginning of the memory array. All types of read operations will be terminated if the bus master
does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the
master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the
next sequence.
Figure 8-3. Sequential Read
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA 1 0 1 0 A10 A9 A8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0
MSB MSB
Start
by ACK ACK
Master from from
Slave Master
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Data Word (n+1) Data Word (n+2) Data Word (n+x)
D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB MSB MSB
Stop
ACK ACK NACK by
from from from Master
Master Master Master

AT24C16C
Device Default Condition from Microchip
9. Device Default Condition from Microchip

The AT24C16C is delivered with the EEPROM array set to logic ’1’, resulting in FFh data in all locations.

AT24C16C
Packaging Information
10. Packaging Information
10.1 Package Marking Information
AT24C16C: Package Marking Information
8-lead SOIC 8-lead TSSOP 8-pad UDFN 8-pad XDFN

2.0 x 3.0 mm Body 1.8 x 2.2 mm Body
ATMLHYWW
ATHYWW ###
###% CO ###%CO H% ###
YYWWNNN YYWWNNN
NNN NNN
8-lead PDIP 5-lead SOT23 8-ball VFBGA

1.5 x 2.0 mm Body
ATMLUYWW
###% CO ##%UYY ###U
YYWWNNN WWNNN WNNN
Note 1: designates pin 1

Note 2: Package drawings are not to scale
Note 3: For SOT23 package with date codes before 7B, the bottom line (YMXX) is marked on the bottom side and there is no Country of Assembly (@) mark on the top line.
Catalog Number Truncation
AT24C16C Truncation Code ###: 16C / ##: AC
Date Codes Voltages

YY = Year Y = Year WW = Work Week of Assembly % = Minimum Voltage
16: 2016 20: 2020 6: 2016 0: 2020 02: Week 2 M: 1.7V min
17: 2017 21: 2021 7: 2017 1: 2021 04: Week 4
18: 2018 22: 2022 8: 2018 2: 2022 ...
19: 2019 23: 2023 9: 2019 3: 2023 52: Week 52
Country of Origin Device Grade Atmel Truncation
CO = Country of Origin H or U: Industrial Grade AT: Atmel
ATM: Atmel
ATML: Atmel
Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)

AT24C16C
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A
N B
E1
NOTE 1
1 2
TOP VIEW
C A A2
PLANE
L c
A1
e eB
8X b1
8X b
.010 C
SIDE VIEW END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
© 2017 Microchip Technology Incorporated

AT24C16C
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)
DATUM A DATUM A
b b
e e
2 2
e e
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2

AT24C16C
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
2X
0.10 C A–B
D
A D
NOTE 5
N
E
2
E1
2
E1 E
NOTE 1 1 2
e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C
C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW
h
R0.13
h
R0.13
H 0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

AT24C16C
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Units MILLIMETERS
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

AT24C16C
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
SILK SCREEN
Y1
X1
E
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55
Notes:
Microchip Technology Drawing C04-2057-SN Rev B

AT24C16C
/HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH 67 ±PP%RG\>76623@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
E1
NOTE 1
1 2
b
e
c
A A2 φ
A1 L1 L
8QLWV 0,//,0(7(56
'LPHQVLRQ/LPLWV 0,1 120 0$;
1XPEHURI3LQV 1
3LWFK H %6&
2YHUDOO+HLJKW $ ± ±
0ROGHG3DFNDJH7KLFNQHVV $
6WDQGRII $ ±
2YHUDOO:LGWK ( %6&
0ROGHG3DFNDJH:LGWK (
0ROGHG3DFNDJH/HQJWK '
)RRW/HQJWK /
)RRWSULQW / 5()
)RRW$QJOH ±
/HDG7KLFNQHVV F ±
/HDG:LGWK E ±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

AT24C16C

AT24C16C
e1
5 4 C
E1 E C
L
L1
1 2 3
TOP VIEW END VIEW
A2 A
SEATING
PLANE e A1
D
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does SYMBOL MIN NOM MAX NOTE
not include interlead flash or protrusion. Interlead flash or protrusion shall not
A — — 1.00
exceed 0.15 mm per side.
2. The package top may be smaller than the package bottom. Dimensions D and E1 A1 0.00 — 0.10
are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch A2 0.70 0.90 1.00
between the top and bottom of the plastic body.
c 0.08 — 0.20 3
3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15
mm from the lead tip. D 2.90 BSC 1,2
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion
shall be 0.08 mm total in excess of the "b" dimension at maximum material E 2.80 BSC 1,2
condition. The dambar cannot be located on the lower radius of the foot. Minimum
E1 1.60 BSC 1,2
space between protrusion and an adjacent lead shall not be less than 0.07 mm.
L1 0.60 REF
e 0.95 BSC
This drawing is for general information only. Refer to JEDEC e1 1.90 BSC
Drawing MO-193, Variation AB for additional information.
b 0.30 — 0.50 3,4
2/2/16
TITLE GPC DRAWING NO. REV.
5TS1, 5-lead 1.60mm Body, Plastic Thin
Shrink Small Outline Package (Shrink SOT) TSZ 5TS1 E
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.

AT24C16C
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
D A B
N
(DATUM A)
E
(DATUM B)
NOTE 1
2X
0.10 C
1 2
2X
0.10 C TOP VIEW
0.10 C A1
C
A
SEATING
PLANE 8X
(A3) 0.08 C
SIDE VIEW
0.10 C A B
D2
e
2
1 2
0.10 C A B
E2
K
N
L 8X b
e 0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
© 2017 Microchip Technology Inc.

AT24C16C
Units MILLIMETERS
Number of Terminals N 8
Pitch e 0.50 BSC
Overall Height A 0.50 0.55 0.60
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.152 REF
Overall Length D 2.00 BSC
Exposed Pad Length D2 1.40 1.50 1.60
Overall Width E 3.00 BSC
Exposed Pad Width E2 1.20 1.30 1.40
Terminal Width b 0.18 0.25 0.30
Terminal Length L 0.35 0.40 0.45
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
2. Package is saw singulated
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2

AT24C16C
X2
EV
G2
8
ØV
C Y2
G1
Y1
1 2
SILK SCREEN
X1
RECOMMENDED LAND PATTERN

Units MILLIMETERS
Contact Pitch E 0.50 BSC
Optional Center Pad Width X2 1.60
Optional Center Pad Length Y2 1.40
Contact Pad Spacing C 2.90
Contact Pad Width (X8) X1 0.30
Contact Pad Length (X8) Y1 0.85
Contact Pad to Center Pad (X8) G1 0.20
Contact Pad to Contact Pad (X6) G2 0.33
Thermal Via Diameter V 0.30
Thermal Via Pitch EV 1.00
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21355-Q4B Rev A

AT24C16C
d 0.10 (4X)
d 0.08 C
f 0.10 C
E A
C
D
2. b
j n 0.15 m C A B
j n 0.08m C
PIN 1 BALL PAD CORNER B A1

A2
TOP VIEW A
SIDE VIEW
PIN 1 BALL PAD CORNER
1 2 3 4
(d1)
8 7 6 5
e COMMON DIMENSIONS
(Unit of Measure - mm)
(e1)
SYMBOL MIN NOM MAX NOTE
BOTTOM VIEW A 0.73 0.79 0.85

8 SOLDER BALLS A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
Notes: b 0.20 0.25 0.30 2
1. This drawing is for general information only. D 1.50 BSC
E 2.0 BSC
2. Dimension ‘b’ is measured at maximum solder ball diameter. e 0.50 BSC
e1 0.25 REF
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
d 1.00 BSC
d1 0.25 REF
7/1/14
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
GXU 8U3-1 G
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)

AT24C16C
8 7 6 5
PIN #1 ID E
1 2 3 4 A1
Top View A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
0.10 A – – 0.40
PIN #1 ID A1 0.00 – 0.05
0.15 D 1.70 1.80 1.90

E 2.10 2.20 2.30
b 0.15 0.20 0.25
b e 0.40 TYP
e
e1 1.20 REF
L 0.26 0.30 0.35
End View
9/10/2012

8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN
(XDFN) DTP 8ME1 B

AT24C16C
Revision History
11. Revision History

Atmel Document 8719 Revision A (September 2010)
Initial release of this document.
Atmel Document 8719 Revision B (July 2013)

Minor grammatical corrections. Updated Atmel logos and template.
Atmel Document 8719 Revision C (January 2015)

Added the UDFN Expanded Quantity Option. Updated the 8X, 8MA2, 8P3, and 8U3-1 package outline
drawings, the ordering information section, and the disclaimer page.
Atmel Document 8719 Revision D (December 2016)

Part marking SOT23:
• Moved backside mark (YMXX) to front side line2.
• Added @ = Country of Assembly
Revision A (August 2018)

Updated to the Microchip template. Microchip DS20006051 replaces Atmel document 8719. Corrected
tLOW typo from 400 ns to 500 ns. Corrected tAA typo from 550 ns to 450 ns. Updated Part Marking
Information. Updated the "Software Reset" section. Added ESD rating. Removed lead finish designation.
Updated trace code format in package markings. Added a figure for “System Configuration Using 2‑Wire
Serial EEPROMs”. Updated "Block Diagram" figure. Added POR recommendations section. Updated
section content throughout for clarification. Updated the 5TS1 SOT23 and 8U3‑1 VFBGA package
drawings. Updated the PDIP, SOIC, TSSOP and UDFN package drawings to Microchip format.

AT24C16C
The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as
a means to make files and information easily available to customers. Accessible by using your favorite
Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support documents, latest software releases and archived
software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory
representatives
Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata
related to a specified product family or development tool of interest.
To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on
“Customer Change Notification” and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support

AT24C16C
Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
AT2 4C1 6C-SSH M-T
Shipping Carrier Option

T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Extended Quantity Option
B = Bulk (Tubes)
Product Family
24C = Standard I2C-compatible Operating Voltage
Serial EEPROM M = 1.7V to 5.5V
Device Grade or
Device Density Wafer/Die Thickness
16 = 16 Kilobit H or U = Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Device Revision
Package Option
SS = JEDEC SOIC
X = TSSOP
MA = 2.0mm x 3.0mm UDFN
ME = 1.8mm x 2.2mm XDFN
P = PDIP
ST = SOT23
C = VFBGA
WWU = Wafer Unsawn
Examples
Device Package Package Package Shipping Carrier Option Device Grade

Drawing Option
Code
AT24C16C‑PUM PDIP P P Bulk (Tubes) Industrial
Temperature
AT24C16C‑SSHM‑T SOIC SN SS Tape and Reel
(-40°C to 85°C)
AT24C16C‑STUM‑T SOT23 5TS1 ST Tape and Reel
AT24C16C‑XHM‑B TSSOP ST X Bulk (Tubes)
AT24C16C‑MAHM‑T UDFN Q4B MA Tape and Reel
AT24C16C‑MAHM‑E UDFN Q4B MA Extended Qty. Tape and
Reel
AT24C16C‑CUM‑T VFBGA 8U3‑1 C Tape and Reel
AT24C16C‑MEHM‑T XDFN 8ME1 ME Tape and Reel
Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.

AT24C16C
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,
BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,
SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL
ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

AT24C16C
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-3390-3
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ISO/TS 16949
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fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
® ®
and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC
®
DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.

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AT24C16C Data Sheet 20006051A

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AT24C16C Data Sheet 20006051A

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AT24C16C

I²C-Compatible (2-Wire) Serial EEPROM 16‑Kbit (2,048 x 8)

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 1

1. Package Types (not to scale).................................................................................... 4

5. Device Operation and Communication....................................................................13

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 2

9. Device Default Condition from Microchip................................................................ 22

10. Packaging Information.............................................................................................23

11. Revision History.......................................................................................................37

The Microchip Web Site................................................................................................ 38

Customer Change Notification Service..........................................................................38

Product Identification System........................................................................................ 39

Microchip Devices Code Protection Feature................................................................. 39

Quality Management System Certified by DNV.............................................................41

Worldwide Sales and Service........................................................................................42

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 3

1. Package Types (not to scale)

GND 4 5 SDA SDA 3 4 Vcc

GND 4 5 SDA GND 4 5 SDA

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 4

2.2 Serial Data (SDA)

2.3 Serial Clock (SCL)

2.4 Write-Protect (WP)

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 5

WP Pin Status Part of the Array Protected

2.5 Device Power Supply

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 6

3.1 System Configuration Using 2-Wire Serial EEPROMs

I2C Bus Master:

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 7

3.2 Block Diagram

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 8

4.1 Absolute Maximum Ratings

4.2 DC and AC Operating Range

Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 9

Parameter Symbol Minimum Typical(1) Maximum Units Test Conditions

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 10

Parameter Symbol 1.7V 2.5V, 2.7V, 5.0V Units

tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO

4.5 Electrical Specifications

4.5.1 Power-Up Requirements and Reset Behavior

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 11

Symbol Parameter Min. Max. Units

4.5.2 Pin Capacitance

Symbol Test Condition Max. Units Conditions

4.5.3 EEPROM Cell Performance Characteristics

Operation Test Condition Min. Max. Units

Data Retention(1) TA = 55°C 100 — Years

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 12

5. Device Operation and Communication

5.1 Clock and Data Transition Requirements

5.2 Start and Stop Conditions

5.2.1 Start Condition

5.2.2 Stop Condition

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 13

5.3 Acknowledge and No-Acknowledge

5.4 Standby Mode

© 2018 Microchip Technology Inc. Datasheet DS20006051A-page 14

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