Bhattacharya - FinFETs From Devices to Architectures

Hindawi Publishing Corporation
Advances in Electronics
Volume 2014, Article ID 365689, 21 pages
http://dx.doi.org/10.1155/2014/365689
Review Article
FinFETs: From Devices to Architectures
Debajit Bhattacharya and Niraj K. Jha

Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA
Correspondence should be addressed to Niraj K. Jha; jha@princeton.edu
Received 4 June 2014; Accepted 23 July 2014; Published 7 September 2014
Academic Editor: Jaber Abu Qahouq
Copyright © 2014 D. Bhattacharya and N. K. Jha. This is an open access article distributed under the Creative Commons
Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is
properly cited.
Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate
FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to
tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable
continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost
architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-
level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for
characterizing FinFET devices, circuits, and architectures.
1. Introduction (𝑆), drain-induced barrier lowering (DIBL), and threshold

voltage (𝑉th ) roll-off. Improvement in these metrics implies
Relentless scaling of planar MOSFETs over the past four less degradation in the transistor’s 𝑉th with continued scaling,
decades has delivered ever-increasing transistor density and which in turn implies less degradation in 𝐼off .
performance to integrated circuits (ICs). However, continu- So far, we have referred to planar MOSFETs built on bulk-
ing this trend in the nanometer regime is very challenging Si wafers (or bulk MOSFETs) as planar MOSFETs. Fully-
due to the drastic increase in the subthreshold leakage depleted silicon-on-insulator (FDSOI) MOSFETs (planar
current (𝐼off ) [1–3]. Due to the very narrow channel lengths MOSFETs built atop SOI wafers) avoid the extra leakage
in deeply scaled MOSFETs, the drain potential begins to paths from the drain to source by getting rid of the extra
influence the electrostatics of the channel and, consequently, substrate beneath the channel [13, 14]. Their performance
the gate loses adequate control over the channel. As a result, metrics are comparable with those of double-gate FETs
the gate is unable to shut off the channel completely in (DGFETs), which are MGFETs with two gates. Both offer
the off-mode of operation, which leads to an increased reduced junction capacitance, higher 𝐼on /𝐼off ratio, better 𝑆,
𝐼off between the drain and the source. The use of thinner and improved robustness against random dopant fluctuation
gate oxides and high-k dielectric materials helps alleviate (RDF). However, DGFETs have a more relaxed constraint
this problem by increasing the gate-channel capacitance. on channel thickness, which makes DGFETs more scalable
However, thinning of gate oxides is fundamentally limited than FDSOI MOSFETs in the long run [15, 16]. Also, DGFET
by the deterioration in gate leakage and gate-induced drain structures can be built on bulk-Si wafers, as well, which makes
leakage (GIDL) [4–6]. Multiple-gate field-effect transistors DGFETs more attractive to foundries that do not want to
(MGFETs), which are an alternative to planar MOSFETs, switch to an SOI process [17, 18].
demonstrate better screening of the drain potential from the Among all MGFETs, FinFETs (a type of DGFET) and
channel due to the proximity of the additional gate(s) to Trigate FETs (another popular MGFET with three gates) have
the channel (i.e., higher gate-channel capacitance) [7–12]. emerged as the most desirable alternatives to MOSFETs due
This makes MGFETs superior to planar MOSFETs in short- to their simple structures and ease of fabrication [19–27].
channel performance metrics, such as subthreshold slope Two or three gates wrapped around a vertical channel enable
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2 Advances in Electronics
easy alignment of gates and compatibility with the standard 400 120
CMOS fabrication process. In Trigate FETs, an additional
350
Subthreshold swing (mV/decade)

selective etching step of the hard mask is involved in order 100
to create the third gate on top of the channel. Although this 300
third gate adds to process complexity, it also leads to some 80
DIBL (mV/V)
250
advantages like reduced fringe capacitances and additional
transistor width [28–30]. 200 60
FinFET/Trigate devices have been explored thoroughly 150 Single-gate/bulk
in the past decade. A large number of research articles have 40
Double-gate
been published that demonstrate the improved short-channel 100
behavior of these devices over conventional bulk MOSFETs 20
50
[19–22, 31–33]. Many researchers have presented novel circuit
design styles that exploit different kinds of FinFETs [34– 0 0
15 25 35 45 55
48]. Researchers have also explored various symmetric and LEFF (nm)
asymmetric FinFET styles and used them in hybrid FinFET
logic gates and memories [49–66]. Newer architectures for Figure 1: DIBL and subthreshold swing (𝑆) versus effective channel
caches, networks-on-chip (NoCs), and processors based on length for double-gate (DG) and bulk-silicon nFETs. The DG device
such logic gates and memories have also been explored [67– is designed with an undoped body and a near-mid-gap gate material
74]. In spite of these advancements in FinFET research, [12].
articles that provide a global view of FinFETs from the
device level to the topmost architecture level are scarce.
Mishra et al. provided such a view at the circuit level [75]. of the channel (𝐻FIN ) determines the width (𝑊) of the
However, FinFETs are not covered at other levels of the design FinFET. This leads to a special property of FinFETs known
hierarchy. Also, at the circuit level, much progress has been as width quantization. This property says that the FinFET
made since the publication of that book chapter. Our article width must be a multiple of 𝐻FIN , that is, widths can be
is aimed at a wide range of readers: device engineers, circuit increased by using multiple fins. Thus, arbitrary FinFET
designers, and hardware architects. Our goal is to provide a widths are not possible. Although smaller fin heights offer
global view of FinFET concepts spanning the entire IC design more flexibility, they lead to multiple fins, which in turn
hierarchy. leads to more silicon area. On the other hand, taller fins
The paper is organized as follows. In Section 2, we lead to less silicon footprint, but may also result in structural
review the different types of FinFETs and possible asym- instability. Typically, the fin height is determined by the
metries that can be designed into their structures. We also process engineers and is kept below four times the fin
discuss the sources of process variations in FinFETs and thickness [77, 78].
their impact on FinFET performance. We discuss FinFET Although FinFETs implemented on SOI wafers are very
process simulation, device simulation, and compact models popular, FinFETs have also been implemented on con-
in Section 3. We describe novel FinFET inverter (INV) ventional bulk wafers extensively [79–81]. Figure 3 shows
and NAND gates, flip-flops, latches, static random-access FinFETs implemented on bulk and SOI wafers. Unlike bulk
memory (SRAM), and dynamic random-access memory FinFETs, where all fins share a common Si substrate (also
(DRAM) cells in Section 4. In Section 5, we discuss circuit- known as the bulk), fins in SOI FinFETs are physically
level analysis and optimization methodologies and a novel isolated. Some companies prefer the bulk technology because
interconnect scheme that leverages FinFETs. We then present it is easier to migrate to bulk FinFETs from conventional bulk
a survey of process-voltage-temperature (PVT) variation- MOSFETs. However, FinFETs on both types of wafers are
aware architecture-level simulation tools in Section 6 and quite comparable in terms of cost, performance, and yield,
conclude in Section 7. and it is premature to pick a winner. From this point on, our
discussion will be limited to SOI FinFETs unless otherwise
mentioned.
2. FinFETs Trigate FETs, referred to interchangeably as FinFETs, in
this paper so far, are a variant of FinFETs, with a third gate
In 1989, Hisamato et al. fabricated a double-gate SOI structure on top of the fin. Intel introduced Trigate FETs at the 22 nm
which they called a fully-depleted lean channel transistor node in the Ivy-Bridge processor in 2012 [28, 82]. Figure 4
(DELTA) [76]. This was the first reported fabrication of shows a Trigate FET along with a FinFET. The thickness of
a FinFET-like structure. FinFETs have attracted increasing the dielectric on top of the fin is reduced in Trigate FETs in
attention over the past decade because of the degrading order to create the third gate. Due to the presence of the third
short-channel behavior of planar MOSFETs [19–24]. Figure 1 gate, the thickness of the fin also adds to the channel width.
demonstrates the superior short-channel performance of Hence, Trigate FETs enjoy a slight width advantage over
FinFETs over planar MOSFETs with the same channel length. FinFETs. Trigate FETs also have less gate-source capacitance
Figure 2 shows a conventional planar MOSFET and a FinFET. compared to FinFETs due to additional current conduction at
While the planar MOSFET channel is horizontal, the FinFET the top surface, but this advantage is diminished by increased
channel (also known as the fin) is vertical. Hence, the height parasitic resistance [29].
Advances in Electronics 3
Drain Drain
Gate
Gate 1
L
Source
Source Gate 2
L
W HFIN
Gate dielectric Gate dielectric
(a) (b)
Figure 2: Structural comparison between (a) planar MOSFET and (b) FinFET.
Drain Drain
Source Source
Gate 2 Gate 2
Gate 1 Gate 1
Buried oxide
Silicon substrate
Silicon substrate
(a) (b)
Figure 3: Structural comparison between (a) bulk and (b) SOI FinFETs.
Yang and Fossum compared Trigate FETs and FinFETs FinFETs are also known as three-terminal (3T) FinFETs and
and argued that FinFETs are superior to Trigate FETs in IG FinFETs as four-terminal (4T) FinFETs. In SG FinFETs,
the long run [83]. They showed that although undoped both the front and back gates are physically shorted, whereas
Trigate FETs may enjoy more relaxed body thickness, they in IG FinFETs, the gates are physically isolated (Figure 5).
are not competitive with FinFETs in SCE metrics. When Thus, in SG FinFETs, both gates are jointly used to control
trying to achieve comparable SCE metrics, Trigate FETs lose the electrostatics of the channel. Hence, SG FinFETs show
the scaling advantage and suffer from significant layout area higher on-current (𝐼on ) and also higher off-current (𝐼off or
disadvantage. However, like the bulk versus SOI debate, it is the subthreshold current) compared to those of IG FinFETs.
also premature to declare a clear winner between FinFETs IG FinFETs offer the flexibility of applying different signals
and Trigate FETs. From this point onwards, we will consider or voltages to their two gates. This enables the use of the
FinFETs only unless stated otherwise. back-gate bias to modulate the 𝑉th of the front gate linearly.
FinFETs can be fabricated with their channel along However, IG FinFETs incur a high area penalty due to the
different directions in a single die. Fabrication of planar need for placing two separate gate contacts.
MOSFET channels along any crystal plane other than ⟨100⟩ SG FinFETs can be further categorized based on asymme-
is difficult due to process variations and interface traps [36, tries in their device parameters. Normally, the workfunctions
84]. However, FinFETs can be fabricated along the ⟨110⟩ (Φ) of both the front and back gates of a FinFET are the
plane as well. This results in enhanced hole mobility. ⟨110⟩- same. However, the workfunctions can also be made different.
oriented FinFETs can be fabricated by simply rotating the This leads to an asymmetric gate-workfunction SG FinFET
transistor layout by 45∘ in the plane of a ⟨100⟩ wafer [85]. or ASG FinFET (Figure 6) [86, 87]. ASG FinFETs can be
Thus, nFinFETs implemented along ⟨100⟩ and pFinFETs fabricated with selective doping of the two gate-stacks. They
along ⟨110⟩ lead to faster logic gates since this gives designers have very promising short-channel characteristics and have
an opportunity to combat the inherent mobility difference two orders of magnitude lower 𝐼off compared to that of
between electrons and holes. However, this multiorientation an SG FinFET, with 𝐼on only somewhat lower than that of
scheme has an obvious drawback of increased silicon area an SG FinFET [49]. Figures 7 and 8 show comparisons of
[85]. In the following sections, we discuss FinFET classifica- the drain current 𝐼DS versus front-gate voltage 𝑉GFS curves
tions and process variations in detail. for SG, IG, and ASG nFinFETs and pFinFETs, respectively,
demonstrating the advantages of ASG FinFETs.
Apart from gate-workfunction asymmetry, other asym-
2.1. FinFET Classification. There are two main types of metries have also been explored in FinFETs. Goel et al.
FinFETs: shorted-gate (SG) and independent-gate (IG). SG [57] show that asymmetric drain-spacer-extended (ADSE)
Drain Drain
Gate 3
Gate 1
Dielectric thickness
of third gate Dielectric thickness
Gate 1 of third gate
Gate 2
Gate 2
Source
Source
(a) (b)
Figure 4: Structural comparison between (a) FinFET and (b) Trigate FET.
Drain
Drain
Gate 1
Source
Source
Gate 2 Gate 2
Gate 1

(a) (b)
Figure 5: Structural comparison between (a) SG and (b) IG FinFET.
Drain Drain
Gate 1 Gate 1
Source Source
Gate 2 Gate 2

(a) (b)
Figure 6: Structural comparison between (a) SG and (b) ASG FinFET; shaded gate implies different workfunctions.
10−2 z
68% Ion reduction w.r.t SG
x Increased gate
LG
sidewall spacer
10 −4 y
Front gate
10−6 L OV L CH TSI
Source L UN Drain
IDS (A)
TOX
10−8 Back gate
L SP L SP ΔLSP
415x
10−10
15x (a)
10−12 ISD
0 0.2 0.4 0.6 0.8 1 Gate IDS Gate
VGFS (V)
Source Drain Source Drain
ASG (VGBS = VGFS )
IG (VGBS = −0.2 V)
SG (VGBS = VGFS ) DrainLunConf SourceLunConf
Vdrain > Vsource Vdrain < Vsource
Figure 7: Drain current (𝐼DS ) versus front-gate voltage (𝑉GFS ) for
(b)
three nFinFETs [49].
Figure 9: Asymmetric drain spacer extension (ADSE) FinFET [57].
10−2
41% Ion reduction w.r.t SG LG Lower doping

10−4
Front gate
10−6 L CH
Source L OV L OVD TSI Drain
IDS (A)
TOX
10−8 Back gate
L SP L SP
10−10 175x
(a)
5x Gate Gate
10−12
−1 −0.8 −0.6 −0.4 −0.2 0
Source Drain Source Drain
VGFS (V)
SG (VGBS = VGFS )
IG (VGBS = 0.2 V)
ASG (VGBS = VGFS )
(b)
Figure 8: Drain current (𝐼DS ) versus front-gate voltage (𝑉GFS ) for Figure 10: Asymmetric drain-source doped (AD) FinFET [58].
three pFinFETs [49].
FinFETs (Figure 9) can lead to improved short-channel char- This also destroys the conventional symmetry in 𝐼DS and
acteristics because of an indirect increase in channel length. 𝐼SD , which again leads to asymmetric FinFET pass transistor
However, this improvement comes at the cost of an increased performance. SCEs are improved in AD FinFETs because of
layout area. This asymmetry also destroys the conventional lower electric fields in the lower-doped drain. FinFETs with
interchangeable source-drain concept in CMOS. An asym- asymmetric oxide thickness (ATox) (Figure 11) have also been
metry is created in the drain-to-source current 𝐼DS and proposed [88, 89]. Such FinFETs have good subthreshold
source-to-drain current 𝐼SD because of the extra underlap. slopes. Use of IG FinFET (or 4T FinFET) in this context
This asymmetry affects FinFET pass transistor performance. also enables variable 𝑉th ’s. This asymmetry can be achieved
Asymmetric drain-source doped (AD) FinFETs (Figure 10), using a ion-bombardment-enhanced etching process. Finally,
with an order of magnitude difference in the drain and asymmetric fin-height FinFETs have also been explored [61,
source doping concentrations, have been exploited in [58]. 90]. Since the channel width of a FinFET is proportional to
D D D
Drive gate Drive gate
Gate 1 Gate 2 Gate 1 Gate 2

Gate Gate
S S
S
Vth control gate Vth control gate
3T-FinFET (TOX1 = TOX2 ) 4T-FinFET (TOX1 = TOX2 ) 4T-FinFET (TOX1 < TOX2 )
Ideal S-slope Flexible Vth Flexible Vth
but fixed Vth but bad S-slope and good S-slope
Figure 11: Asymmetric oxide thickness (ATox) FinFET [89].
Table 1: 22 nm SOI FinFET parameter values. L GF L SPF
𝐿 GF , 𝐿 GB (nm) 24
TOXF
Effective 𝑇OXF , 𝑇OXB (nm) 1 HGF
𝑇SI (nm) 10
𝐻FIN (nm) 40
𝐻GF , 𝐻GB (nm) 10 TSI
𝐿 SPF , 𝐿 SPB (nm) 12
𝐿 UN (nm) 4 TOXB
𝑁BODY (cm−3 ) 1015 HGB
𝑁S/D (cm−3 ) 1020
L GB
ΦGF , ΦGB (eV) 4.4(𝑛), 4.8(𝑝) L SPB L UN (L OV )
FP (nm) 50
GP (nm) 92 Figure 12: A 2D cross-section of a 3D nFinFET with extended
source and drain [49].
its fin height, pFinFETs with taller fins can compensate for In planar MOSFETs, a sufficient number of dopants must
the inherent mobility mismatch between electrons and holes. be inserted into the channel in order to tackle SCEs. However,
Figure 12 shows a two-dimensional (2D) cross-section of this means that RDF may lead to a significant variation in
a three-dimensional (3D) FinFET, illustrating various device 𝑉th . For example, at deeply scaled nodes, the 3(𝜎/𝜇) variation
parameters of interest. Typical values for these parameters in 𝑉th caused by discrete impurity fluctuation can be greater
are given in Table 1. 𝐿 GF , 𝐿 GB , 𝑇OXF , 𝑇OXB , 𝑇SI , 𝐻FIN , 𝐻GF , than 100% [91]. Since FinFETs enable better SCE performance
𝐻GB , 𝐿 SPF , 𝐿 SPB , 𝐿 UN , 𝑁BODY , 𝑁𝑆/𝐷, ΦGF , ΦGB , FP, and GP due to the presence of the second gate, they do not need a
refer to the physical front- and back-gate lengths, front- high channel doping to ensure a high 𝑉th . Hence, designers
and back-gate effective oxide thicknesses, fin thickness, fin can keep the thin channel (fin) at nearly intrinsic levels
height, front- and back-gate thicknesses, front- and back-gate
(1015 cm−3 ). This reduces the statistical impact of RDF on 𝑉th .
spacer thicknesses, gate-drain/source underlap, body doping,
The desired 𝑉th is obtained by engineering the workfunction
source/drain doping, front- and back-gate workfunctions, fin
of the gate material instead. Low channel doping also ensures
pitch, and gate pitch, respectively.
better mobility of the carriers inside the channel. Thus,
FinFETs emerge superior to planar MOSFETs by overcoming
2.2. Process Variations. Reduced feature size and limited a major source of process variation.
photolithographic resolution cause statistical fluctuations in FinFETs do suffer from other process variations. Due to
nanoscale device parameters. These fluctuations cause varia- their small dimensions and lithographic limitations, FinFETs
tions in electrical device parameters, such as 𝑉th , 𝐼on , 𝐼off , and are subjected to several important physical fluctuations,
so forth, known as process variations. These variations can be such as variations in gate length (𝐿 GF , 𝐿 GB ), fin-thickness
inter-die or intra-die, correlated or uncorrelated, depending (𝑇SI ), gate-oxide thickness (𝑇OXF , 𝑇OXB ), and gate underlap
on the fabrication process. They lead to mismatched device (𝐿 UN ) [91–97]. For example, gate oxide is on the etched
strengths and degrade the yield of the entire die. This is sidewall of the fin, and may suffer from nonuniformity. The
why continued scaling of planar MOSFETs has become so degree of nonuniformity depends on the line-edge roughness
difficult. (LER) of the fin. LER also causes variations in fin thickness.
0.25 L UN 25
0.2 TOX 20
Probability of occurrence
ASG
15
Frequency
0.15 IG
SG
10
0.1
LG
5
0.05 TSI
0
0 −13 −12 −11 −10 −9 −8 −7 −6
−9.4 −9.3 −9.2 −9.1 −9.0 −8.9 −8.8 −8.7 −8.6 Log10 (Ioff /1A)
Log10 (Ioff /1A)
Figure 15: Distributions of 𝐼off under process variations for three
L UN LG nFinFETs [49].
TOX TSI
Figure 13: Distribution of leakage current (𝐼off ) for different process

parameters, each varying independently [94]. SOI FinFETs because the oxide layer under the fin has poor
thermal conductivity. Hence, heat generated in the fin cannot
dissipate easily in SOI FinFETs. Bhoj and Jha have evaluated
10−7 SG, IG, and ASG FinFETs under temperature variation and
found that even though 𝐼off degrades for all three FinFETs
at a higher temperature, ASG FinFETs still remain the best
10−8
104x and retain a 100× advantage over SG FinFETs, as shown in
Figure 14 [49]. They also showed the distribution of 𝐼off under
10−9 8x process variations for the three FinFETs (Figure 15).
Ioff (A)
640x
10−10
3. FinFET Device Characterization
In this section, we discuss various ways of characterizing Fin-
−11 FET devices through simulation. Process simulation followed
10
by device simulation constitutes a technology computer-
18x aided design (TCAD) characterization flow of nanoscale
10−12 devices, such as FinFETs. Compact models, on the other
280 300 320 340 360 380 400 hand, have been another very popular way of characterizing
Temperature (K) CMOS devices for decades.
ASG
SG 3.1. Process Simulation. Real devices undergo several process-
IG (VGBS = −0.2 V) ing steps. The functionality and performance of the fabricated
devices depend on how optimized the process flow is. TCAD
Figure 14: 𝐼off versus temperature for three nFinFETs [49]. process simulation is, therefore, an important step in FinFET
device optimization. Process simulation is followed by device
simulation. These two simulation steps form an optimization
Figure 13 shows the impact of parametric variations on the loop in which small changes in the process flow (e.g., time,
subthreshold current (𝐼off ) of an nFinFET. Xiong and Bokor temperature, doses, etc.) can lead to desirable electrical
have studied the sensitivity of electrical parameters to various characteristics of the device. Thus, process simulation helps
physical variations in devices designed with a nearly intrinsic device engineers explore the parameter space of the process,
channel [91]. obviating the need for actual device fabrication. Although 3D
Choi et al. have studied temperature variations in FinFET process simulation is computationally very expensive, it not
circuits under above-mentioned physical parameters varia- only gives good insights into device physics but also provides
tions [98]. They showed that even under moderate process a cost-effective pre-fabrication process optimization flow.
variations (3(𝜎/𝜇) = 10%) in gate length (𝐿 GF , 𝐿 GB ) and The Sentaurus process and device simulator from Syn-
body thickness (𝑇SI ), thermal runaway is possible in more opsys is a widely used tool for process simulation [99].
than 15% of ICs when primary input switching activity is Its 3D process simulation framework is compatible with
0.4. The effect of temperature variation is more severe in the mainstream 2D TCAD framework TSUPREM4/MEDICI
(also from Synopsys). The 2D framework has been used by ΦGF = ΦGB = 4.4 eV ΦGF = ΦGB = 4.8 eV
designers over the past decade and has been well-calibrated
with advanced CMOS libraries. Nawaz et al. have imple-
mented a complete FinFET process flow as a commercially-
available process and device simulation environment [100].
As in real devices, all important geometrical features, such as
corner roundings and 3D facets, have been implemented in
their setup.
(a) (b) (c) (d)
Process simulations of large layouts that consist of multi-
ple devices incur extremely high computational costs. A novel Figure 16: Schematic diagrams of (a) SG nFinFET, (b) IG nFinFET,
layout/process/device-independent TCAD methodology was (c) SG pFinFET, and (d) IG pFinFET. Their gate workfunctions are
proposed in [54] in order to overcome the process simulation also shown [49].
barrier for accurate 3D TCAD structure synthesis. In it, Bhoj
et al. adopt an automated structure synthesis approach that
obviates the need for repetitive 3D process simulations for
4. FinFET Standard Cells
different layouts. In this approach, process-simulated unit
devices are placed at the device locations in the layout, After the characterization of individual n/pFinFET devices,
eliminating the need for process simulation of the entire we move one level up to characterization of FinFET logic
layout, thereby reducing computational costs significantly. gates, latches, flip-flops, and memory cells, which are the
This structure synthesis approach, followed by transport building blocks of any digital integrated circuit [49–51].
analysis based capacitance extraction methodology, has been IG and ASG FinFETs offer new leakage-delay tradeoffs in
shown to capture accurate parasitic capacitances in FinFET FinFET logic gates that can be exploited in low-power or
SRAMs and ring oscillators in a practical timeframe [54, 55, high-performance applications. The schematic diagrams of
63, 66]. Accurate extraction of parasitic capacitances has led SG and IG FinFETs are shown in Figure 16. Schematic
to a comprehensive evaluation of transient metrics of various diagrams of ASG FinFETs are shown in Figure 17. Bhoj and
FinFET SRAM bitcells [55]. Jha have performed an in-depth analysis and comparison of
SG, IG, and ASG FinFET based INV and NAND2 (two-input
3.2. Device Simulation. After process simulation generates NAND) gates [49]. These two gates are the most essential
a meshed device structure, device simulation is performed building blocks of any logic library because any logic network
on the structure by invoking appropriate transport models. can be built with just these two gates.
The conventional drift-diffusion transport model is not ade-
quate for capturing SCEs in nanometer MOSFETs and Fin- 4.1. SG/IG INV. There are four possible configurations of
FETs. The hydrodynamic model, with quantum corrections an INV based on how SG and IG FinFETs are combined
(such as density gradient models), has been popular among to implement them. They are called SG, low-power (LP),
researchers for FinFET device simulation [101]. Other more IGn, and IGp INV. Their schematic diagrams are shown in
accurate models, such as Green’s function based solution Figure 18. As suggested by its name, an SG INV has SG
to Boltzmann’s transport equation, impose a drastic com- n/pFinFETs. It has a highly compact layout. The other three
putational burden [101]. In order to simulate circuits with configurations use at least one IG FinFET. The back-gate of
multiple devices, Sentaurus device (Synopsys) allows mixed- an IG pFinFET (nFinFET) is tied to a 𝑉HIGH (𝑉LOW ) signal.
mode device simulation. Here, individual FinFET devices are When these signals are reverse-biased, for example, when
connected externally using wires or other circuit elements to 𝑉HIGH is 0.2 V above 𝑉DD and 𝑉LOW is 0.2 V below ground,
form a netlist and coupled transport equations are solved on there is a significant reduction in 𝐼off . The presence of an IG
the entire netlist. This feature enables device engineers to see FinFET also leads to a more complex layout, resulting in 36%
how the device behaves when used in a circuit. area overhead relative to that of an ×2 SG INV (that is double
the size of a minimum-sized SG INV). Table 2 compares
3.3. Compact Models. Physics based compact models of the normalized area, delay, and leakage of the various INVs.
FinFETs have been a very useful tool for designers. Berke- Clearly, SG INV is the best in area and propagation delay
ley short-channel IGFET model (BSIM) and University of (𝑇𝑝 ), but incurs much higher leakage current than LP INV.
Florida double-gate model (UFDG) for SOI multigate MOS- However, LP INV performs poorly in area and propagation
FETs and FinFETs were built using TCAD and calibrated delay. IGn INV, however, looks promising based on its
using fabricated hardware [102–105]. These models are com- intermediate area, delay, and leakage.
patible with commercial circuit simulators, such as simu-
lation program with integrated circuit emphasis (SPICE). 4.2. SG/IG NAND2. Similar to INVs, NAND2 gates also
Hence, large netlists can be simulated with these models as have SG (LP) configurations in which all transistors are SG
long as the solution space is within their range. However, (IG) FinFETs. Since there are more transistors in a NAND2
device simulation precedes derivation of compact models and gate than in an INV, there are more opportunities available
is more accurate. Thus, all results presented in this article are for combining SG and IG FinFETs. This leads to various
based on mixed-mode device simulations. other configurations: MT, IG, IG2, XT, and XT2. Schematic
ΦGB = 4.4 eV ΦGB = 4.4 eV
ΦGF = 4.8 eV ΦGF = 4.8 eV
(a) (b)
Figure 17: Schematic diagrams of ASG: (a) nFinFET and (b) pFinFET. Their gate workfunctions are also shown [49].
Vhigh Vhigh
PA PA PA PA
Out Out Out Out
A A A
A
Vlow Vlow
NA NA NA NA
(a) (b) (c) (d)
Figure 18: Schematic diagrams of (a) SG INV, (b) LP INV, (c) IGn INV, and (d) IGp INV [49].
Table 2: Comparison of FinFET INVs [49]. NAND2 outperforms others in area and propagation delay,
but consumes significantly more leakage current than LP
Topology SG LP IGn IGp
NAND2. Out of all the variants, XT2 NAND2 stands out as a
Area 1 1.36 1.36 1.36 reasonable compromise.
Avg. 𝐼off 20.92 1 2.75 19.25
𝑇𝑝 1 3.67 1.67 2.92
4.3. ASG Logic Gates. Bhoj and Jha investigated INV and
NAND2 gates with a mix of SG and ASG FinFETs [49].
Table 3: Comparison of FinFET NAND2 gates [49]. Schematics/layouts of any SG-FinFET logic gate can be
converted to those of an ASG-FinFET logic gate, as shown
Topology SG LP MT IG IG2 XT XT2 in Figure 21, without any area overhead. Hence, introduction
Area 1 1.27 1.27 1 1 1.27 1 of ASG FinFETs only impacts leakage and propagation delay.
Avg. 𝐼off 18.40 1 7.00 18.40 7.73 18.13 7.73 Preserving some of the SG FinFETs in the NAND2S gate
𝑇𝑝 (Toggle A) 1 4.13 3.80 1.60 2.08 3.20 1.47 (Figure 21(c)) enables leakage-delay tradeoffs, as evident from
𝑇𝑝 (Toggle B) 1 4.50 3.88 1.69 2.02 3.58 1.38 the leakage-delay spectrum shown in Figure 22 for various
𝑇𝑝 (Toggle AB) 1 3.48 3.09 1 1.55 2.38 1.55 logic gates. The pure ASG gates lie in the left half of the
spectrum, indicating low leakage, while pure SG gates lie in
the bottom half of the spectrum, indicating less delay.
diagrams of SG, LP, and MT NAND2 gates are shown in
Figure 19. Schematic diagrams for IG, IG2, XT, and XT2 4.4. SG/IG/ASG Latches and Flip-Flops. Brute-force trans-
NAND2 gates are shown in Figure 20. Table 3 shows the mission gate (TG) and half-swing (HS) latches and flip-flops
normalized area, delay, and leakage of all these NAND2 (as shown in Figures 23 and 24) implemented with SG, IG,
gates. Again, all comparisons in Table 3 are made relative to and ASG FinFETs have also been investigated [49, 50]. Tawfik
×2 SG NAND2 gate, because it is the largest SG NAND2 gate et al. proposed an IG latch by introducing IG FinFETs in the
that can be accommodated in the standard cell height. SG feedback inverter (I3) of the all-SG TG latch in Figure 23(a).
PB Vhigh Vhigh
PB PB
PA PA PA
B A B A B A
Out Out Out

NA NA Vlow NA
Vlow
NB NB NB
(a) (b) (c)
Figure 19: Schematic diagrams of NAND2 gates: (a) SG, (b) LP, and (c) MT [49].
Vhigh
PB PA
PA PA
B A B A B A
Out Out Out
NA Vlow NA NA
NB NB NB
(a) (b) (c)
PB PA
B A
Out
Vlow NA
NB
(d)
Figure 20: Schematic diagrams of NAND2 gates: (a) IG, (b) IG2, (c) XT, and (d) XT2 [49].
With appropriate reverse-biasing of the back gates, the IG area improvements are obtained for IG flip-flops relative to
FinFETs in I3 are made weaker compared to the drive inverter TG flip-flops (Figure 24(a)). Bhoj and Jha introduced ASG
(I1). As a result, the drive inverter need not be oversized, FinFETs in the TG and HS latches and observed similar
as conventionally done, ensuring a safe write operation at tradeoffs. Introducing ASG FinFETs in all the latch inverters
the same time. At nominal process corners, the IG latch (I1, I2, and I3) results in a minimum-leakage and maximum-
leads to 33% less leakage power and 20% less area compared delay configuration. Introducing ASG FinFETs in only I3
to the conventional SG latch with almost no degradation leads to a configuration similar to the IG latch. The new
in propagation delay and setup time. Similar power and configuration reduces leakage power by approximately 50%,
A B A B
Out Out
Out
A
(a) (b) (c)
Figure 21: Schematic diagrams of ASG FinFET logic gates: (a) INV, (b) NAND2, and (c) NAND2S [49].
×10−12 to SRAMs [106]. Since SRAMs are built with the smallest
14 transistors possible at a technology node (in order to increase
the memory density), statistical fluctuations are extremely
12 detrimental to SRAM performance. Deeply scaled SRAMs,
built atop planar MOSFETs, suffer from mismatches in
transistor strengths and 𝑉th caused by RDF and other sources
Average FO4 delay (s)
10 XT2 NAND2
of process variations. SRAMs also consume most of the chip’s
ASG NAND2S total leakage power because of very long idle periods in
8 ASG NAND2
IGn INV
large memory arrays. Six-transistor (6T) FinFET SRAMs (as
SG NAND2 shown in Figure 25) have been explored quite thoroughly in
6 the past decade from the point of view of suppressing leakage
power and tackling increased variability among bitcells [52–
4 60, 64, 65]. Figure 26 shows the butterfly curves, under
ASG INV
SG INV process variations, for MOSFET and FinFET based SRAMs.
2 The curves clearly demonstrate that FinFET SRAMs have a
10−11 10−10 10−9 10−8 superior static noise margin (SNM) because they do not suffer
Average Ioff (A) from RDF.
Figure 22: The leakage-delay spectrum of various logic gates [49]. New SRAM bitcell structures have been proposed using
a mix of SG, IG, and ASG FinFETs [55, 56, 60, 62]. In
[55], FinFET SRAMs have been classified into the following
categories: (i) vanilla shorted-gate configurations (VSCs) in
but the propagation delay increases by roughly 30%. This which all FinFETs are SG, (ii) independent-gate configura-
configuration also results in area savings as I1 can be sized tions (IGCs) in which one or more SG FinFETs are replaced
down, maintaining the desired write stability. Similar results with IG FinFETs, and (iii) multiple workfunction shorted-
are obtained for ASG flip-flops as well. gate configurations (MSCs) in which one or more SG FinFETs
As in the case of TG latches and flip-flops, combina- are replaced with ASG FinFETs. Table 4 shows the best bitcells
tions of SG, IG, and ASG FinFETs in inverters (I1 and from the perspectives of different metrics. RPNM, WTP,
I2) and nFinFETs (N1 to N4) generate various HS latches 𝐼READ , 𝐼off , 𝑇𝑅 , and 𝑇𝑊 refer to the read power noise margin,
(Figure 23(b)) and flip-flops (Figure 24(b)). As expected, write-trip power, read current, leakage current, read access
the leakage power of the all-ASG configuration is reduced time, and write access time of the bitcell, respectively. Out
by almost 65%, however, at the expense of doubling of of these, 𝑇𝑅 and 𝑇𝑊 represent transient metrics whereas the
its propagation delay. Using ASG FinFETs in N2/N4 only remaining metrics are DC. In Table 4, 𝑉 (𝑚𝑛𝑝) and 𝐴 (𝑚𝑛𝑝)
makes an interesting configuration that results in around 20% refer to VSC and MSC bitcells that have 𝑚, 𝑛, and 𝑝 fins
improvement in leakage, but only at a negligible cost (less in the pull-up (PU), pass-gate (PG), and pull-down (PD)
than 5%) in propagation delay. Similar results were obtained FinFETs, respectively. Pass-gate feedback (PGFB) [59], pull-
for HS flip-flops. up write gating (PUWG) [60], split pull-up (SPU) [65], and
row-based back-gate bias (RBB) [64] are some popular IGC
4.5. SRAM. SRAM is a key component of on-chip caches FinFET SRAM bitcells, as shown in Figure 27. Table 4 also
of state-of-the-art microprocessors. In today’s multicore pro- indicates that there is no single SRAM cell that is the best in
cessors, typically more than half of the die area is dedicated all the metrics, but it is possible to find a cell that is ahead of
I1
Q
CLK I2
CLK
N1 N3
CLK I2
T1
D Q D D
N4
I1 N2
CLK I3
(a) (b)
Figure 23: Schematic diagrams of FinFET latches: (a) transmission-gate and (b) half-swing [49].
I1 I3
INB IN Q
QB
I2 I4
CLK CLK
N1 N3 INB
N5
I2 D D N6
CLK CLK I4
T1 T2 I6 Vdd /2
D Q N4
IN N2 N7
I1 INB CLK QB
CLK
CLK I3 I5 I5
(a) (b)
Figure 24: Schematic diagrams of FinFET flip-flops: (a) transmission-gate and (b) half-swing [49].
Vdd Table 4: Comparison of FinFET SRAM cells [55].

WL WL
Metric VSC IGC MSC
PU1 PU2
Max. RPNM V(113) PGFB-PUWG A(112)
NL NR Min. WTP V(122) PGFB-SPU A(111)
BL BLB Max. 𝐼READ V(135) RBB A(112)
PG1 PG2
Min. 𝐼off V(111) RBB DPG-H
PD1 PD2 Min. 𝑇𝑅 V(111) PGFB A(11)S
Gnd Min. 𝑇𝑊 V(111) PGFB-SPU A(111)
Figure 25: Schematic diagram of a 6T FinFET SRAM.
the bitcell, it is called contact-underlap-storage (CUS) SRAM.

This SRAM exploits the bidirectional current flow in ADSE
the others in some of the metrics. A careful look at the FinFETs to improve both the read and write margins (by 11%
absolute values of the metrics reveals that IGC bitcells exhibit and 6%, resp.). Also, it reduces the leakage current by as much
superior DC metric values relative to those of VSC bitcells, as 57%. However, it suffers from a degraded access time (7%)
but their poor transient performance makes them unattrac- and cell area (7%).
tive. On the other hand, MSC bitcells have competitive DC Moradi et al. proposed a FinFET SRAM bitcell that
metric values and better transient performance relative to exploits AD FinFETs [58]. The lowly doped drains of the
VSC bitcells. Hence, in a nutshell, MSC bitcells may be a good AD-access transistors are placed towards the storage nodes.
choice for a FinFET SRAM bitcell. Out of all MSC bitcells, This SRAM bitcell is able to resolve the read-write conflicts
A(111) seems to be the most promising one. It is also shown in as the strength of the access transistors varies based on the
[55] that the transient behavior of a bitcell is very important to voltage of the storage nodes. This boosts both read (7.3%) and
account for. Evaluations based on only DC metrics may lead write (23%) margins. These improvements come at the cost of
to incorrect conclusions. an increased access time (42%) because the access transistor
Goel et al. proposed a different FinFET SRAM bitcell becomes weak during a read operation. Improvement in
using ADSE FinFETs in the access transistors (i.e., the PG subthreshold leakage of this bitcell is also to be noted (2.8×).
FinFETs) [57]. When the extended spacers of the PG FinFETs Sachid and Hu showed that multiple fin-height FinFETs
are placed towards the internal storage nodes (NL and NR) of can be used to design more dense and stable SRAMs [61].
1.0 1.0
𝛽 ratio = 2 𝛽 ratio = 2
0.8 0.8
Vout (V)
Vout (V)
0.6 0.6
0.4 0.4
0.2 0.2
200 samples 200 samples

0 0
0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0
Vin (V) Vin (V)
(a) (b)
Figure 26: Butterfly curves for SRAMs implemented with 20 nm gate-length (a) bulk planar MOSFET and (b) FinFET. The FinFET SRAM
exhibits a superior SNM because of smaller 𝑉th variation due to the use of an undoped channel [95].
Vdd Vdd
WL WL WL WL
PU1 PU2 WWL PU1 PU2 WWL
NL NR NL NR
BL BLB BL BLB
PG1 PG2 PG1 PG2
PD1 PD2 PD1 PD2

Gnd Gnd
(a) (b)
Vdd Vdd
WL WL WL WL
PU1 PU2 PU1 PU2
PG1 PG2
BLB
NL NR NL NR
BL BLB BL
PG1 PG2
Vbias
PD1 PD2 PD1 PD2 Vbias
Gnd Gnd
(c) (d)
Figure 27: Schematic diagrams of FinFET SRAM bitcells: (a) PGFB, (b) PGFB-PUWG, (c) PGFB-SPU, and (d) RBB.
Using multiple fin heights enables better control over the off-chip main memory and on-chip caches due to their
strengths of PU, PG, and PD transistors, leading to a better significant area advantage over SRAMs. With the advent of
noise margin, without incurring any area penalty. The draw- partially depleted-SOI (PDSOI) technology, a capacitorless
backs of this scheme are increased leakage power and process 1T-DRAM, also known as floating-body cell (FBC), was
complexity. proposed. This DRAM leads to a smaller area and a less com-
plicated fabrication process than conventional embedded
4.6. DRAM. One-transistor dynamic random-access mem- DRAMs [107–109]. Its functionality is based on the 𝑉th shift
ories (1T-DRAMs) have traditionally been used both in produced by majority carrier accumulation in the floating
H L temperature variation models are macromodel based [94],

Vdd Vdd
whereas the delay models are based on an SSTA approach
[114]. These models also take spatial correlations of the gates
into account using a rectangular grid based method [115].
FinPrin’s performance has been compared with that of accu-
rate quasi-Monte Carlo (QMC) simulations [116, 117] and was
Vin V Vout shown to produce very accurate means (𝜇) and reasonably
accurate standard deviations (𝜎), while enabling a significant
computation time speedup (two orders of magnitude).
5.2. Optimization. Optimization of logic circuits is made

possible by accurate analysis. Synopsys Design Compiler is
VssH VssL commercially used for power/delay optimization of logic
circuits, given a standard cell library [99]. In order to exploit
Figure 28: Buffer design using TCMS [34]. the various FinFET design styles, a linear programming based
optimization algorithm and tool are proposed in [39]. The
algorithm is used to assign gate sizes and FinFET types to
H L L
Vdd Vdd H
Vdd Vdd the mapped circuit, under a timing constraint, by selecting
standard cells from the FinFET design library. Unlike tradi-
Vin Vin tional greedy gate-sizing algorithms, this algorithm divides
S1 S1
the available slack among gates whose cells may be replaced. It
S2 L INT S2
is shown that this approach can achieve 15–30% better power
VssH VssL
consumption than Synopsys Design Compiler [39].
VssH VssL
Figure 29: Interconnect design using TCMS [34].

5.3. Novel Interconnect Structures and Logic Synthesis. Inter-
connects assume a lot of importance in deeply scaled technol-
ogy nodes as they govern the delay and power consumption of
body. However, the higher impurity concentration required modern integrated circuits. FinFETs not only provide newer
to suppress SCEs degrades the retention characteristics of circuit design styles, but also can lead to an efficient inter-
planar PDSOI 1T-DRAMs. Double-gate FinFET DRAMs connect implementation strategy. A mechanism to improve
(DG FinDRAM) are able to overcome these scaling issues of the interconnect efficiency, called threshold voltage control
1T-DRAMs [110–112]. The second gate, with the application of through multiple supply voltages (TCMS), has been proposed
an appropriate bias, helps with the accumulation of majority in [34]. The TCMS principle is based on the fact that the back-
carriers and thereby relaxes the high impurity concentration gate bias of a FinFET affects the 𝑉th of the front gate. Instead
criterion. FinFET based 1T-DRAMs also exhibit long reten- of using the conventional dual-𝑉dd scheme, TCMS uses a
𝐻
tion times and large sense margins. Thus, they have emerged slightly higher supply voltage (𝑉dd ) and a slightly negative
as a promising embedded memory alternative. 𝐻
supply voltage (𝑉ss ) along with the nominal supply voltages,
𝐿
𝑉dd , and ground (which is referred to as 𝑉ss𝐿 for symmetry).
5. Circuit-Level Analysis TCMS is based on the observation that an overdriven inverter
(i.e., whose input is driven by an inverter supplied with
𝐻
Logic circuit analysis and optimization tools have been imple- 𝑉dd and 𝑉ss𝐻 and whose supply voltage is 𝑉dd 𝐿
), as shown in
mented using FinFET based standard cell libraries described Figure 28, has both less leakage and less delay. Less leakage
in the previous section. In this section, we describe them in is ensured because of an increase in the 𝑉th of the leaking
brief. transistor and less delay is ensured because of the higher
current drive in the active transistor. The improvement in
5.1. Analysis. FinPrin is a statistical static timing analysis the drive strength of the active transistor results in improved
(SSTA) and power analysis tool for FinFET logic circuits that delay that can be traded off for area and power reduction
considers PVT variations and is based on accurate statistical under a given timing constraint. A chain of such inverter pairs
models for delay, dynamic power, and leakage power of the can be formed on the interconnect, as shown in Figure 29,
logic netlist [113]. It takes a register transfer-level (RTL) or without the need for voltage-level shifters due to the use
𝐻
gate-level description of a netlist as an input and estimates of higher-𝑉th transistors in the inverter supplied with 𝑉dd
𝐻
leakage/dynamic power and delay distributions (𝜇 and 𝜎 and 𝑉ss . This scheme enables a significant reduction in
for Gaussian distributions) at every node of the netlist, subthreshold leakage power in TCMS buffer interconnects.
based on the circuit-level parameter values provided in the It has been shown that, on an average, TCMS provides
FinFET design library, such as input and output capacitance, overall power savings of 50.4% along with area savings of
input and output resistance, and leakage current, taking 9.2% as compared to a state-of-the-art dual-𝑉dd interconnect
into account the impact of PVT variations. The leakage and synthesis scheme [34].
Target technology node

Cell configurations
Cache FinFET design library

structure Environment
parameters
FinFET FinFET Voltage
logic gate memory cell generator
Cache characteristics characteristics characteristics
configurations
Power/delay/ PVT variation

energy CACTI-PVT cache model parameters
constraints
Optimization
Power model PVT variation model
target Spatial grid
Area
parameter
constraints Delay model Delay variation model
assignment
Leakage variation model
Area model
Floorplan Fail
information
Optimization and correctness check
Pass
Delay profile Power profile

Search Write Read Dynamic Leakage
delay delay delay power power
Figure 30: CACTI-PVT block diagram [69].
The TCMS principle can also be applied to logic synthesis architecture for a given process. In the following subsections,
[35]. In this case, a FinFET logic gate can take advantage of we discuss PVT-aware simulation tools for various FinFET
the TCMS principle if its input arrives from a gate supplied based architectural components.
𝐻 𝐿
with the 𝑉dd set and its supply voltage belongs to the 𝑉dd set.
Since the opposite scenario leads to a high leakage current,
6.1. FinFET Based Caches. An integrated PVT variation-
it is avoided. Based on the combinations of supply voltage
𝐿 𝐻 𝐿 𝐻 aware power-delay simulation framework, called
(𝑉dd or 𝑉dd ), input voltage (𝑉dd or 𝑉dd ), and threshold voltage FinCANON [69], has been developed for FinFET based
(high-𝑉th or low-𝑉th ), INV and NAND2 have seven and 25 caches and NoCs. It has two components: CACTI-PVT
variants, respectively. As in the case of the interconnects, for caches and ORION-PVT for NoCs. CACTI-PVT is
𝐻
use of high-𝑉th FinFETs in 𝑉dd gates that need to be driven an extension of CACT-FinFET [67]. CACTI-PVT can
𝐿
by a 𝑉dd input voltage obviates the need for a voltage-level be used to obtain the delay and leakage distributions of
𝐿 𝐻
converter between the 𝑉dd and 𝑉dd gates. With the use of FinFET based caches with varying sizes, SRAM cell types,
a linear programming based optimization algorithm, TCMS and back-gate biases. The block diagram of CACTI-PVT
leads to an overall power reduction of 3× under relaxed delay is shown in Figure 30. It uses a FinFET design library
constraints. consisting of FinFET logic gates of various sizes and types
and different types of FinFET SRAM cells. This library is
characterized using accurate device simulation. The process
6. Architecture-Level Analysis variation models used in CACTI-PVT are calibrated using
QMC simulations, along with the rectangular grid-based
Next, we ascend the design hierarchy to the architecture level.
method to model spatial correlations. Peripheral components
Due to shrinking feature sizes and severe process variations,
implemented with SG FinFETs and SRAM cells implemented
the delay and power consumption at the chip level are not
with some IG FinFETs or ASG FinFETs provide the best
easy to predict any more [114]. Because of their inherent
balance between delay and leakage of the FinFET caches.
statistical nature, a yield analysis of an integrated circuit
(under a design constraint) has become very important. This
analysis estimates the percentage of chips that will meet the 6.2. FinFET Based NoCs. With increasing number of cores
given power and delay constraints for the particular chip in chip multiprocessors (CMPs), NoCs have emerged as an
Target technology node

Cell
configurations
FinFET design library
Environment
parameters
ORION-PVT
CACTI-PVT PVT variation

parameters
Delay estimation PVT variation model
model
GEMS SSTA delay model
performance Spatial grid
simulation Power estimation parameter
Leakage macromodel
model assignment
Network traffic NOC component model

profile
Router Input buffer Crossbar
configuration model model
Network
configuration Arbiter Clock Link
model model model
Router Clock/link
delay/power delay/power
profile profile
Figure 31: ORION-PVT block diagram [69].
effective communication mechanism among the cores. Fin- variation-aware integrated power-delay simulation tool for
CANON also includes a performance/power simulation tool, FinFET based multicore processors [71]. Figure 32 shows the
called ORION-PVT, aimed at FinFET NoCs [69]. ORION- block diagram of McPAT-PVT. It has two key components:
PVT, whose block diagram is shown in Figure 31, is an processor model and yield analyzer. The processor model
extension of ORION-FinFET [68]. Here, an SSTA technique contains power/delay macromodels of various functional
and a macromodel based methodology are used to model the units (e.g., arithmetic-logic unit, floating-point unit, memory
PVT variations in delay and leakage. It also provides a power management unit, etc.) of the processor core. The yield
breakdown of an on-chip router. Leakage power is found to analyzer can predict the yield of a specified processor con-
dominate the total power of the router at higher temperatures. figuration under PVT variations. Figure 33 zooms into the
A FinFET based implementation of a variable-pipeline- components of the processor model. The efficacy of this
stage router (VPSR) is proposed in [70]. VPSR enables tool has been demonstrated on an alpha-like processor core
dynamic adjustment of the number of pipeline stages in and multicore simulations based on Princeton Application
the router based on incoming network traffic. As a result, Repository for Shared-Memory Computer (PARSEC) bench-
different flow control digits (flits) may traverse pipeline marks.
stages of varying lengths while passing through the router.
This leads to enhanced router performance because VPSR
adapts its throughput to the network traffic requirement at
runtime. VPSR also enables significant savings in leakage 7. Conclusion
power through reverse-biasing (called adaptive back-gate In this paper, we have explored the impact of FinFETs
biasing) of the back gates of IG FinFETs in infrequently from the device to architecture level. We learnt about the
accessed components of the router. shortcomings of planar MOSFETs in today’s deeply scaled
technologies and the advantages of FinFETs as suitable
6.3. FinFET Based Multicore Processors. In the computer replacements for planar MOSFETs. We looked into FinFET
architecture domain, the trend has shifted in recent years device characteristics and evaluated tradeoffs among SG, IG,
from uniprocessors to CMPs and multicore systems in order and ASG FinFETs, along with other FinFET asymmetries,
to serve the ever-increasing performance demand. Tools like such as drain-spacer extension, source/drain doping, gate-
FinCANON have paved the way for a more powerful tool for oxide thickness, and fin height. We learnt about the detrimen-
characterizing multicore processors. McPAT-PVT is a PVT tal impact of PVT variations on FinFET chip performance
Design Processor
Acknowledgment
constraints configuration
This work was supported by NSF under Grant nos. CCF-
1217076 and CCF-1318603.
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Hindawi Publishing Corporation

Debajit Bhattacharya and Niraj K. Jha

Correspondence should be addressed to Niraj K. Jha; jha@princeton.edu

Received 4 June 2014; Accepted 23 July 2014; Published 7 September 2014

Academic Editor: Jaber Abu Qahouq

1. Introduction (𝑆), drain-induced barrier lowering (DIBL), and threshold

Subthreshold swing (mV/decade)

Gate dielectric Gate dielectric

Figure 5: Structural comparison between (a) SG and (b) IG FinFET.

Gate dielectric Gate dielectric

41% Ion reduction w.r.t SG LG Lower doping

Gate 1 Gate 2 Gate 1 Gate 2

Vth control gate Vth control gate

Figure 11: Asymmetric oxide thickness (ATox) FinFET [89].

Table 1: 22 nm SOI FinFET parameter values. L GF L SPF

Figure 13: Distribution of leakage current (𝐼off ) for different process

ΦGB = 4.4 eV ΦGB = 4.4 eV

ΦGF = 4.8 eV ΦGF = 4.8 eV

(a) (b) (c) (d)

Out Out Out

(a) (b) (c)

(a) (b) (c)

(a) (b) (c)

Vdd Table 4: Comparison of FinFET SRAM cells [55].

Figure 25: Schematic diagram of a 6T FinFET SRAM.

the bitcell, it is called contact-underlap-storage (CUS) SRAM.

200 samples 200 samples

PD1 PD2 PD1 PD2

H L temperature variation models are macromodel based [94],

5.2. Optimization. Optimization of logic circuits is made

Figure 29: Interconnect design using TCMS [34].

Target technology node

Cache FinFET design library

Power/delay/ PVT variation

Optimization and correctness check

Delay profile Power profile

Figure 30: CACTI-PVT block diagram [69].

Target technology node

CACTI-PVT PVT variation

Network traffic NOC component model

Figure 31: ORION-PVT block diagram [69].

[113] Y. Yang and N. K. Jha, “FinPrin: analysis and optimization of

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