Mc 33394

Freescale Semiconductor,Order
Inc. this document from Analog Marketing

Rev. 2.5, 11/2002
Switch Mode Power Supply with 33394

Multiple Linear Regulators and
High Speed CAN Transceiver MULTI–OUTPUT
The 33394 is a multi–output power supply integrated circuit with high POWER SUPPLY
speed CAN transceiver. The IC incorporates a switching pre–regulator SEMICONDUCTOR
operating over a wide input voltage range from +4.0V to +26.5V (with
TECHNICAL DATA
transients up to 45V).
The switching regulator has an internal 3.0A current limit and runs in both
buck mode or boost mode to always supply a pre–regulated output followed
by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V
@ 120mA; VDDL / 2.6V (User scalable between 3.3V – 1.25V) @ 400mA
typically, using an external NPN pass transistor. The Keep Alive regulator
VKAM (scalable) @ 50mA; FLASH memory programming voltage VPP /
Freescale Semiconductor, Inc...
5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V

44–Lead HSOP
(tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to DH SUFFIX
supply 125mA clamped to 17V. CASE 1291
Additional features include Active Reset circuitry watching VDDH,
VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT),
Power Sequencing circuitry guarantees the core supply voltages never
exceed their limits or polarities during system power up and power down.
A high speed CAN transceiver physical layer interfaces between the
microcontroller CMOS outputs and differential bus lines. The CAN driver is
44–Lead QFN
short circuit protected and tolerant of loss of battery or ground conditions.
FC SUFFIX
33394 is designed specifically to meet the needs of modules, which use CASE 1310
the MPC565 microcontroller, though it will also support others from the (BOTTOM VIEW)
MPC5XX family of Motorola microcontrollers.
Features:
• Wide operating input voltage range: +4.0V to +26.5V (+45V transient).
• Provides all regulated voltages for MPC5XX MCUs and other ECU’s
logic and analog functions.
• Accurate power up/down sequencing.
• Provides necessary MCU support monitoring and fail–safe support. 54–Lead SOICW–EP
• Provides three 5.0 V buffer supplies for internal & external (short–circuit DWB SUFFIX
CASE 1377
protected) sensors.
• Includes step–down/step–up switching regulator to provide supply
voltages during different battery conditions.
• Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by PIN CONNECTIONS
means of Serial Peripheral Interface. GND 1 CANTXD
CANL CANRXD
PIN CONNECTIONS CANH /PORESET
HRT /HRESET
/SLEEP /PRERESET
VPRE_S
VCOMP
VBAT 1 SW1
VREF2
VREF3
N/C N/C
VDDH
VPRE
SCLK
VBAT SW1 CS VDDL_FB

INV
DO
CS
DI
KA_VBAT SW1 DI VDDL_B

VIGN BOOT SCLK VDDL_X
VKAM SW2G DO VDD3_3FB
GND 1 /SLEEP
VKAM_FB GND N/C VDD3_3
SW2G HRT
VSEN INV VREF3 VPP
BOOT CANH
REGON VCOMP VREF2 VPP_EN
SW1 CANL
SW1 GND
WAKEUP VPRE VDDH SOICW VREF1
VREF1 VPRE_S VPRE_S WAKEUP
SW1 QFN CANTXD VPP_EN HSOP VDDH VPRE REGON
VBAT CANRXD
VBAT VPP VREF2 VCOMP VSEN
/PORESET VDD3_3 VREF3
KA_VBAT /HRESET INV VKAM_FB
VIGN VDD3_3FB DO GND VKAM
/PRERESET
VKAM VDDL_X SCLK SW2G VIGN
VDDL_FB VDDL_B DI BOOT N/C
VDDL_FB CS N/C KA_VBAT
/PRERESET /SLEEP
VKAM_FB
VDD3_3
VREF1
VDD3_3FB
VPP
VSEN
VPP_EN
VDDL_X
VDDL_B
WAKEUP
REGON
SW1 VBAT
/HRESET HRT SW1 VBAT
/PORESET CANH SW1 VBAT
CANRXD CANL SW1 VBAT
CANTXD GND SW1 VBAT
TOP VIEW
This document contains information on a new product. Specifications

and information herein are subject to change without notice.
 Motorola, Inc. 2002 For More Information On This Product,

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MOTOROLA ANALOG INTEGRATED CIRCUIT to: www.freescale.com
DATA 1
Freescale Semiconductor,
33394 Inc.
To Q3 Figure 1. 33394DH – Simplified Block Diagram and Typical Application L1
Lf1
Dp1 6.8 H m VBAT SW1
47 H m D2
VPRE
5.6 V
+ + 1, 2 42–44 +
+ Cf1 Cf2 Oscillator C1
Dp2 10 F m 100 Fm Cb
100 nF 100 Fm
Feed
– Forward BOOT D1
KA_VBAT Ramp Buck High–Side
Generator Drive 41
3 Control
ON Logic SW2G
4.7 k VIGN Low–Side Q1
Control Boost Drive 40
OFF 4 GND MTD20N03HDL
10 nF 39
+
–
2.6 V VKAM
VKAM
+ 22 k
5 Keep–Alive
Adj. Volt. 40 k
Cc3
3.3 nF
INV
10 nF 22 F m VKAM_FB 60 mA
I–Lim +
–
38
+ Rc3
6 – Rc2
20 k 11.7 k 100 pF Cc1 100 k 430R
Vbg
VCOMP 1.0 nF Cc2
VSEN
VSEN VBAT Volt. 37 VPRE
7 125 mA
T–Lim, I–Lim 36 VPRE_S
REGON 35
8 CANRXD Enable
WAKEUP
9 Sleep
VREF1 VDDH
5.0 V VREF1 5.0 V CAN 5.0 V VDDH 5.0 V
100 mA Wakeup 400 mA
+ 10 LDO Logic LDO 34 +
T–Lim, I–Lim T–Lim, I–Lim 10 nF
10 nF 1.0 Fm 47 F m
Vbg
VPP_EN VPP VREF2
5.0 V/3.3 V 5.0 V VREF2 5.0 V
11 150 mA Band Gap 100 mA
VPP
+
5.0 V/3.3 V Reference 33
LDO LDO
+ 12 T–Lim, I–Lim T–Lim, I–Lim
1.0 Fm
10 nF
10 nF m
47 F
VDD3_3 VDD3_3 VREF3
3.3 V 5.0 V VREF3 5.0 V
13 Standby
120 mA 100 mA
3.3 V VDD3_FB LDO, Pass Control LDO 32 +
+ VQ3
14 T–Lim, I–Lim T–Lim, I–Lim
1.0 Fm
10 nF
10 nF 47 F m VPRE
VDDL_B VDDL Drive DO
16 Bit 31
15 Adj. Volt. SCLK
Q2 Q3 VDDL_X SPI
40 mA 30
MJD31C MJD31C 16 VDDL_FB Dual Pass Control DI
VDDL Fault Rep. 29
2.6 V T–Lim CS
17 28
+ 110R
VDDH
/PRERESET 18 Sleep
10 nF 47 Fm /HRESET 19
Reset
Detection 27
/SLEEP 5.0 V
100R VDDH,
/PORESET VDD3_3, High–Speed CAN HRT 47 k
VDDL Transceiver POR Timer
20 26
10 k 10 k 10 k
1.0 F m
21 22 23 24 25
VKAM CANRXD CANH CANL
2.6 V CANTXD
GND 120 R
Notes: 1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins).
Notes: 2.VDDL and VKAM are adjustable to support current microprocessor technology (1.25 V to 3.3 V) by means of an external resistor divider.
Notes: 3. When the 33394 CAN transceiver is not used, CANL and CANH pins can be shorted together.
Notes: 4. Dp1 = reverse battery protection diode. Dp2 = load dump protection diode. Dp1, Dp2 can be ommitted in those applications which do not require such protection.
For More Information On This Product,

2 Go to: www.freescale.com
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33394 Inc.
PIN FUNCTION DESCRIPTION (44–HSOP Package)
PIN NO. NAME DESCRIPTION
1 VBAT Battery supply to IC (external reverse battery protection needed in some applications)
3 KA_VBAT Keep alive supply (with internal protection diode)
4 VIGN Turn–On control through ignition switch (with internal protection diode)
5 VKAM VDDL tracking Keep Alive Memory (Standby) supply
6 VKAM_FB VKAM output feedback
7 VSEN Switched battery output
8 REGON Regulator “Hold On” input
9 WAKEUP CAN wake up event output
10 VREF1 VDDH tracking linear regulator 1
11 VPP_EN VPP enable
12 VPP 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3
13 VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor
14 VDD3_3FB VDD3_3 output feedback
15 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only
16 VDDL_B VDDL external pass transistor base drive
17 VDDL_FB VDDL output feedback
18 /PRERESET Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset)
19 /HRESET Open drain / HRESET (Hardware Reset) output
20 /PORESET Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.
21 CANRXD CAN receive data (DOUT)
22 CANTXD CAN transmit data (DIN)
23 GND Ground
24 CANL CAN differential bus drive low line
25 CANH CAN differential bus drive high line
26 HRT Hardware Reset Timer pin (programmed with external capacitor and resistor)
27 /SLEEP Sleep Mode & Power Down control
28 CS SPI chip select
29 DI SPI serial data in
30 SCLK SPI clock input
31 DO SPI serial data out
34 VDDH 5.0 V regulated supply output
35 VPRE_S Switching pre–regulator output sense
36 VPRE Switching pre–regulator output
37 VCOMP Switching pre–regulator compensation (error amplifier output)
38 INV Switching pre–regulator error amplifier inverting input
39 GND Ground
40 SW2G External power switch (MOSFET) gate drive — Boost regulator
41 BOOT Bootstrap capacitor
42 SW1 Source of the internal power switch (n–channel MOSFET)
NOTE: The exposed pad of the 44 HSOP package is electrically and thermally connected with the IC ground.

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DATA 3
33394 Inc.
PIN FUNCTION DESCRIPTION (44–QFN Package)
1 GND Ground
2 SW2G External power switch (MOSFET) gate drive — Boost Reg.
9 KA_VBAT Keep alive battery supply (with internal protection diode)
10 VIGN Turn on control through ignition switch (with internal protection diode)

29 GND Ground
NOTE: The exposed pad of the 44 QFN package is electrically and thermally connected with the IC ground.

33394 Inc.
PIN FUNCTION DESCRIPTION (54 SOICW–EP Package)
1 GND Ground
6 N/C No Connect
11 N/C No Connect

19 GND Ground
20 SW2G External power switch (MOSFET) gate drive — Boost regulator
33 KA_VBAT Keep alive supply (with internal protection diode)
34 N/C No Connect
35 VIGN Turn–On control through ignition switch (with internal protection diode)
49 N/C No Connect
NOTE: The exposed pad of the 54 SOICW–EP package is electrically and thermally connected with the IC ground.

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DATA 5
33394 Inc.
1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur.
Voltage parameters are absolute voltages referenced to ground.)
Parameter Min. Max. Unit
Supply Voltage (VBAT), Load Dump –0.3 +45 V
Supply Voltage (KA_VBAT, VIGN), Load Dump –18 +45 V
Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM) –0.3 +5.8 V
Supply Voltages (VREF1, VREF2, VREF3, VSEN) –2.0 +18 V
CANL, CANH (0<VBAT<18 VDC no time limit) –18 +26.5 V
ESD Voltage
Human Body Model all pins (Note 1) –2.0 +2.0 kV
Machine Model all pins (Note 2) –200 +200 V
CANLesd, CANHesd (Note 1) –4.0 +4.0 kV
CANLesd, CANHesd (Note 2) –200 +200 V
CANLtransient, CANHtransient (Note 3) –200 +200 V
/SLEEP –18 +45 V
REGON, VPP_EN, /HRESET, /PORESET, /PRERESET, HRT, DO, DI, CS, SCLK –0.3 +7.0 V
CANTXD, CANRXD –0.3 +7.0 V

Operational Package Temperature [Ambient Temperature] –40 +125 °C
Storage Temperature –65 +150 °C
Power Dissipation (TA = 125_C)
44 HSOP (Note 4) 8.3 W
44 QFN (Note 4) 5.0 W
54 SOICW–EP (Note 4) 5.0 W
Lead Soldering Temperature (Note 5) 260 _C
Maximum Junction Temperature +150 °C
RθJA, Thermal Resistance, Junction to Ambient (44 HSOP) (Note 6) 41 °C/W
RθJC, Thermal Resistance, Junction to Case (44 HSOP) (Note 7) 0.2 °C/W
RθJB, Thermal Resistance, Junction to Base (44 HSOP) (Note 8) 3 °C/W
RθJA, Thermal Resistance, Junction to Ambient (44 QFN) (Note 6) 77 °C/W
RθJC, Thermal Resistance, Junction to Case (44 QFN) (Note 7) 1.7 °C/W
RθJB, Thermal Resistance, Junction to Base (44 QFN) (Note 8) 5.0 °C/W
RθJA, Thermal Resistance, Junction to Ambient (54 SOICW–EP) (Note 6) 52 °C/W
RθJC, Thermal Resistance, Junction to Case (54 SOICW–EP) (Note 7) 1.2 °C/W
RθJB, Thermal Resistance, Junction to Base (54 SOICW–EP) (Note 8) 8.1 °C/W
1. Human body model: C = 100 pF, R = 1.5 kΩ.
2. Machine model: C = 200 pF, R = 10 Ω and L = 0.75 µH. In case of a discharge from pin CANL to pin GND: – 100 V < CANL transient < +100
V; in case of a discharge from pin CANH to Vcc: –150 V < CANH transient < +150 V.
3. The waveforms of the applied transients is in accordance with ”ISO 7637 part 1” test pulses 1, 2, 3a and 3b.
4. Maximum power dissipation at indicated junction temperature.
5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering
time/temperature limits.
6. Thermal resistance measured in accordance with EIA/JESD51–2.
7. Theoretical thermal resistance from the die junction to the exposed pad.
8. Thermal resistance measured in accordance with JESD51–8.
2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted)
Parameter Value Unit
Supply Voltages (VBAT, KA_VBAT) 4.0 to 26.5 V
Switching Regulator Output Current (IVPRE) (Note 1) 0 to 1.2 A
VDDH Output Current 0 to 400 mA
VDD3_3 Output Current 0 to 120 mA
VDDL_B Pass Transistor Base Drive Current 0 to 40 mA
VPP Output Current 0 to 150 mA
VREF Output Current 0 to 100 mA
VSEN Output Current 0 to 125 mA
VKAM Standby Output Current (normal mode of operation) 0 to 60 mA
VKAM Standby Output Current (standby mode of operation) 0 to 12 mA
1. See Typical Application Diagram in Figure 1.

33394 Inc.
3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
GENERAL
Start Up Voltage VBATstart 6.2 V
Power Dissipation, VBAT = 13.3 V (Buck Mode) 1.8 W
Undervoltage Shut Down VBATUV 3.4 3.9 V
Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V; IVBAT(sleep) 750 1000 µA
IVKAM = 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V
Battery Input Current, Keep Alive Mode 12 mA
VIGN = 0; IVKAM = –10 mA
Power On Current, Regulator ON with no load on VDDH, VDD3_3, IVBAT(no load) 27 mA
VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V
Battery Input Current, VPRE = –1.0 A, VBAT = 4.5 V IVBAT(4.5) 2.2 3.0 A
Battery Input Current, VPRE = –1.0 A, VBAT = 9 V IVBAT(9) 1.5 A
Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V IVBAT(13.3) 1.2 A

Battery Input Current, VPRE = –1.0 A, VBAT = 18 V IVBAT(18) 1.1 A
MODE CONTROL
VIGN Input Voltage Threshold, REGON = 0 V VIH 2.8 3.15 3.4 V
VBAT = 13.3 V; Battery Voltage = 14 V VIL 1.7 2.0 2.3
VIGN Hysteresis 0.7 1.0 1.5 V
VIGN Pull–Down Current, REGON = 0V RPD 40 100 150 µA
VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V
REGON Input High Voltage Threshold VIH 1.3 1.65 2.1 V
REGON Input Low Voltage Threshold VIL 0.8 1.35 1.5 V
REGON Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V
REGON Pull–Down Current, REGON = VDDH to VIL(min) RPD 10 20 50 µA
/SLEEP Input High Voltage Threshold VIH 1.7 2.2 2.6 V
/SLEEP Input Low Voltage Threshold VIL 1.4 1.9 2.2 V
/SLEEP Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V
/SLEEP Pull–Down Current, /SLEEP = VDDH to VIL(min) RPD 10 20 50 µA
VPP_EN Input High Voltage Threshold VIH 1.3 1.65 2.1 V
VPP_EN Input Voltage Low Threshold VIL 0.8 1.35 1.5 V
VPP_EN Pull–Down Current, VPP_EN = VDDH to VIL(min) RPD 10 20 50 µA

GoDEVICE
DATA 7
33394 Inc.
DC CHARACTERISTICS:
BUCK CONVERTER
Buck Converter Output Voltage, VBAT = 7.5V to 18V; ILOAD=500mA VPRE 5.4 5.6 5.8 V
Buck to Boost Mode Threshold Voltage (Note 1) VBATthd 6.7 V
Boost to Buck Mode Threshold Voltage (Note 1) VBATthu 7.2 V
N–channel power MOSFET SW1
SW1 Drain–Source Breakdown Voltage (Note 1) BVDSS 50 V
SW1 Continuous Drain Current IDSW1 –2.75 A
SW1 Drain–Source Current Limit IscSW1 –2.5 –3.0 –3.5 A
SW1 Drain–Source On–Resistance; ID = 1.0 A, VBAT = 9.0 V RDS(on) 300 mΩ
Error Amplifier (Design Information Only)
Input Offset Voltage (Note 1) VOS 20 mV
DC Open Loop Gain (Note 1) AVOL 80 dB

Unity Gain Bandwidth (Note 1) BW 1.5 MHz
Output Voltage Swing — High Level (Note 1) VOH 4.2 V
Output Voltage Swing — Low Level (Note 1) VOL 0.4 V
Output Source Current (Note 1) IOUT 1.0 mA
Output Sink Current (Note 1) IOUT 200 µA
Ramp Generator
Sawtooth Peak Voltage (Note 1) VOSC 3.5 V
Sawtooth Peak–to–Peak Voltage (Note 1) VOSCp–p 3.0 V
BOOST CONVERTER
External Power MOSFET Gate Drive SW2G
Boost Converter Output Voltage, VBAT = 4.5 V to 6.0 V (Note 1) VPRE 5.9 6.0 6.6 V
SW2G Output Voltage, Power MOSFET On (Note 1) Vg VPRE V
SW2G Source Continuous Current (Note 1) Isource TBD mA
SW2G Sink Continuous Current Isink 200 300 400 mA
AC CHARACTERISTICS:
BUCK CONVERTER
Oscillator Frequency Freq 180 200 220 kHz
SW1 Switch Turn–ON Time (Note 1) tT–ON TBD ns
SW1 Switch Turn–OFF Time (Note 1) tT–OFF TBD ns
SW2G Switch Turn–ON Time, Cgate = pF (Note 1) tT–ON TBD ns
SW2G Switch Turn–OFF Time, Cgate = pF (Note 1) tT–OFF TBD ns
OFF Time (Note 1) tOFF 1.25 µs
Duty cycle (Note 1) d 75 %
NOTE:
1. Guaranteed by design but not production tested.

33394 Inc.
DC CHARACTERISTICS:
VDDH
VDDH Output Voltage, IVDDH = –400 mA; VDDH 4.9 5.0 5.1 V
VDDH Load Regulation, VBAT = 13.3 V; IVDDH = 0 to –400 mA; LoadRgVDDH –40 40 mV
VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; IVDDH = –400 mA; LineRgVDDH –20 20 mV
VDDH Drop Out Voltage, VPRE – VDDH, IVDDH = –400 mA; VDOV 450 mV
Decrease VBAT until Resets asserted
VDDH Output Current, VBAT = 4.0 V to 26.5 V IVDDH –400 mA
VDDH Short Circuit Current, VDDH = 0 V ISC –750 –440 mA
VDDH Maximum Allowed Feedback Current (Note 1) 135 µA
(Power Up Sequence Guaranteed) (Note 2)
VDDH Reset Voltage, Range of VDDH where Resets must remain VVDDH_HRST 0.5 4.8 V
asserted
Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C

Thermal Shutdown Hysteresis (Note 1) TSHYS 5.0 20 °C
VDD3_3
VDD3_3 Output Voltage, IVDD3_3 = –120 mA; VDD3_3 3.21 3.3 3.36 V
VDD3_3 Load Regulation, VBAT = 13.3 V; IVDD3_3 = 0 to –120 mA LoadRgVDD3 –40 40 mV
VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; IVDD3_3 = –120mA LineRgVDD3 –20 20 mV
VDD3_3 Drop Out Voltage, VPRE – VDD3_3 VDOV 2.04 V
IVDD3_3 = –120 mA; Decrease VBAT until Resets asserted
VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V IVDD3_3 –120 mA
VDD3_3 Short Circuit Current, VDD3_3 = 0 V ISC –320 –130 mA
VDD3_3 Maximum Allowed Feedback Current (Note 1) 135 µA
(Power Up Sequence Guaranteed) (Note 2)
VDD3_3 Reset Voltage VVDD3_HRST 0.5 3.1 V
Range of VDD3_3 where Resets must remain asserted
VDDL
VDDL Feedback Reference Voltage, pin VDDL_FB VDDLREF 1.242 1.267 1.292 V
IVDDL_B = 0 to –40 mA
VDDL Load Regulation, VBAT = 13.3 V; IVDDL_B = 0 to –40 mA LoadRgVDDL –1.6 0 %
VDDL Line Regulation LineRgVDDL –0.8 0.8 %
VBAT = 4.0 V to 26.5 V; IVDDL_B = –40 mA
VDDL Drop Out Voltage, VPRE – VDDL VDOV 1.3 V
IVDDL = –400 mA; VBAT decreases until Resets asserted
VDDL Reset Voltage, (Note 1) VVDDL_HRST 0.5 VDDL V
Range of VDDL where Resets must remain asserted –5%
VDDL Susceptibility to Feeding Back (Note 3) VDDLREF 0.187 V
(Power Up Sequence Guaranteed)
VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V IVDDL_B –40 mA
VDDL_B Drive Short Circuit Current IscVDDL_B –100 –45 mA
VDDL_B = 0V, VBAT = 7.5V to 26.5V
VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V IVDDL_B –40 mA
VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6V IscVDDL_X –100 –45 mA
VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V IVDDL_FB 0 2.0 µA
NOTE:
2. Maximum allowed current flowing back into the regulator output.
3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing.

GoDEVICE
DATA 9
33394 Inc.
DC CHARACTERISTICS:
VKAM
VKAM Feedback Reference Voltage, pin VKAM_FB VKAMREF 1.242 1.267 1.292 V
Normal Mode (switcher running), IVKAM = 0 to –50mA
VKAM Load Regulation, VBAT = 13.3 V; IVKAM = –0 to –50 mA LoadRgVKAM –1.6 0 %
VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; IVKAM = –50 mA LineRgVKAM –0.8 0.8 %
VKAM Tracking to VDDL Voltage, VDDL – VKAM VTVKAM –1.6 0.8 %
VBAT = 4.0 V to 26.5 V; IVKAM = 0 to –50 mA, IVDDL = 0 to –400mA
VKAM Feedback Voltage — Power Down Mode VKAM 0.675 V
3.0 V ≤ Battery Voltage ≤ 26.5 V, IVKAM = –12 mA
VKAM Reset Voltage (/PORESET) VVKAM_HRST 0.5 VKAM V
Range of VKAM where Resets must remain asserted –5%
VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V IVKAM –50 mA
VKAM Output Current (Sleep Mode and when VBAT ≤ 4.0 V) IVKAM(sleep) –12 mA
VKAM Short Circuit Current, VKAM = 0 V ISC –140 –50 mA
VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V IVKAM_FB 0 2.0 µA
VKAM Output Capacitance Required, Capacitor Initial Tolerance 10% 22 100 µF
VPP
VPP 5.0V Output Voltage (Default), IVPP = –150 mA VPP5 4.86 5.0 5.12 V
VPP 3.3 V Output Voltage (Programmed by SPI) VPP3 3.22 3.3 3.38 V
IVPP = –150 mA
VPP Load Regulation, VBAT = 13.3 V; IVPP = 0 to –150 mA LoadRgVPP –0.8 0.8 %
VPP Line Regulation, VBAT = 4.0 V to 26.5 V; IVPP = –150 mA LineRgVPP –0.4 0.4 %
VPP Tracking to VDDH Voltage, VDDH – VPP, VTVPP –0.8 0.8 %
VBAT = 4.0 V to 26.5 V; IVPP = 0 to –150 mA;
IVDDH = 0 to –400 mA
VPP Drop Out Voltage, VPRE — VPP (VPP set to default 5.0V) VDOV 0.4 V
IVPP = –150 mA; Decrease VBAT until VPP is out of specification
(less than 4.86 V)
VPP Output Current, VBAT = 4.0 V to 26.5 V IVPP –150 mA
VPP Short Circuit Current, VPP = 0 V ISC –360 –165 mA
NOTE:

33394 Inc.
DC CHARACTERISTICS:
VREF1, 2, 3
VREF Output Voltage, IVREF = –100 mA VREF 4.86 5.0 5.12 V
VREF Load Regulation, VBAT = 13.3 V; IVREF = 0 to –100 mA LoadRgVREF –40 40 mV
VREF Line Regulation, VBAT = 4.0 V to 26.5 V; IVREF = –100 mA LineRgVREF –20 20 mV
VREF Tracking to VDDH Voltage, VDDH – VREF, VTVREF –40 20 mV
VBAT = 4.0 V to 26.5 V, IVREF = 0 to –100 mA;
IVDDH = 0 to –400 mA
VREF Drop Out Voltage, VPRE–VREF VDOV 0.4 V
IVREF = –100 mA; Decrease VBAT until VREF is out of specification
(less than 4.86 V)
VREF Output Current, VBAT = 4.0 V to 26.5 V IVREF –100 mA
VREF Short Circuit Current, VREF = –2.0 V ISC –260 –110 mA
VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V IstbVREF 40 mA

VREF Leakage Current, VREF disabled, VREF = –2.0 V ILKVREF –2.0 mA
VSEN
VSEN Saturation Voltage, IVSEN = 0 to –125 mA, VBAT= 8 to 16 V VSENsat 0.2 V
VSEN Output Voltage Limit, IVSEN = 0 to –125mA, VBAT= 16 to 26.5V VSENlimit 16 17 21 V
VSEN Short Circuit Current, VSEN = –2.0 V IscVSEN –290 –140 mA
VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V IstbVSEN 40 mA
VSEN Leakage Current, VSEN disabled, VSEN = –2.0 V ILKVSEN 200 µA
NOTE:

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DATA 11
33394 Inc.
DC CHARACTERISTICS:
SUPERVISORY OUTPUTS
Reset Voltage Thresholds
/HRESET to follow /PRERESET by 0.7 µs
VDDH Reset Upper Threshold Voltage (Note 1) 5.2 V
VDDH Reset Lower Threshold Voltage (Note 1) 4.8 V
VDD3_3 Reset Upper Threshold Voltage (Note 1) 3.43 V
VDD3_3 Reset Lower Threshold Voltage (Note 1) 3.17 V
VDDL Reset Upper Threshold Voltage (Notes 1, 4) 1.35 V
VDDL Reset Lower Threshold Voltage (Notes 1, 4) 1.2 V
/PORESET Voltage Threshold
VKAM Reset Upper Threshold Voltage (Notes 2, 5) 1.35 V
VKAM Reset Lower Threshold Voltage (Notes 2, 5) 1.2 V

/PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage 7.0 V
(Note 3)
/PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current, 1.0 mA
Vreset< 0.4 V
/PRERESET, /HRESET, /PORESET Low–Level Output Voltage, 0.5 V
IOL = 1.0 mA
/PRERESET /HRESET /PORESET Leakage Current 15 µA
WAKEUP High–Level Output Voltage, IOH = –800µA VDDH–0.8 V
WAKEUP Low–Level Output Voltage, IOL = 1.6 mA 0.4 V
HRT Voltage Threshold 2.49 2.53 2.57 V
HRT Sink Current 1.0 mA
HRT Leakage Current 5.0 µA
HRT Saturation Voltage, HRT Current = 1 mA 0.4 V
AC CHARACTERISTICS:
SUPERVISORY OUTPUTS
/PORESET Delay 7.0 10 15 ms
Delay time from VKAM in regulation and stable to the release of
/PORESET
Reset Delay Time 10 20 50 µs
Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset
(/PORESET, /PRERESET)
/HRESET Delay Time 0.5 0.7 1.0 µs
Time From /PRERESET low to /HRESET low
VDDH, VDDL, VREF Power Up Sequence 800 µs
Max Power Up Sequence Time Dependent on Output Load
Characteristics. (Note 3)
NOTE:
1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET.
2. VKAM regulator output supervised by /PORESET.
4. Measured at the VDDL_FB pin.
5. Measured at the VKAM_FB pin.

33394 Inc.
DC CHARACTERISTICS:
CAN Transceiver (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL)
CAN Transceiver Supply Current (dominant), VCANTXD = 0V IDD(CAN) 30 50 70 mA
CAN Transceiver Supply Current (recessive), VCANTXD = VDDH IDD(CAN) 2.5 5 10 mA
Transmitter Data Input CANTXD
High–Level Input Voltage Threshold (recessive), Vdiff<0.5V VIH 1.4 2.0 V
Low–Level Input Voltage Threshold (dominant), Vdiff>1.0V VIL 0.8 1.4 V
High–Level Input Current, VCANTXD = VDDH IIH –5 0 +5 µA
Low–Level Input Current, VCANTXD = 0V IIL –10 –15 –30 µA
CANTXD Pull–up Current, VCANTXD = 0V to VIH(max) IPU –10 –60 µA
CANTXD Input Capacitance (Note 1) CI(TXD) 5 10 pF
Receiver Data Output CANRXD
High–Level Output Voltage VOH VDDH VDDH V

VCANTXD = VDDH, ICANRXD = –0.8 mA –0.8
Low–Level Output Voltage, VCANTXD = 0, ICANRXD = 1.6 mA VOL 0.4 V
High–Level Output Current, VCANRXD = 0.7VDDH IOH –800 µA
Low–Level Output Current, VCANRXD = 0.4V IOL 1.6 mA
BUS Lines CANH, CANL
Output Voltage CANH (recessive) VCANH(r) 2.0 2.5 3.0 V
VCANTXD = VDDH; RL = open
Output Voltage CANL (recessive) VCANL(r) 2.0 2.5 3.0 V
VCANTXD = VDDH; RL = open
Output Current CANH (recessive) IO(CANH)(r) 100 µA
VCANTXD = VDDH; VCANH, VCANL = 2.5V
Output Current CANL (recessive) IO(CANL)(r) –100 µA
VCANTXD = VDDH; VCANH, VCANL = 2.5V
Output Voltage CANH (dominant), VCANTXD = 0V VCANH(d) 2.75 3.5 4.5 V
Output Voltage CANL (dominant), VCANTXD = 0V VCANL(d) 0.5 1.5 2.25 V
Differential Output Voltage (dominant) VCANH(d) – VCANL(d) VOdiff(d) 1.5 2.0 3.0 V
VCANTXD = 0V
Differential Output Voltage (recessive) VCANH(r) – VCANL(r) VOdiff(r) 0 0.5 V
VCANTXD = VDDH
Differential Input Common Mode Voltage Range VCM –2.0 7.0 V
Differential Receiver Threshold Voltage (recessive) VRXDdiff(th) 0.5 0.75 1.0 V
VCANTXD = VDDH, VCANRXD < 0.4V, – 2.0V < VCM < 7.0V
Differential Receiver Input Voltage Hysteresis VIdiff(hys) 0.10 0.2 0.30 V
Short Circuit Output Current CANH ISC(CANH) –70 –200 mA
VCANH = – 8.0V, VCANTXD = 0V
Short Circuit Output Current CANL ISC(CANL) 70 200 mA
VCANL = VBAT = 18V, VCANTXD = 0V
Loss of Ground — see Figure 11. Refer to Figure 10 for loading considerations.
Output Leakage Current CANH, VCANH = –18V IOLKG(CANH) –2.0 2.0 mA
Output Leakage Current CANHL, VCANL = –18V IOLKG(CANL) –2.0 2.0 mA
Loss of Battery — see Figure 12. Refer to Figure 10 for loading considerations.
Input Leakage Current CANH, VCANH = 6.0V IILKG(CANH) –800 800 µA
Input Leakage Current CANHL, VCANL = 6.0V IILKG(CANL) –800 800 µA
NOTE:

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DATA 13
33394 Inc.
DC CHARACTERISTICS:
CAN Transceiver (Continued) (Bus Load CANH to CANL RL = 60 Ω; Vdiff = VCANH – VCANL)
CANH,CANL impedance
CANH Common Mode Input Resistance Ri(CM)CANH 5.0 25 50 kΩ
CANL Common Mode Input Resistance Ri(CM)CANL 5.0 25 50 kΩ
CANH, CANL Common Mode Input Resistance Mismatch Ri(CM)MCAN –3.0 3.0 %
100(RiCANH – Ri(CM)CANL )/[ (RiCANH + Ri(CM)CANL )/2]
Differential Input Resistance RI(dif) 25 50 75 kΩ
CANH Input Capacitance, VCANTXD = VDDH (Note 1) CI(CANH) 7.5 20 pF
CANL Input Capacitance, VCANTXD = VDDH (Note 1) CI(CANL) 7.5 20 pF
Differential Input Capacitance, CINCANH – CINCANL, CI(CANdif) 3.75 10 pF
VCANTXD = VDDH (Note 1)
Thermal Shutdown
AC CHARACTERISTICS:
CAN Transceiver
Timing Characteristics
See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load RL = 60 Ω differential.
Delay CANTXD to Bus Active, CL = 3nF tonTXD 50 ns
Delay CANTXD to Bus Inactive, CL = 10pF toffTXD 80 ns
Delay CANTXD to CANRXD, Bus Active, CL = 3nF tonRXD 120 ns
Delay CANTXD to CANRXD, Bus Inactive, CL = 10pF toffRXD 190 ns
NOTE:
VDDH (5V)
CANTxD
0V
CANH = 3.5V (Dominant bit)
CANH (Recessive bit)
Vdiff 2.5 V
CANL (Recessive bit) CANL = 1.5V (Dominant bit)
0.9 V
Vdiff 0.5 V
VDDH (5V)
CANRxD 0.7VDDH
0.3VDDH
0V
tonTxD
toffTxD
tonRxD toffRxD
Figure 2. CAN Delay Timing Waveform

33394 Inc.
DC CHARACTERISTICS:
SPI
DO Output High Voltage, IOH = –100 µA VOH 4.2 V
DO Output Low Voltage, IOL = 1.6 mA VOL 0.4 V
DO Tri–state Leakage Current, CS = 0 IDOLkg –10 10 µA
CS, SCLK, DI Input High Voltage VIH 2.7 3.1 3.5 V
CS, SCLK, DI Input Low Voltage VIL 1.7 2.1 2.5 V
CS, SCLK, DI Input Voltage Threshold Hysteresis VIhys 0.8 1.0 1.2 V
CS, SCLK, DI Pull–Down Current, ISPI_PD 10 20 50 µA
CS, SCLK, DI = VDDH to VIL(min)
AC CHARACTERISTICS:
SPI
NOTES: MPC565 QSMCM/ SPI set for CPHA = 0 & CPOL = 0. *Assumes MPC565 SCLK rise and fall times of 30 ns, DO load = 200pF
– Transfer Frequency fop dc 5.00 MHz
1 SCLK Period tsck 200 – ns
2 Enable Lead Time tlead 105 – ns
3 Enable Lag Time tlag 50 – ns
4 SCLK High Time* tsckhs 70 – ns
5 SCLK Low Time* tsckls 70 – ns
6 SDI Input Setup Time tsus 16 – ns
7 SDI Input Hold Time ths 20 – ns
8 SDO Access Time ta – 75 ns
9 SDO Disable Time tdis – 100 ns
10 SDO Output Valid Time tvs – 75 ns
11 SDO Output Hold Time tho 0 – ns
12 Rise Time (Design Information) (Note 1) tro – 30 ns
13 Fall Time (Design Information) (Note 1) tfo – 30 ns
14 CS Negated Time (Note 1) tcsn 500 – ns
NOTE:
3 14
20% and 70% of Vdd typ.
CS
2 4 1
SCLK
5
8 10 11 9
DO LSB OUT DATA MSB OUT DON’T
CARE
6 7 12 13
DI LSB IN DATA MSB IN
Figure 3. SPI Timing Diagram

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DATA 15
33394 Inc.
4. FUNCTIONAL DESCRIPTION
The 33394 is an integrated buck regulator/linear supply output are brought out to enable the control loop to be
specifically designed to supply power to the Motorola externally compensated. The compensation technique is
MPC55x/MPC56x microprocessors. A detailed functional described in paragraph 5.2.3. Buck Converter Feedback
description of the Buck Regulator, Linear Regulators, Power Compensation in the Application Information section. In
Up/Down Sequences, Thermal Shutdown Protection, Can order to improve line rejection, feed forward is implemented in
Transceiver Reset Functions and Reverse Battery Function the ramp generator. The feed forward modifies the ramp slope
are given below. Block diagram of the 33394 is given in Figure in proportion to the VBAT voltage in a manner to keep the loop
1. The 33394 is packaged in a 44 pin HSOP, 54 pin SOICW gain constant, thus simplifying loop compensation. At startup,
and the 44 pin QFN. a soft start circuit lowers the current limit value to prevent
potentially destructive in–rush current.
4.1. Input Power Source (VBAT, KA_VBAT & VIGN) In Boost mode, pulse–frequency modulation (PFM) control
The VBAT and KA_VBAT pins are the input power source is utilized. The duty cycle is set to 75% and the switching
for the 33394. The VBAT pins must be externally protected action is stopped either by the Boost Comparator, sensing the
from vehicle level transients greater than +45 V and reverse switcher output voltage VPRE, or by the Current Limit circuit
battery. See typical application diagram in Figure 1. The VBAT when the switching current reaches its predetermined limit
pins directly supply the pre–regulator switching power supply. value. This control method requires no external components.
All power to the linear regulators (except VKAM in the power The selection of the control method is determined by the
down mode) is supplied from VBAT through the switching control logic based on the VBAT input voltage.
regulator. VKAM power is supplied through VBAT input pins
and switching regulator when the 33394 is awake. When the 4.2.1. Switching Transistor (SW1)
microprocessor is in a power down mode (no VDDH or VDDL The internal switching transistor is an n–channel power
supply), the current requirement on VKAM falls to less than 12 MOSFET. The RDS(on) of this internal power FET is
mA. During this period the VKAM current is supplied from the approximately 0.25 ohm at +125_C. The 33394 has a nominal
reverse battery protected KA_VBAT input. instantaneous current limit of 3.0 A (well below the saturation
The KA_VBAT supply pin is the power source to the Keep current of the MOSFET and external surface mounted
Alive Memory regulator (VKAM) in power down mode. Power inductor) in order to supply 1.2 A of current for the linear
is continuously supplied regardless of the state of the ignition regulators that are connected to the VPRE pin (see Figure 1).
switch (VIGN input). The KA_VBAT input is reverse battery The input to the drain of the internal N—channel MOSFET
protected but requires external load dump protection (refer to must be protected by an external series blocking diode, for
Figure 1). reverse battery protection (see Figure 1).
The VIGN pin is used as a control input to the 33394. The
regulation circuits will function and draw current from VBAT 4.2.2. Bootstrap Pin (BOOT)
when VIGN is high (active) or REGON is high (active) or on An external bootstrap 0.1 µF capacitor connected between
CAN bus activity (WAKEUP active). To keep the VIGN input SW1 and the BOOT pin is used to generate a high voltage
W
from floating, a 10k pull–down resistor to GND should be supply for the high side driver circuit of the buck controller. The
used. The VIGN pin has a 3.0 V threshold and 1.0 volt of capacitor is pre charged to approximately 10V while the
hysteresis. VIGN is designed to operate up to +26.5 volt internal FET is off. On switching, the SW1 pin is pulled up to
battery while providing reverse battery and +45 volt load dump VBAT, causing the BOOT pin to rise to approximately
protection. The input requires ESD, and transient protection. VBAT+10V — the highest voltage stress on the 33394.
See Figure 1 for external component required.
4.2.3. External MOSFET Gate Drive (SW2G)
4.2. Switching Regulator Functional Description This is an output for driving an external FET for boost mode
A block diagram of the internal switching regulator is shown operation. Due to the fact that the gate drive supply voltage is
in Figure 4. The switching regulator incorporates circuitry to VPRE the external power MOSFET should be a logic level
implement a Buck or a Buck/Boost regulator with additional device. It also has to have a low RDS(on) for acceptable
external components. A high voltage, low RDS(on) power efficiency. During buck mode, this gate output is held low.
MOSFET is included on chip to minimize the external
components required to implement a Buck regulator. The 4.2.4. Compensation (INV, VCOMP)
power MOSFET is a sense FET to implement current limit. For The PWM error amplifier inverting input and output are
low voltage operation, a low side driver is provided that is brought out to allow the loop to be compensated. The
capable of driving external logic level MOSFETs. This allows recommended compensation network is shown in Figure 18
a switching regulator utilizing Buck/Boost topology to be and its Bode plot is in Figure 19. The use of external
implemented. Two independent control schemes are utilized compensation components allows optimization of the buck
in the switching regulator. converter control loop for the maximum bandwidth. Refer to
In Buck mode, voltage mode pulse–width modulation the paragraph 5.2.3. Buck Converter Feedback
(PWM) control is used. The switcher output voltage divided by Compensation in the Application Information section for
an internal resistor divider is sensed by an Error Amplifier and further details of the buck controller compensation.
compared with the bandgap reference voltage. The PWM
Comparator uses the output signal from the Error Amplifier as 4.2.5. Switching Regulator Output Voltage (VPRE)
the threshold level. The PWM Comparator compares the The output of the switching regulator is brought into the chip
sawtooth voltage from the Ramp Generator with the output at the VPRE pin. This voltage is required for both the switching
signal from the Error Amplifier thus creating a PWM signal to regulator control and as the supply voltage for all the linear
the control logic block. The Error Amplifier inverting input and regulators.

33394 Inc.
4.2.6. Switching Regulator Output Voltage Sense resistor divider and compared with the bandgap reference
(VPRE_S) voltage (see Figure 4).
This is the switching regulator output voltage sense input. Refer to Section 5 Application Information for detailed
The switcher output voltage VPRE is divided by an internal description of the switching regulator operation.
BOOT
SW1
VBAT
VPRE
BOOTSTRAP
SOFT
START CURRENT HS
LIMIT DRIVER
VPRE
SWITCHER LS
MODE VPRE
DRIVER
ENABLE BUCK & SW2G
BOOST VPRE_S
CONTROL
Vbg LOGIC 40 k
PWM
E/A
THERMAL COMP + – INV
LIMIT +
– 11.7 k
Vbg
1.25 V
FEED
FORWARD
VCOMP
RAMP
GENERATOR Vbg
SWITCHER
OSCILLATOR Vbg
200 kHz
+
VPRE –
Vbg
COMP
1.25 V
+
–
BOOST
COMP Vbg
1.25 V
Figure 4. Switching Regulator Block Diagram
4.3. Voltage Regulator (VDDH) output, and incorporates current limit short circuit protection
The VDDH output is a linearly regulated +5.0 +/– 0.10V and over temperature shut down protection. This output is
voltage supply capable of sourcing a maximum of 400 mA intended for FLASH memory programming and includes a
steady state current from VPRE (+5.6 V) for VBAT voltages dedicated enable pin (VPP_EN). The regulator enable can
from +4.0 V to +26.5 V (+45V transient). This regulator also be controlled through the SPI interface but requires both
incorporates current limit short circuit protection and thermal the VPP_EN pin and the SPI bit (EN_VPP bit) to be high to
shut down protection. The voltage output is stable under all enable. The selection of tracking VDDH or VDD3_3 is
load/line conditions. However, the designer must consider controlled by the VPP_V bit in the SPI. Logic “1” selects VDDH
ripple and high frequency filtering as well as regulator (default), logic “0” selects VDD3_3. The voltage output is
response, when choosing external components. See Table 1 stable under all load/line conditions. However, the designer
in the Applications Information section for recommended must consider ripple and high frequency filtering as well as
output capacitor parameters. regulator response when choosing external components. See
Table 1 for recommended output capacitor parameters.
NOTE : The VPP tracking regulator should not be used in parallel
Backfeeding into the VDDH output can cause problems with the VDDH regulator, because this arrangement can
during the power up sequence. Refer to the Electrical corrupt the proper power sequencing of the IC.
Characteristics VDDH Regulator Section for the maximum
allowed backfed current into the VDDH output. 4.5. Tracking Voltage Regulator (VREFn)
The outputs of the VREF1, VREF2, VREF3 linear regulators
4.4. Tracking Voltage Regulator (VPP) are 100 mA at +5.0 V. They track the VDDH output. The power
This linearly regulated +5.0 V/+3.3 V (SPI selectable) supplies are designed to supply power to sensors that are
voltage supply is capable of sourcing 150 mA of steady state located external to the module. These regulators may be
current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to enabled or disabled via the SPI, which also provides fault
+26.5 V (up to +45V transient). It tracks the VDDH or VDD3_3 reporting for these regulators. They are protected for short to

GoDEVICE
DATA 17
33394 Inc.
battery (+18 V) and short to –2.0 V. Precautions must be taken Applications Information section for recommended output
to protect the VREF pins from exposure to transients. See capacitor parameters.
Table 1 for recommended output capacitor parameters.
NOTES:
4.5.1. VREF Over Temperature Latch Off Feature 1. The use of an EXTERNAL pass device allows the power
If either the VREF1, VREF2 or VREF3 outputs is shorted to dissipation of the 33394 to be reduced by approximately 50%
ground for any duration of time, an over temperature shut and thereby allows the use of a thermally efficient package
down circuit disables the output source transistor once the such as an HSOP 44 or QFN 44. The base drive control
local die temperature exceeds +150°C to +190°C. The output signal (VDDL_B) is provided by on chip circuitry. The
transistor remains off until the locally sensed temperature is regulated output voltage sense signal is fed back into the on
5°C to 20°C. below the trip off temperature. The output(s) will chip differential amplifier through pin VDDL_FB. The
periodically turn on and off until either the die temperature collector of this external pass device should be connected to
decreases or until the fault condition is removed. If one of VPRE to minimize power dissipation and adequately supply
these outputs goes into over—temperature shutdown, it will 400 mA. Proper thermal mounting considerations must be
not impact the operation of any of the other outputs (assuming accounted for in the PCB design.
that no other package thermal or VPRE current limit
specifications are violated). Fault information is reported 2. Backfeeding into the VDDL output can cause problems
through the SPI communication interface (see Figure 8). during the power up sequence. Refer to the Electrical
Characteristics VDDL Regulator Section for the maximum
4.6. Voltage Regulator (VDD3_3) allowed backfed current into the VDDL output.
This linearly regulated +3.3 V +/–0.06 V voltage supply is
capable of sourcing 120 mA of steady state current from 4.8. Keep–Alive/Standby Supply (VKAM)
VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V This linearly regulated Keep Alive Memory voltage supply
transient). This regulator incorporates current limit short tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is
circuit protection and thermal protection. When no external capable of sourcing 50 mA of steady state current from VPRE
pass transistor is used the VDD3_3 and the VDD3_3FB pins during normal microprocessor operation and 12 mA through
must be shorted together — see Figure 22. The current KA_VBAT pin during stand–by/sleep mode. The VKAM
capability of the VDD3_3 output can be increased by means regulator output incorporates a current limit short circuit
of an external pass transistor — see Figure 1. When the protection. The output requires a specific range of capacitor
external pass transistor is used the VDD3_3 internal short values to be stable under all load/line conditions. See Table 1
circuit current limit does not provide the short circuit in the Applications Information section for recommended
protection. The voltage output is stable under all load/line output capacitor parameters.
conditions. However, the designer must consider ripple and
high frequency filtering as well as regulator response when NOTE :
choosing external components. See Table 1 in the The source current for the VKAM supply output depends on
Applications Information section for recommended output the sleep/wake state of the 33394.
capacitor parameters.
4.9. Switched Battery Output (VSEN)
NOTE : This is a saturated switch output, which tracks the VBAT and
Backfeeding into the VDD3_3 output can cause problems is capable of sourcing 125 mA of steady state current from
during the power up sequence. Refer to the Electrical VBAT. This regulator will track the voltage VBAT to less than
Characteristics VDD3_3 Regulator Section for the maximum 200 mV, and its output voltage is clamped at +17 V. The gate
allowed backfed current into the VDD3_3 output. voltage of the internal N—channel MOSFET is provided by a
charge pump from VBAT. There is an internal gate–to–source
4.7. Voltage Regulator (VDDL) voltage clamp. This regulator is short circuit protected and has
The output voltage of the VDDL linear regulator is independent over—temperature protection. If this output is
adjustable by means of an external resistor divider. shorted and goes into thermal shutdown, the normal operation
This linearly regulated +/–2% core voltage supply uses an of all other voltage outputs is not impacted. This output is
external pass transistor and is capable of sourcing 40 mA controlled by the SPI VSEN bit.
base drive current typically (see application circuit, Figure 1)
of steady state current. The collector of the external NPN pass NOTE:
transistor is connected to VPRE (+5.6 V) for a VBAT voltage A short to VBAT on VREF1, VREF2, VREF3 or VSEN will
from +7.5 V to +26.5 V (+45V transient). The voltage output is not result in additional current being drawn from the battery
stable under all load/line conditions. However, the designer under normal (+8 V to +18 V) voltage levels. Under jumpstart
must consider ripple and high frequency filtering as well as condition (VBAT = +26.5 V) and during load dump condition,
regulator response when choosing external components. the device will survive this condition, but additional current
Also, the dynamic load characteristics of the microprocessor, may be drawn from the battery.
relative to CPU clock frequency changes must be considered.
An additional external pass transistor, for VDDL regulation in 4.9.1. VSEN Over Temperature Latch Off Feature
the Boost mode, can be added between protected battery If the VSEN output is shorted to ground for any duration of
voltage (see Figure 1) and VDDL, with its base driven by time, an over temperature shut down circuit disables the
VDDL_X. In that arrangement the 33394’s core voltage supply output source transistor once the local die temperature
operates over the whole input voltage range VBAT = +4.0 V exceeds +150°C to +190°C. The output transistor remains off
to +26.5 V (up to +45V transient). See Table 1 in the until the locally sensed temperature drops 5°C to 20°C below

33394 Inc.
the trip–off temperature. The output will periodically turn on capacitor is used to program the timer. To minimize quiescent
and off until either the die temperature decreases or until the current during power down modes, the RC timer current
fault condition is removed. If the VSEN output goes into should be drawn from one of the VDD supplies (see Figure 1).
over—temperature shutdown, it does not impact the operation The threshold on the HRT pin has zero temperature coefficient
of any of the other outputs (assuming that no other package and is set at 2.5 V.
thermal or VPRE current limit specifications are violated).
Fault information is reported through the SPI communication 4.12. Power Up/Down Sequencing
interface (see Figure 8). The 33394 power up sequence is specifically designed to
meet the power up and power down requirements of the
4.10. Resets To Microprocessor MPC565 microprocessor. The MPC565 processor requires
/PORESET – Power On Reset, /PRERESET — Pre Reset, that VDDH remain within 3.1 volts of VDDL during power up
/HRESET– Hardware Reset. All the Reset pins are open drain and can not lag VDDL by more than 0.5 volts. This condition
‘active low’ outputs, capable of sinking 1.0 mA current and is met by the 33394 regardless of load impedance. It is critical
able to withstand +7.0 V. See Figure 1 and Figure 20 for to note that the 33394 under normal conditions is designed to
recommended pull–up resistor values and their connection. supply VKAM prior to the power up sequence on VDDH,
The /PORESET pin is pulled up to the VKAM voltage by a VDD3_3 and VDDL. During power up and power down
pull up resistor. It is connected to the microprocessor Power sequencing /PRERESET and /HRESET are held low. Power
On Reset (POR) pin, and is normally high. During initial battery up and power down sequencing is implemented in six steps.
connect the /PORESET is held to ground by the 33394. After During this process the reference voltage for VDDH, VDD3_3
the VKAM supply is in regulation and an internal 10 ms timer and VDDL is ramped up in six steps. Minimum power up/down
has expired, the /PORESET is released. If VKAM goes out of time is dependent on the internal clock and is 800 µs.
regulation the device will first pull the /PORESET and Maximum power up/down time is also dependent on load
/PRERESET followed by a 0.7 µs delay then /HRESET. By impedance. During the power up/down cycle, voltage level
/HRESET low VDDH, VDD3_3 and VDDL will start a power requirements for each step of VDDH, VDD3_3 and VDDL
down sequence. When the fault is removed a standard power must be met before the supply may advance to the next
up sequence is initiated. The VKAM linear regulator output voltage level. Hence VDDH and VDDL will remain within the
must be out of regulation for greater than 20 µs before 3.1/0.5 V window. Figure 6 illustrates a typical power up and
/PORERSET and /PRERESET (with /HRESET 0.7 µs down sequence.
delayed) are pulled low. If a fault occurs on VKAM in the
Key–Off Mode (when the VIGN is off) and the fault is then 4.13. Regulator Enable Function (REGON)
removed the VKAM will regulate but /PORESET will not be This feature allows the microcontroller to select the delayed
released until Key–On (asserting VIGN pin) allows the 10 ms shut down of the 33394 device. It holds off the activation of the
timer to run. Reset signals, to the microcontroller, after the VIGN signal has
The Reset signals (/PRERESET, /HRESET) are not transitioned and signals the request to shutdown the VDDH,
asserted when the 33394 enters Sleep Mode by asserting the VDD3_3, VDDL, VSEN and the VREFn supplies. This allows
/SLEEP pin. When exiting out of Sleep Mode the 33394 the microcontroller to delay a variable amount of time, after
asserts the Resets (/PRERESET, /HRESET) during the power sensing that the VIGN signal has transitioned and signaled the
up sequence. request to shutdown the regulated supplies. This time can be
The /PRERESET and /HRESET pins are pulled up to the used to store data to EPROM memory, schedule an orderly
VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to shutdown of peripherals, etc. The microcontroller can then
section 5. Application Information, paragraph 5.3. drive the REGON signal, to the 33394, to the low logic state,
Selecting Pull–Up Resistors for detailed description of to turn off the regulators (except for the VKAM supply).
these two connection scenarios. The 33394 monitors the main
supply voltages VDDH, VDD3_3 and VDDL. If any of these 4.14. Regulator Shutdown Function (/SLEEP)
voltages falls out of regulation limits the /PRERESET will be This feature allows for an external control element (e.g.
pulled down followed by the /HRESET after 0.7 µs delay, and microprocessor) to shut down the 33394 regulators, even if
the power down sequence will be initiated. There are several the VIGN signal (or REGON) is active, by asserting the
different scenarios how to connect the /PRERESET and /SLEEP pin from high to low (falling edge transition). In this
/HRESET pins to the microprocessor. Typically the case the 33394 initiates the power down sequence, but the
/PRERESET pin will be connected to the IRQ0 pin of the Reset signals (/PRERESET, /HRESET) are not asserted. This
microprocessor, and the /HRESET to the microprocessor allows the microprocessor to continue to execute code when
/HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL it is supplied only from the Keep Alive supply VKAM. When the
linear regulator outputs must be out of regulation for greater microprocessor exits sleep state by pulling /SLEEP pin high
than 20 µs before /PRERESET (with /HRESET 0.7 µs the Resets (/PRERESET, /HRESET) are asserted during the
delayed) are pulled low. power up sequence.
The /SLEEP pin has an internal pull down, therefore when
4.11. Hardware Reset Timer (HRT) its functionality is not used this pin can be either pulled up to
The HRT pin is used to set the delay between VDDH, VKAM, VBAT, pulled down to ground or left open.
VDD3_3 and VDDL active and stable and the release of the The /SLEEP pin should not be pulled up to VDDH.
/HRESET and /PRERESET outputs. An external resistor and

GoDEVICE
DATA 19
33394 Inc.
33394 * VDD3_3 = 3.3V (not used by MPC56x) MPC56X
Output Supply Input
VDDH = 5.0V
VDDH, VDDA, 5.0V
VDD3_3 = 3.3V* VFLASH5
VDDH
VDD3_3 NVDDL, QVDDL,
VDDL = 2.6V
VDDL VDD, VDDSYN, 2.6V
2 VDDF
VIGN 6 8
4 9 10
VKAM = 2.6V
KAPWR,
1 3 2.6V VDDSRAM1,2,3
VKAM VDDRTC
7 11
/PORESET 2.6V PORESET
10ms
/PRERESET 2.6V IRQ0
5
/HRESET HRESET
0.7ms 0.7ms 0.7ms
HRT DELAY HRT DELAY HRT DELAY
Figure 5. 33394 Timing Diagram
1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms.
2 VIGN is applied, 33394 starts power up sequence.
3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay
programmable by an external capacitor and resistor, HRT pin).
4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated.
5 /HRESET is asserted 0.7 ms after /PRERESET
6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released
(with an HRT delay).
7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET
with 0.7 ms delay) are asserted – see Note 1.
8 33394 initiates power down sequence.
9 Fault on VKAM removed, the 33394 initiates the start up sequence.
10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT
delay).
11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed.
VDDH = 5.0 V
VDD3_3 = 3.3 V
LESS THAN 3.1 V VDDL = 2.6 V*
0V POWER UP SEQUENCE POWER DOWN SEQUENCE
*NOTE: VDDL = 2.6 V for MPC565
Figure 6. 33394 Power Up/Down Sequence
* VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.

33394 Inc.
4.15. SPI Interface to Microcontroller (Serial pin be in a logic low state whenever the chip select pin (CS)
Peripheral Interface) makes any transition. For this reason, it is recommended
The pins specified for this function are: DI (Data Input), DO though not necessary, that the SCLK pin is commanded to a
(Data Output), CS (Chip Select) and SCLK. Refer to Figure 3 low logic state as long as the device is not accessed (CS in
for the 33394 SPI timing information. The delay, which is logic low state). When CS is in a logic low state, any signal at
needed from CS leading edge active to the first SCLK leading the SCLK and DI pin is ignored and the DO is tri—stated (high
edge transition (0 to 1) is approximately 125 ns. The SCLK impedance).
rate is a maximum of 5.0 MHz. The SPI function will provide
control of such 33394 features as VREFn regulator turn on/off, 4.15.3. DI (Data Input) Pin
VREFn fault reporting and CAN wake up feature activation. The DI pin is used for serial data input. This information is
Refer to Figure 7 & Figure 8 for the data and status bit latched into the input register on the rising edge of SCLK. A
assignments for the 16 bit SPI data word exchange. logic high state present on DI will program a specific function
(see Figure 7 for the data bits assignments for the 16 bit SPI
4.15.1. CS (Chip Select) Pin data word exchange.). The change will happen with the falling
The system MCU selects the 33394 to be communicated edge of the CS signal. To program the specific function of the
with through the use of the CS pin. Whenever the pin is in a 33394 a 16 bit serial stream of data is required to be entered
logic high state, data can be transferred from the MCU to the into the DI pin starting with LSB. For each rising edge of the
33394 and vice versa. Clocked—in data from the MCU is SCLK while CS is logic high, a data bit instruction is loaded into
transferred to the 33394 shift register and latched in on the the shift register per the data bit DI state. The shift register is
falling edge of the CS signal. On the rising edge of the CS full after 16 bits of information have been entered. To preserve
signal, output status information is transferred from the output data integrity, care should be taken to not transition DI as
status register into the device’s shift register. Whenever the SCLK transitions from a low to high logic state.
CS pin goes to a logic high state, the DO pin output is enabled
allowing information to be transferred from the 33394 to the 4.15.4. DO (Data Output) Pin
MCU. To avoid any spurious data, it is essential that the The serial output (DO) pin is the output from the shift
transition of the CS signal occur only when SCLK is in a logic register. The DO pin remains tri—state until the CS pin goes
low state. to a logic high state. See Figure 8 for the status bits
assignments for the 16–bit SPI data word exchange. The CS
4.15.2. SCLK (System Clock) Pin positive transition will make LSB status available on DO pin.
The shift clock pin (SCLK) clocks the internal shift registers Each successive positive SCLK will make the next bit status
of the 33394. The serial input (DI) data is latched into the input available. The DI/DO shifting of data follows a
shift register on the rising edge of the SCLK. The serial output first—in—first—out protocol with both input and output words
pin (DO) shifts data information out of the shift register also on transferring the Least Significant Bit (LSB) first.
the rising edge of the SCLK signal. It is essential that the SCLK
33394 SPI Registers:

Serial Input Data/Control
Default Value 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Name
Bit Definitions:
Bit 15 to 8 = 0
Bit 7 6 5 4 3 2 1 0 (LSB)
Name WKUP CAN_EN VPP_V EN_VPP VSEN VREF3 VREF2 VREF1
Bit Definitions:
Bit 7 — WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity
Bit 6 — CAN_EN: Enables CAN receiver, will draw small current during power off
Bit 5 — VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V
Bit 4 — EN_VPP: – Used to turn the VPP regulator off and on from the MCU
Bit 3 — VSEN: – Used to turn the VSEN regulator off and on from the MCU
Bit 2 — VREF3: – Used to turn the VREF3 regulator off and on from the MCU
Figure 7. SPI Input Data/ Control Register

GoDEVICE
DATA 21
33394 Inc.
33394 SPI Registers:
Serial Output Data/Status
Bit 15 14 13 12 11 10 9 8
Name
Bit Definitions:
Bit 15 to 8 = 0
Bit 7 6 5 4 3 2 1 0 (LSB)
Name VSEN–T VREF3–T VREF2–T VREF1–T VSEN–I VREF3–I VREF2–I VREF1–I
Bit Definitions:
Bit 7 — VSEN–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 6 — VREF3–T: – Will be set (1), if a thermal limit occurred since last SPI data transfer
Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists

Bit 2 — VREF3–I: – Will be set (1), if a current limit condition exists
NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal
Figure 8. SPI Output Data/ Status Register
4.16. CAN Transceiver controller will contain one of the terminations. The other
The CAN protocol is defined in terms of ’dominant’ and termination should be as close to the other ”end” of the CAN
’recessive’ bits. When the digital input (CANTXD) is a logic ”0” Bus as possible. The termination provides a total of 60 Ω
(negated level, dominant bit), CANH goes to +3.5 V (nominal) differential resistive impedance for generation of the voltage
and CANL goes to +1.5 V (nominal). The digital output will also difference between CANH and CANL. Current flows out of
be negated. When the digital input is logic ”1” (asserted level, CANH, through the termination, and then through CANL and
recessive bit), CANH and CANL are set to +2.5 V (nominal). back to ground. The CAN bus is not defined in terms of the bus
The corresponding digital output is also asserted. capacitance. A filter capacitor of 220 pF to 470 pF may be
required. The maximum capacitive load on the CAN bus is
4.16.1. CAN Network Topology then 15 nF (not a lumped capacitance but distributed through
There are two 120 Ω (only two), terminations between the the network cabling). Refer to Figure 9.
CANH and CANL outputs. The majority of the time, the module
Common Mode Choke

PCM 2.2 mH Max : 31 Remotes Vehicle Term.
CANH
470 pF* 470 pF*
120 W 120 W
CANL
470 pF* 470 pF*
*Optional
Figure 9. CAN Load Characteristics
4.16.2. CAN Transceiver Functional Description sensed on the CAN bus pins, the 33394 will perform a power
A block diagram of the CAN transceiver is shown in Figure up sequence and will provide the microprocessor with
10. A summary of the network topology is shown in Figure 9. indication (WAKEUP pin high) that wake up occurred from a
The transceiver has wake up capability controlled by the state CAN message. The 33394 may be placed back in low
of the SPI bit WKUP. This allows 33394 to enter a low power quiescent mode by pulling the /SLEEP pin from high to low.
mode and be awakened by CAN bus activity. When activity is

33394 Inc.
The Wake–up function can be disabled through SPI by setting input drives the outputs to a differential (dominant) voltage,
the WKUP bit to 0. where the CANH output is +3.5 V and the CANL output is +1.5
The CAN transceiver of the 33394 is designed for V. A logic ‘1’ input drives the outputs to their idle (recessive)
communications speeds up to 1.0 Mbps. The use of a state, where the CANH and CANL outputs are +2.5 V. An
common mode choke may be required in some applications. internal pull–up to VDDH shall guarantee a logic ”1” input level
When the 33394 CAN transceiver physical interface is not if this input is left open. On power–up, or in the event of a
used in the system design, the CAN bus driver pins CANH and thermal shutdown, this input must be toggled high and then
CANL should be shorted together. low to clear the thermal fault latch. The faulted CAN bus
output(s) will remain disabled until the thermal fault latch is
4.16.3. CANH cleared. The CAN bus data rate is determined by the data rate
CANH is an output driver stage that sources current on the of CANTXD.
CANH output. It’s output follows CANL, but in the opposite
polarity. The output is short circuit protected. In the event that 4.16.6. CANRXD
battery or ground is lost to the module, the CANH transmitter’s This is a CMOS compatible output used to send data from
output stage is disabled. the CAN bus pins, CANH and CANL, to the microprocessor.
When the voltage differential between CANH and CANL is
4.16.4. CANL under the differential input voltage threshold (recessive state),
CANL is an output driver stage that sinks current on the CANRXD is logic ‘1’. When the voltage differential between
CANL output. The sink type output is short circuit protected. CANH and CANL is over the voltage threshold (dominant
In the event that battery or ground is lost to the module, the state), CANRXD is logic ‘0’. In standby mode, input voltage
CANL transmitter’s output stage is disabled. threshold remains the same. There is a minimum of 0.1 V of
hysteresis between the high and low (and vice versa)
4.16.5. CANTXD transition points.
CANTXD input comes from the microcontroller and drives
that state of the CAN bus pins, CANH and CANL. A logic ‘0’
OverTemp
Sense &
Hysteresis
VDDH
VDDH CANH
Complimentary
CAN_EN
High/Low Side
10 µA Drivers w/
CANTXD Current Limit CANL
0.8 – 2.0 V
25 k W
0.5 – 1.0 V 5k W
CANRXD + + 2.5 V
– –
CANRXD AWAKE 5k W
CAN_EN
25 k W
Figure 10. CAN Transceiver Block Diagram
4.16.7. CAN Over Temperature Latch Off Feature on the module level in Figure 11. The nomenclature is suited
If the CANH or CANL output is shorted to ground or battery to a test environment. In the application, a loss of ground
for any duration of time, an over temperature shut down circuit condition results in all I/O pins floating to battery voltage. In
disables the output stage. The output stage remains latched this condition, the CAN bus must not source enough current
off until the CANTXD input is toggled from a logic ’1’ to a logic to corrupt the bus.
’0’ to clear the over temperature shutdown latch. Thermal
shutdown does not impact the remaining functionality of the 4.16.9. CAN Loss of Assembly Battery
IC. The loss of battery condition at the IC level is that the power
input pins of the IC see infinite impedance to the battery supply
4.16.8. CAN Loss of Assembly Ground voltage (depending upon the application) but there is some
The definition of a loss of ground condition at the device undefined impedance looking from these pins to ground. In
level is that all pins of the IC (excluding transmitter outputs) will this condition, the CAN bus must not sink enough current to
see very low impedance to VBAT. The loss of ground is shown corrupt the bus. Refer to Figure 12.

GoDEVICE
DATA 23
33394 Inc.
Battery ICANH ICANH
16 V Battery
VBAT CANH VBAT CANH
VIGN ICANL VIGN ICANL

51 W 51 W
CANL CANL
POWER + POWER +
OAK –2V OAK +6V
– –
VDDH VDDH
68 W + 68 W +
VDD3_3 –2V VDD3_3 +6V
43 W –
43 W –
VDDL VDDL
43 W 43 W
GND GND
Figure 11. CAN Loss of Ground Test Circuit Figure 12. CAN Loss of Battery Test Circuit

33394 Inc.
5. APPLICATION INFORMATION
This section provides information on external components reasonable for most of practical applications. Then the ESR
that are required by the 33394. The IC is designed to operate of the output capacitor has to satisfy the following condition:
v DDVIoo
in an automotive environment. Conducted immunity and
radiated emissions requirements have been addressed ESR
during the design. However, the IC requires some external
protection. Where:
Protection is required for all pins connected directly to
battery. The module designer should use an MOV or another ∆Vo is the maximum allowed linear regulator voltage drop
transient voltage suppressor in all cases, when the load caused by the load current transient.
dump transition exceeds + 45 volts with respect to ground. ∆Io is the maximum current transient, which can occur due to
Protection should also include a reverse battery protection the abrupt step in the linear regulator load current.
diode (or relay) and input filter. This is required to protect the
In this example the VDDH output with the 400 mA load step
33394 from ESD and +/– 300V ignition transients. Typical
is considered with the maximum voltage drop of 100mV. This
configurations are shown in Figure 1. Outputs and inputs
gives the output capacitor’s maximum ESR value of:
connected directly to connector pins require module level
ESD protection. ESR + 100 mV + 250 mW
400 mA
5.1. Selecting Components for Linear Regulators This level of ESR requires a relatively large capacitance. In
The output capacitor of the linear regulator serves two order to maintain the linear regulator stability and to satisfy
different purposes. It maintains the linear regulator loop large load current steps requirements the solid tantalum
stability, and it provides an energy reservoir to supply current capacitor 100µF/10V with ESR = 200 mΩ. One device that
during very fast load transients. This is especially true when meets these requirements is the TPSC107K010S020
supplying highly modulated loads like microcontrollers and tantalum capacitor from the AVX Corporation.
other high–speed digital circuits. Due to the limited DVESR + ESR DIo + 200 mW 400 mA + 80 mV
bandwidth of the linear regulators, the output capacitor is
selected to limit the ripple voltage caused by these abrupt In the next step, the voltage drop associated with the
changes in the load current. During the fast load current capacitance can be calculated:
DVC + DIo C Dt + 0.4100

A 5 ms
mF + 20
transients, the linear regulator output capacitor alone
controls the initial output voltage deviation. Hence, the output mV
capacitor’s equivalent series resistance (ESR) is the most
critical parameter. Where:
The outputs, which do not experience such severe
C is the output capacitance.
conditions (the VREF e.g.), use the output capacitor mainly
for stability purpose, and therefore its capacitance value can Dt is the linear regulator response time.
be significantly smaller. The typical output capacitor
∆Io is the maximum current transient, which can occur due to
parameters are: C = 1.0 µF; ESR = 2.0 ohms. When a
the abrupt step in the linear regulator load current.
ceramic 1 µF capacitor is used, the ESR can be provided by
a discrete serial resistor (see Figure 20). Assuming that the capacitor ESL is negligible, the total
The following example shows how to determine the output voltage drop in the voltage regulator output caused by the
capacitance for a heavily loaded output supplying digital current fast transient can be calculated as:
circuits. DVtotal + DVESR ) DVC + 80 mV ) 20 mV + 100 mV
5.1.1. Selecting the Output Capacitor Example: A ceramic capacitor with capacitance value 10nF should
The output capacitance must be selected to provide be placed in parallel to provide filtering for the high frequency
sufficiently low ESR. The selected capacitor must have an transients caused by the switching regulator.
adequate voltage, temperature and ripple current rating for Properly sized decoupling ceramic capacitor close to the
the particular application. microprocessor supply pin should be used as well. Table 1
In order to calculate the proper output capacitor shows the suggested output capacitors for the 33394 IC
parameters, several assumptions will be made. linear regulator outputs.
1) During the very fast load current transients, the linear Other factors to consider when selecting output capacitors
regulator can not supply the required current fast enough, include key off timing for memory retention. Though the
and therefore for a certain time the entire load current is VKAM is not a heavily loaded output, the VKAM output
supplied by the output capacitor. 2) The capacitor’s capacitor has to have a sufficiently large capacitance value to
equivalent series inductance (ESL) is neglected. These supply current to the microcontroller for a certain time after
assumptions can greatly simplify the calculations, and are battery voltage is disconnected.

GoDEVICE
DATA 25
33394 Inc.
Table 1. Linear Regulator Output Capacitor Examples
Output SMD tantalum
Value/Rating Part n. (AVX Corp.)
VDDH 100uF/10V TPSC107K010S0200
VPP 33uF/10V TPSB336K010S0650
VDD3_3 68uF/6.3V TPSC686K006S0200
VDDL 100uF/6.3V TPSC107K006S0150
VREFx 10uF/16V THJB106K016S
VKAM* 100uF/6.3V TPSC107K006S0150
5.2. Switching Regulator Operation inductor input voltage is clamped one forward diode drop
The 33394 switching regulator circuit consists of two basic below ground. The inductor current during the off time is:
+ (Vo * Vfwd
switching converter topologies. One is the typical voltage ) toff
mode PWM step–down or buck regulator, which provides iL(off)
L
pre–regulated VPRE voltage (+5.6 V) during normal
operating conditions. Where:
During cold start–up, when the car battery is weak, the
toff is the off–time of the power switch.

input voltage for the 33394 can fall below the lower operating
limit of the step–down converter. Under such conditions, the iL(off) is the inductor current during the off time.
step–up or boost converter provides the required value of the
VPRE voltage. The following paragraphs describe the basic Vfwrd is forward voltage drop across the rectifier.
principles of the two converters operation. During the steady state operation iL(on) = iL(off) = ∆IL, and
Buck Mode Vin/Vo = d

One switching cycle of the step–down converter operation Where:
has two distinct parts: the power switch on state and the off
state. When the power switch is on, one inductor terminal is d is the duty cycle, and d = ton/T.
connected to the input voltage Vin, and the other inductor
T is switching period, T = 1/f.
terminal is the output voltage Vo. During this part of the
switching period the rectifier (catch diode) is back biased, f is the frequency of operation.
and the current ramps up through the inductor to the output: Two relations give the ripple voltage in the output capacitor
iL(on) + (Vin * Vo) ton Co. The first describes ripple voltage caused by current
L variation upon the output capacitance Co:
Where: VppCo + 8CoDIL

f
ton is the on–time of the power switch. The other is caused by current variations over the output
capacitor equivalent series resistance ESR:
Vin is the input voltage.
Vo is the output voltage. VppESR +
DIL RESR
iL(on) is the inductor current during the on–time. Practically, the ESR contributes predominantly to the buck
converter ripple voltage:
L is the inductance of the inductor L. VppESR >>VppCo
During the on time, current ramping through the inductor The inductor peak current can be calculated as follows:
stores energy in the inductor core.
During the off time of the power switch, the input voltage IpkL + Io ) 12 DIL
source Vin is disconnected from the circuit. The energy
stored in the core forces current to continue to flow in the Where:
same direction, the rectifier is forward biased and the
Io is the average output current.

33394 Inc.
DIL
IQ IL
+
IL IO
Q L
+
ID VO RLOAD
D CO
Vin
– IQ
L ILO +
–ID
+ ILOAD
RLOAD
CO
Vin Vout
–
POWER SWITCH ON VD
Vfwd
ILO +
+ ILOAD
RLOAD
CO VCo
VD(fwd) Vout
– ton toff
POWER SWITCH OFF t
T
Figure 13. Basic Buck Converter Operation and its Waveforms
Boost Mode
The operation of the boost converter also consists of two iL(off) + (Vo * VLin) toff
parts, when the power switch is on and off. When the power
switch turns on, the input voltage source is placed directly Where:
across the inductor, and the current ramps up linearly toff is the off–time of the power switch.
through the inductor as described by:
Vo is the output voltage.
iL(on) + Vin L ton During the steady state operation iL(on) = iL(off) = ∆IL, and
Where:
ton is the on–time of the power switch.
d + Vo V*oVin
Vin is the input voltage. Where:
iL(on) is the inductor current during the on–time. d is the duty cycle, and d = ton/T.
L is the inductance of the inductor L. T is switching period, T = 1/f.
The current ramping across the inductor stores energy f is the frequency of operation.
within the core material. In order to maintain steady–state
The ripple voltage of the boost converter can be described
operation, the amount of energy stored during each switching
as:
cycle, times the frequency of operation must be higher (to
cover the losses) than the power demands of the load:
VppCo + CIoo (Vo * Vin)
Psto + 12 LI pk f u Pout
2
Vo f
Where:
When the power switch turns off again, the inductor voltage
flies back above the input voltage and is clamped by the VppCo is the ripple caused by output current.
forward biased rectifier at the output voltage. The portion of the output ripple voltage caused by the ESR
The current ramps down through the inductor to the output of the output capacitor is:
until the new on time begins or, in case of discontinuous
mode of operation, until the energy stored in the inductor core
drops to zero.
VppESR + (Io Vo
Vin
) 12 DIL) RESR

GoDEVICE
DATA 27
33394 Inc.
Where Io is the average output current.
The inductor peak current is given by the following
IpkL + Io Vo
Vin
) 12 DIL
equation:
DIL
IL ID
+
IL
L D
+
VO RLOAD
Q IQ
CO
Vin
– ID
IO
+
IQ
+ ILOAD
L RLOAD
ION
CO
Vin Vout
–
POWER SWITCH ON
VQ
IL +
IOFF + ILOAD
RLOAD
CO VCo
VIN Vout
– ton toff t
POWER SWITCH OFF
T
Figure 14. Basic Boost Converter Operation and its Waveforms
5.2.1. Switching Regulator Component Selection 5.6 V and the linear regulators require a minimum of 0.4 V
The selection of the external inductor L2 and capacitor C2 dropout voltage. This leaves a ±0.2 V window for the
values (see Figure 15) is a compromise between the two peak—to–peak output voltage ripple. Assuming the following
modes of operation of the switching regulator, the pre conditions:
regulated voltage VPRE and the dropout voltage of the linear Vin(typ) = 13.5 V
regulators. Ideal equations describing the peak—peak
inductor current ripple, peak—peak output voltage ripple and Io = 1.2
peak inductor current are shown below. Since the switching VPRE = 5.6 V (+6 V in the boost mode)
regulator will work mostly in the buck mode, the inductor and
the switcher input and output capacitor were selected for f = 200 kHz
optimum buck controller performance, but also taking into Vfwd1 = Vfwd2 = 0.5 V
account the restriction placed by adopting the boost
converter as well. Maximum allowed output voltage ripple in the buck mode
Vpp(max) = 0.2 V/2 = 0.1 V (to allow for process and
temperature variations).
IQ VRDS(on) VRL IL Vfwd2
+
5.2.1.1. Selecting the Inductor
Q1 RDS(on) RL L D2 In order to select the proper inductance value, the inductor
RLOAD
ESR ripple current ∆IL has to be determined. The usual ratio of ∆IL
D1 Vfwd1 VO to output current Io is:
Q2 +
Vin ∆IL = 0.3 Io
CO
As described in the previous section, and taking into
account the 33394 switcher topology (see Figure 15), the
–
inductor ripple current can be estimated as:
Figure 15. 33394 Switcher Topology
The following example shows a procedure for determining DIL +
(Vin * Vo * Vfwd2) )
Vo Vfwd2
L Vin f
the component values. The VPRE output is set to regulate to

33394 Inc.
After substitution, the calculated inductance value is L = 45 VppESR = ∆IL x RESR = 0.345 x 0.08 = 28 [mV]
µH, which gives 47 µH standard component value. One device that meets both, the low ESR, and the
The peak–to peak ripple current value is: ∆IL = 0.345 A. temperature stability requirements is, for example, the
TPSV107K020R0085 tantalum capacitor from AVX Corp.
The peak inductor current is given by:
ILpk = 0.5∆IL + Io = 0.5x0.345 + 1.2 = 1.37[A] Boost Converter Power Capability
The boost converter with selected components has to be
The inductor saturation current is given by the upper value
able to deliver the required power.
of the 33394 internal switch current limit Ilim(max) = 3.0 A.
Due to the nature of this non–compensated PFM control
Considering also the inductor serial resistance, these
technique, the Boost converter output ripple voltage is higher
requirements are met, for example by the PO250.473T
than if it utilized a typical PWM control method. Therefore the
inductor from Pulse Engineering, Inc.
switcher output voltage level is set higher than in the Buck
5.2.1.2. Selecting the Catch Diode D1 mode (in the Boost mode VPRE = +6 V), in order to maintain
The rectifier D1 current capability has to be greater than a sufficient dropout voltage for the 5–volt linear regulators
calculated average current value. (VDDH, VREFs) and to avoid unwanted Resets to the
The maximum reverse voltage stress placed upon this microcontroller.
rectifier D1 is given by maximum input voltage (maximum The most stringent conditions for the 33394 boost
transient battery voltage). These requirements are met, for converter occur with the lowest input voltage:
example by the HSM350 (3 A, 50 V) schottky diode from Vin(min) = 3.5 V

Microsemi, Inc.
Io = 0.8 A
5.2.1.3. Selecting the Output Capacitor Vpre = +6 V
The output capacitor Co should be a low ESR part,
therefore the 100 µF tantalum capacitor with 80 mΩ ESR was f = 200 kHz
chosen. Vfwd1 = Vfwd2 = 0.5 V
From the formula for calculating the ripple voltage:
d = 0.75, duty cycle is fixed at 75% in boost mode
VRES IL Vfwd2 IL
+
ILIM
RD L D2 I01
IL1
I02
ESR
IQ VO RLOAD IL2
Q2 + L1 > L2
Vin
CO DIL1 < DIL2
IO1 > IO2
– T t
Figure 16. 33394 Switcher Topology – Boost Mode

The input voltage drop associated with the resistance of Then the maximum average input current can be
the internal switch Q1 and inductor series resistance can be calculated as:
estimated as:
IinAve + Ipk(min) * 12 DIL + 2.5 * 0.125 + 2.43[A]
VD [ Ipk(min) RD + 2.5 A 0.35 W + 0.875 V
2
Finally, the boost converter power capability has to be
Where: higher than the required output power or:
VD is the voltage dissipated on the major parasitic Pin(max) h u Pout
resistances, RDSon of the internal power switch and inductor
series resistance RL. Where Pin(max) is the boost converter maximum input power:
For the worst case conditions: h is the boost converter efficiency, in our case h is
estimated to be h = 85%, and includes switching losses of the
RD = RDSon(max) + RL = 0.25 + 0.1 = 0.35[Ω]
external power switch Q2 (MOSFET) inductor and capacitors
Ipk(min) is the minimum internal power switch current limit AC losses, and output rectifier D2 (schottky) switching
value. losses.
Then the equation for calculating ∆IL can be modified as Pout is the boost converter output power, which includes
power loss of the output rectifier D2:
+ (Vo ) Vfwd2) Io + (6 ) 0.5) 0.8 + 5.2[W]
follows:
DIL + Vin * VD [(Vo ) Vfwd2) * (Vin * VD)] d + Pout

L (Vo ) Vfwd2) f Pin + (Vin * VD) IinAve h +
* 0.875 [(6 ) 0.5) * (3.5 * 0.875)] 0.75
+ 3.5
47 10 * 6 (6 ) 0.5) 0.2 10 6
+ (3.5 * 0.875) 2.43 0.85 + 5.42[W]
As can be seen, the boost converter input power capability
+ 125[mA] meets the required criteria.

GoDEVICE
DATA 29
33394 Inc.
5.2.1.4. Selecting the Power MOSFET Q2 5.2.2. Input Filter Selection
The boost converter maximum output voltage plus the Since the switcher will work in the Boost mode only during
voltage drop across the output schottky rectifier D2 gives the cold crank condition, the 33394 EMC (electromagnetic
MOSFET’s maximum drain–source voltage stress: compatibility) performance is not of concern during this mode
BVdsQ2>Vo+Vfwd2 = 6 V+0.5 V, as can be seen, the of operation. Therefore, only the Buck mode of operation is
breakdown voltage parameter is not critical. important for selecting the appropriate input filter. For the
The more important in our case is the Q2 current handling Buck converter topology (see Figure 13) the low impedance
capability. The external power MOSFET has to withstand 3rd order filter (C3, L2, C4 and C26 in the Application
higher currents than the upper current limit of the 33394: Schematic Diagram Figure 20) offers a good solution. It can
IDQ2>3A be seen from the Buck converter current waveforms that
comparatively high current pulses are drawn from the
In order to keep the power dissipation of the 33394 boost
converter’s input source. The filter inductance must be kept
converter to its minimum, a very low RDSon power MOSFET
minimal and the capacitor, which is placed right next to the
has to be selected. Moreover, due to the fact that the 33394
power switch, must be sized large enough to provide
external MOSFET gate driver is supplied from VPRE, in
sufficient energy reservoir for proper switcher operation.
order to assure proper switching of Q2 a logic level device
The ESR of this input capacitor combination C4, C26 has
has to be selected.
to be sufficiently low to reduce the switching ripple of the
Last but not least, the Q2 package has to suitable for the
switcher input node VBAT. There are three main reasons to
harsh automotive environment with low thermal resistance.
keep the voltage ripple of the VBAT pin at its minimum. First,
These requirements are met, for example by the

it is the EMC (electromagnetic compatibility) performance of
MTD20N03HDL power MOSFET from ON Semiconductor.
the switcher in the normal operating mode (buck mode).
Second, it allows a smooth transition between the boost and
5.2.1.5. Selecting the Boost Converter Output
buck mode of operation. Third, it helps to avoid entering an
Rectifier D2 undervoltage condition too early. A practical way to achieve
Criteria similar to that of selecting the power MOSFET was
sufficiently low ESR of the switcher input capacitor, even at
used to select the boost converter output rectifier. Its reverse
low temperature extremes, is to use several high value
breakdown voltage is not a critical parameter:
ceramic capacitors in parallel with a large electrolytic
VrD2>Vo=6 V capacitor. These capacitors should be physically placed as
The D2 rectifier has to withstand higher peak current than close to the VBAT pins as possible.
is the 33394 internal switch upper current limit Ilim(max).
The most important parameter is its forward voltage drop, 5.2.3. Buck Converter Feedback Compensation
which has to be minimal. This parameter is also crucial for the A typical control loop of the buck regulator is shown in
proper 33394 switcher functionality, and especially for proper Figure 17. The loop consists of a power processing block —
transition between the buck and boost modes. the modulator in series with an error–detecting block — the
Finally, its switching speed, forward and reverse recovery Error (Feedback) Amplifier. In principle, a portion of the
parameters play a significant role when selecting the output output voltage (VPRE of the 33394 switcher) is compared to
rectifier D2. a reference voltage (Vbg) in the Error Amplifier and the
These requirements are met, for example by the HSM350 difference is amplified and inverted and used as a control
schottky rectifier from Microsemi, Inc. input for the modulator to keep the controlled variable (output
voltage VPRE) constant.
Vin Vout
Gain Block
PWM
+ To Load
(Modulator) Ramp Signal
Vin
+
S G Vout –
– +
MODULATOR
H
Zf
Feedback
Block – Zin
+
Vout/Vin = G/(1 + GH)
Reference
Voltage
ERROR FEEDBACK AMPLIFIER
Figure 17. The Buck Converter Control Loop

33394 Inc.
R2 C2 80
CLOSED LOOP (overall)
60
R3 C3
fp(LC)
C1 40 ERROR
VPRE_S R1 AMPLIFIER fp2
fp1
– E/A VCOMP
GAIN (dB)
+ 20
R A2
MODULATOR fZ1 A1 fZ2
Ref U1 0
Ifxo
–20
Figure 18. Error Amplifier Two–Pole–Two–Zero
Compensation Network –40 fZ(ESR)
The process of determining the right compensation
–60
components starts with analysis of the open loop (modulator) 1 10 100 1000 10 k 100 k 1M
transfer function, which has to be determined and plotted into
f (Hz)
the Bode plot (see Figure 19). The modulator DC gain can be
determined as follows: 90
ADC + DVVine MODULATOR

0
Where Ve is the maximum change of the Error Amplifier
PHASE (deg)
voltage to change the duty cycle from 0 to 100 percent (Ve = –90
2.6 V at Vbat =14 V).
As can be seen from Figure 19, the buck converter ERROR AMPLIFIER
modulator transfer function has a double complex pole –180
caused by the output L–C filter. Its corner frequency can be
calculated as:
–270
fp(LC) + 2p Ǹ1LC
o CLOSED LOOP (overall)
–360
This double pole exhibits a —40dB per decade rolloff and 1 10 100 1000 10 k 100 k 1M
a —180 degree phase shift.
f (Hz)
Another point of interest in the modulator’s transfer
function is the zero caused by the ESR of the output Figure 19. Bode Plot of the Buck Regulator
capacitor Co and the capacitance of the output capacitor The frequency of the compensating poles and zeros can
itself: be calculated from the following expressions:
fz(ESR) + 2pRESR
1
Co
+ 2pR12C2
fz1
fz2 + [ 2pR11C3
The ESR zero causes +20dB per decade gain increase,
2p(R1 ) R3)C3
1
and +90 degree phase shift.
Once the open loop transfer function is determined, the
appropriate compensation can be applied in order to obtain fp1 + 1
the required closed loop cross over frequency and phase 2pR3C3
C ) C2
fp2 + 1 [ 1
margin (~60 degree) — refer to Figure 18 and Figure 19.
Figure 19 shows the 33394 Switching Regulator modulator 2pR2C1C2 2pR2C1
gain–phase plot, E/A gain–phase plot, closed loop
gain–phase plot, and the E/A compensation circuit. The and the required absolute gain is:
+ RR21
frequency fxo is the required cross–over frequency of the
buck regulator. A1
In order to achieve the best performance (the highest
bandwidth) and stability of the voltage–mode controlled buck
PWM regulator the two–pole–two–zero type of compensation R1R3
A2 + R2(R1 ) R3) [ R2
R3
was selected — see Figure 19 for the compensated Error
Refer to Application Schematic Diagram (Figure 20) and
Amplifier Bode plot, and Figure 18 for the compensation
Table 2 for the 33394 switcher component values.
network. The two compensating zeros and their positive
phase shift (2 x +90 degree) associated with this type of
compensation can counteract the negative phase shift
caused by the double pole of the modulator’s output filter.

GoDEVICE
DATA 31
33394 Inc.
Table 2. Where R is the HRT timer pull–up resistor,
Part number Application diagram Component value C is the HRT timer capacitor
(Figure 18) part number (Figure 1) VB is the pull–up voltage,
Vth is the HRT timer threshold voltage (Vth = 2.5V
R1 33394 internal resistor 39.6kΩ
nominal value),
R2 R2 100kΩ VSAT is the saturation voltage of the internal pull–down
R3 R1 430Ω transistor.
C1 C6 100pF If the HRT timer pull–up resistor is connected to VDDH
C2 C7 1.0nF W
(see Figure 1) and the resistor value is ≥ 47 k , therefore the
C3 C5 3.3nF VSAT can be neglected, the formula for calculating the time
delay can be simplified to:
5.3. Selecting Pull–Up Resistors
All the Resets (/PORESET, /PRERESET and /HRESET) tD + 0.7 RC
are open drain outputs, which can sink a maximum of 1 mA
drain current. This determines the pull–up resistor minimum 5.5. Selecting the VKAM Resistor Divider
value. VKAM should be used as the pull–up source for the The VKAM linear regulator output voltage is divided by an
/PORESET output. /PORESET is pulled low only during external resistor divider and compared with the bandgap
initial battery connect or when VKAM is below 2.5 volts (for reference voltage (Vbg) in the input of the VKAM error
amplifier. The resistor divider can be designed according to
ǒ) Ǔ
VDDL = 2.6 V).
To select the /PRERESET and /HRESET pull–up resistor the following formula:
+ VKAMref
connections, consider current draw during sleep modes. For Rupper
example, the pull up resistor on /PRERESET and /HRESET VKAM 1
Rlower
should receive its source from VDDL, if the sleep mode or low
power mode of the module is initiated primarily by the state of VKAMref = 1.267 V
the VIGN pin. Refer to Figure 20 for recommended pull–up
Where VKAMref is the bandgap reference voltage.
resistor values.
Another way to connect the /PRERESET and /HRESET Since the VKAM feedback pin (VKAM_FB) input current is
pull–up resistors is to connect them to the VKAM output only a few nA, the resistor value can be selected sufficiently
together with the /PORESET pull–up resistor (see Figure 1). high in order to minimize the quiescent current of the module.
This is the preferable solution when the sleep or low power See Figure 20 for the VKAM resistor divider recommended
mode is initiated primarily by the microprocessor. In that values.
case, when the 33394 is shut down by pulling the /SLEEP pin
down, all three Resets (/PORESET, /PRERESET and 5.6. Selecting the VDDL Resistor Divider
/HRESET) stay high. Since they are pulled–up to the supply The VDDL regulator resistor divider is designed according
to the same formula as described in the paragraph above
ǒ) Ǔ
voltage (VKAM) they draw no current from the VKAM and the
module quiescent current is minimized. (see Figure 20).
5.4. Selecting Hardware Reset Timer Components VDDL + VDDLref 1

Rupper
Rlower
The HRT input sets the delay time from VDDH, VDD3_3
and VDDL stable to the release of /PRERESET and Where VDDLref = 1.267 V
/HRESET. When sizing the delay time the module design Nonetheless, the actual resistor values should be chosen
engineer must consider capacitor leakage, printed board several decades lower than in the previous example. This is
leakage and HRT pin leakage. Resistor selection should be due to the fact that the VDDL linear regulator needs to be
low enough to make the leakage currents negligible. The pre–loaded by a minimum of 10 mA current in order to
Hardware Reset (/HRESET) delay can be calculated as guarantee stable operation. See Figure 20 for the VDDL
follows: resistor divider recommended values.
Delay time:
+ * RC *
(VB VSAT) Vth *
tD ln[
*
(VB VSAT)
]

33394 Inc.
D2 * L2 L1 D1
JP1 MURS320T3 Q3 6.8uH 47uH 20BQ030
+Battery 1 2 Vbat 1 2
1
2 VDDH +
C3 C4 + C2
1.0uF/50V 100uF/35V D3
SS25 C5 100uF/16V
SW1 Q1 3.3nF
DIP–2 R13 MMSF3300R2
18R
R1
C29 430R
VPP_EN R14 1.0uF/50V
4.7k C1
IGN VIGN U1 100nF
1.0uF/50V
R3 C28 C26 28 27 C6 C7
BOOT
4.7k VKAM VBAT SW1 100pF
29 26 1.0nF
10nF 30 VBAT SW1 25
R4 31 VBAT SW1 24
22k VBAT SW1 R22
32 VBAT SW1 23
+ 33 22 100k
C23 34 KA_VBAT N/C
N/C 21
10nF C24 35 BOOT 20 VPRE
22uF R6 36 VIGN SW2G
VKAM 19
20k 37 GND 18 C30
VSEN 38 VKAM_FB INV 17 VDDH
MC33394DWB
REGON 39 VSEN VCOMP 10nF
REGON 16
WAKEUP 40 VPRE VPRE_S +
VPRE_S 15
VREF1 41 WAKEUP C10
VREF1 14 C11
VPP_EN 42 VDDH 47uF
VPP_EN VREF2 13 10nF
C8 43 12
10nF C9 44 VPP VREF3
VDD3_3 N/C 11
1.0uF 45 10 37
VDDL_X 46 VDD3_3FB DO 9 36 VREF2
R19 VDDL_B 47 VDDL_X SCLK 35
8
2.0R VDDL_FB 48 VDDL_B DI 34 C14
VDDL_FB CS 7 C15
49 6 1.0uF 10nF
50 N/C N/C /SLEEP

5
51 /PRERESET /SLEEP R20
/HRESET HRT 4
52 3 2.0R
CANRXD /PORESET CANH
53 2
VPP CANTXD CANRXD CANL
54 CANTXD 1
GND
CANH
CANL
+
C12 C13 VREF3
10nF 10uF
R15 C16
/PORESET
C17
/PRERESET
/HRESET
R8 47k 1.0uF 10nF
+3.3V 120R VDDH
C21 + C18 R21
10nF C22 1.0uF 2.0R
10uF C25 * C27 *
37 R9 4.7k DO R16 R17 R18
10k 10k 10k
36 R10 4.7k SCLK
35 R11 4.7k DI
VKAM
34 R12 4.7k CS Q3
VPRE
Q2 VDDL_B Q3
MJD31C MJD31C VDDL_X
VDDL = 2.6V
VDDL
/PRERESET
/PORESET
/HRESET
WAKEUP
CANRXD
CANTXD
VPP_EN
+Battery
+Battery
+Battery
+Battery
REGON
/SLEEP
VREF2
VREF1
VREF3
VKAM
CANH
VDDH
VSEN
R5
CANL
VDDL
+3.3V
SCLK
GND
GND
GND
GND
GND
VPP
IGN
DO
110R
CS
+
DI
C15 VDDL_FB
10nF C20
J1 47uF R7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 20. 33394 Application Circuit Schematic Diagram
Table 3. 33394 Evaluation Board Performance

Value Line Regulation Load Regulation
Parameter (TA = 25_C, Vin = 14V) (Vin = 5.2V to 26.5V) (Vin = 14 V)
V Load DV Load DV Load
[mV] [mA] [mV] [mA] [mV] [mA]
VDDH 5.028 400 10 400 18 0 to 400
VPP 5.026 150 10 150 5 0 to 150
VREF1 5.023 100 8 100 8 0 to 100
VREF2 5.022 100 8 100 10 0 to 100
VREF3 5.021 100 6 100 11 0 to 100
VDD3_3 3.307 120 5 120 7 0 to 120
VDDL 2.667 400 5 400 10 0 to 400
VKAM 2.638 60 2 60 14 0 to 60

GoDEVICE
DATA 33
33394 Inc.
Table 4. 33394DWB Evaluation Board Bill of Material
Item Qty. Part Designator Value/ Rating Part Number/ Manufacturer
1 1 C1 100nF/16V, Ceramic X7R Any manufacturer
2 1 C2 100µF/20V TPSV107K020R0085, AVX Corp.
3 3 C3,C26,C29 1.0µF/50V C1812C105K5RACTR, Kemet
4 1 C4 100µF/35V UUB1V101MNR1GS, Nichicon
5 1 C5 3.3nF, Ceramic X7R Any manufacturer
6 1 C6 100pF, Ceramic X7R Any manufacturer
8 10 C8,C11,C12,C15,C17,C19,C21,C23,C28,C30 10nF, Ceramic X7R Any manufacturer
9 4 C9,C14,C16,C18 1.0µF, Ceramic X7R Any manufacturer
10 2 C20,C10 47µF/10V, Tantalum TPSC476K010R0350, AVX Corp.
11 1 C13 10µF/16V, Tantalum TPSB106K016R0800, AVX Corp.
12 1 C22 10µF/6.3V, Tantalum TPSA106K006R1500, AVX Corp.

14 2 C25,C27 470pF, Ceramic X7R Any manufacturer
15 1 D1 30V/2A Schottky 20BQ030, International Rectifier
16 1 D2 200V/3A Diode MURS320T3, ON Semiconductor
17 1 D3 50V/2A Schottky SS25, General Semiconductor
18 1 JP1 2–pin, 0.2 (5.1mm) Terminal Block
19 1 J1 34–pin, 0.1 x 0.1 PCB Header Connector
20 1 L1 47µH P0250.473T, Pulse Engineering
21 1 L2 6.8µH P0751.682T, Pulse Engineering
22 1 Q1 30V/11.5A, Mosfet MMSF3300R2, ON Semiconductor
23 2 Q2,Q3 100V/3A, BJT MJD31C, ON Semiconductor
24 1 R1 430R, Resistor 0805 Any manufacturer
25 1 R2 100k, Resistor 0805 Any manufacturer
26 6 R3,R9,R10,R11,R12,R14 4.7k, Resistor 0805 Any manufacturer
27 1 R4 22k, Resistor 0805, 1% Any manufacturer
28 1 R5 110R, Resistor 0805, 1% Any manufacturer
34 3 R16,R17,R18 10k, Resistor 0805 Any manufacturer
35 3 R19,R20,R21 2.0R, Resistor 0805 Any manufacturer
36 1 SW1 2–Position DIP Switch BD02, C&K Components
37 1 TP1 Test Point, 0.038 240–333, Farnell
38 1 U1 Integrated Circuit 33394DWB/ Motorola

33394 Inc.
OPTIONAL
Q4 OUTPUT
* D1 FILTER
JP1 D2 L2 VPRE_S
+BATTERY 1 2 VBAT L1 20BQ030 L3
1
6.8 Hm + 1 2 1 2
m
2 VDDH
m MURS320T3
m
100 F/ C4 1.0 F/ C26 m 47 H + +
m
1.0 F/ C5
50 V 1.0 F/50 V C3 50 V D3 3.3 nF C2 C30
SW1
DIP–2
C29 35 V
SS25 Q1
MTD20N03HDL m
100 F/ m
33 F/16 V
C1 20 V
VPP_EN
R14 100 nF R13
VIGN R1
2.6V VKAM 18R 430R
4.7k
R3 +
10
11
R4 U1
9
8
7
6
5
4
3
2
1
4.7 k C23 C24 22 k
m
GND
VKAM
VIGN
SW1
SW1
SW1
SW2G
BOOT
KA_VBAT
VBAT
VBAT
10 nF 100 F
C6 C7
C28 12 44 100 pF 1.0 nF
10 nF R6 VKAM_FB INV R2 100 k
20 k 13 VSEN VCOMP 43
14 42 VPRE
REGON VPRE
15 WAKEUP VPRE_S 41
5.0V @ 100mA VREF1 16 40 VDDH 5.0V @ 400 mA
VREF1 VDDH
C8
+ 17
18
VPP_EN PC33394FC
VPP
VREF2
VREF3
39
38 + C11
C9 C10
10 nF m
1.0 F
19
20
VDD3_3 DO 37
36 m
47 F 10 nF
VDD3_3FB SCLK
/PRERESET
21 VDDL_X DI 35
/PORESET
VDDL_FB
22 34
/HRESET
5.0V @ 150mA VPP
CANRXD
5.0V @ 100 mA
CANTXD
VDDL_B CS VREF2
/SLEEP
+ +
CANH
CANL
GND
HRT
C12 C13 C14 C15
10 nF 33 Fm m
1.0 F 10 nF
23
24
25
26
27
28
29
30
31
32
33
VPRE R15 VDDH
47 k
Q2
C18
m
MJD31C 120R
R19 R16 R17 R18 1.0 F
10R 10 k 10 k 10 k 5.0V @ 100 mA
+3.3V VKAM C25 * C27 *
VREF3
C21
+ R9 4.7 k DO
+ C17
C22 C16
10 nF 47 mF
37
R10 4.7 k SCLK
m
1.0 F 10 nF
36
R11 4.7 k DI VPRE Q4
35
R12 4.7 k CS
34 Q3 VDDL_B Q4 VDDL_X
MJD31C MJD31C
2.6V @ 400 mA
/PRERESET
+BATTERY
+BATTERY
+BATTERY
+BATTERY
/PDRESET
VDDL VDDL
/HRESET
WAKEUP
CANRXD
CANTXD
VPP_EN
+
REGON
/SLEEP
VREF2
VREF1
VREF3
VKAM
CANH
VDDH
VSEN
CANL
VDDL
+3.3V
SCLK
R5
GND
GND
GND
GND
GND
VPP
IGN
C19 C20
DO
110R
CS
m
DI
10 nF 100 F VDDL_FB
R7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
J1 100R
CON/34
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted.
Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Figure 21. 33394 Application Circuit with Increased 3.3V Output Current Capability

GoDEVICE
DATA 35
33394 Inc.
Table 5. 33394FC Evaluation Board Bill of Material
Item Qty. Part Designator Value/ Rating Part Number/ Manufacturer
1 1 C1 100nF/16V, Ceramic X7R Any manufacturer
2 1 C2 100µF/20V TPSV107K020R0085, AVX Corp.
3 3 C3,C26,C29 1.0µF/50V C1812C105K5RACTR, Kemet
4 1 C4 100µF/35V UUB1V101MNR1GS, Nichicon
6 1 C6 100pF, Ceramic X7R Any manufacturer
8 9 C8,C11,C12,C15,C17,C19,C21,C23,C28 10nF, Ceramic X7R Any manufacturer
9 1 C18 1.0µF, Ceramic X7R Any manufacturer
10 3 C9,C14,C16 1.0µF/35V Tantalum TPSA105K035R3000, AVX Corp.
11 2 C10,C22 47µF/10V Tantalum TPSC476K010R0350, AVX Corp.
12 1 C13 33µF/10V Tantalum TPSB336K010R0500, AVX Corp.
13 1 C20 100µF/6.3V Tantalum TPSC107K006R0150, AVX Corp.

15 2 C27,C25 470pF, Ceramic X7R Any manufacturer
16 1 C30 33µF/16V TPSC336K016R0300, AVX Corp.
17 1 D1 30V/ 2A Schottky 20BQ030, International Rectifier
18 1 D2 200V/3A Diode MURS320T3, ON Semiconductor
19 1 D3 SS25 SS25, General Semiconductor
20 1 JP1 2–pin, 0.2 (5.1mm) Terminal Block
21 1 J1 34–pin, 0.1 x 0.1 PCB Header Connector
22 1 L1 47µH P0250.473T, Pulse Engineering
23 1 L2 6.8µH P0751.682T, Pulse Engineering
24 1 L3 Ferrite Bead HF30ACC575032/ TDK
25 1 Q1 30V/20A Mosfet MTD20N03HDL, ON Semiconductor
26 3 Q2,Q3,Q4 100V/3A BJT MJD31C, ON Semiconductor
29 6 R3,R9,R10,R11,R12,R14 4.7k, Resistor 0805 Any manufacturer
37 3 R16,R17,R18 10k, Resistor 0805 Any manufacturer
39 1 SW1 2–Position DIP Switch BD02, C&K Components
40 1 TP1 Test Point 240–333, Farnell
41 1 U1 Integrated Circuit MC33394DWB/ Motorola

33394 Inc.
L1
47µF VPRE = 5.6V
Input voltage +7V to +26.5V 1 44
VBAT SW1
C1
ON S1 100µF + 2 43 +
VBAT SW1
Cb D1 C2
OFF 3 42 100nF MBRS340T 100µF
R5 KA_VBAT SW1
4.7k C5
10nF 4 41
VIGN BOOT BAV99
330nF
VKAM = 2.6V @ 60mA 5 40
VKAM SW2G Rf3
+ Cf3 Rf2
C6 C7 6 39 3.3nF 100k 430R
10nF VKAM_FB GND
47µF R2
22k 7 38 Cf1
R1 VSEN INV
20k 100pF Cf2
8 37
REGON VCOMP 1nF
9 36
WAKEUP VPRE
PC33394
VREF1 = 5V @ 100mA 10 35
VREF1 VPRE_S
+
C8 C9 11 34 VDDH = 5V @ 400mA
10nF 1.0µF VDDH VPP_EN VDDH
+
VPP = 5V @ 150mA 12 33 VREF2 = 5V @ 100mA C14 C15
VPP VREF2 100µF 10nF
+ +
C16 C17 3.3V @ 120mA 13 32 VREF3 = 5V @ 100mA C18 C19
47µF VDD3_3 VREF3 1.0µF 10nF

10nF + +
C10 C11 14 31 C20 C21
VDD3_3FB DO 10nF
10nF 47µF 1.0µF
VPRE 15 30
VDDL_X SCLK
Q1
MJD44H11 16 29
VDDL_B DI
VDDL = 2.6V @ 600mA 17 28
VDDL_FB CS
+ R4
C12 C13 22R /PRERESET 18 27
R3 /PRERESET /SLEEP Rt
10nF 100µF
20R /HRESET 19 26 47k
/HRESET HRT VDDH
/PORESET 20 25 Ct
/PORESET CANH 1.0 µF
R6 10k 60R
21 24
VKAM CANRXD CANL
R7 10k 22 23
CANTXD GND
R8 10k
Figure 22. 33394 Buck–Only Application

GoDEVICE
DATA 37
33394 Inc.
+12V @ 100mA
+
D3
+
C23 D3 C22
47µF 47µF
Input voltage +10V to +26.5V 1 44
VBAT SW1 –12V @ 100mA
C1
ON S1 100µF + 2 43 VPRE = 5.6V
VBAT SW1
T1
OFF R5 3 42 +
C5 KA_VBAT SW1
4.7k D1 C2
10nF Cb MBRS340T 100µF
4 41
VIGN BOOT 100nF
VKAM = 2.6V @ 60mA 5 40 Rf3
VKAM SW2G 430R
+
C6 C7 6 39
10nF VKAM_FB GND
47µF R2 Cf3 Rf2
22k 7 38 3.3nF 100k
R1 VSEN INV
20k 37
8
REGON VCOMP Cf1
100pF Cf2
9 36
WAKEUP VPRE 1nF
PC33394
VREF1 = 5V @ 100mA 10 35
VREF1 VPRE_S
+
C8 C9 11 34 VDDH = 5V @ 400mA
10nF 1.0µF VDDH VPP_EN VDDH
+
VPP = 5V @ 150mA 12 33 VREF2 = 5V @ 100mA C14 C15
VPP VREF2 100µF 10nF
+ +
C16 C17 3.3V @ 120mA 13 32 VREF3 = 5V @ 100mA C18 C19
47µF VDD3_3 VREF3 1.0µF 10nF
10nF + +
C10 C11 14 31 C20 C21
VDD3_3FB DO 10nF
10nF 47µF 1.0µF
VPRE 15 30
VDDL_X SCLK
Q1
MJD31C 16 29
VDDL_B DI
VDDL = 2.6V @ 400mA 17 28
VDDL_FB CS
+ R4
C12 C13 22R /PRERESET 18 27
R3 /PRERESET /SLEEP Rt
10nF 100µF
20R /HRESET 19 26 47k
/HRESET HRT VDDH
/PORESET 20 25 Ct
/PORESET CANH 1.0 µF
R6 10k 21 60R
VKAM CANRXD CANL 24
R7 10k 22 23
CANTXD GND
R8 10k
Figure 23. 33394 Flyback Converter Provides Symmetrical Voltages

33394 Inc.
PACKAGE DIMENSIONS
DH SUFFIX
44–LEAD HSOP
PLASTIC PACKAGE
CASE 1291–01
ISSUE O
PIN ONE ID
h X 45 _
E3 NOTES:
E2 1. CONTROLLING DIMENSION: MILLIMETER.
4X E5 2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
1 44
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
42X
e
D2
THE BOTTOM OF THE PARTING LINE.
D3
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
D1
4X
0.150 PER SIDE. DIMENSIONS D AND E1 DO
D INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
0.325
PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
22 23
CONDITION.
EXPOSED 6. DATUMS –A– AND –B– TO BE DETERMINED AT
HEATSINK AREA
DATUM PLANE –H–.
B E1 E4 7. DIMENSION D DOES NOT INCLUDE TIEBAR
22X A PROTRUSIONS. ALLOWABLE TIEBAR
E PROTRUSIONS ARE 0.150 PER SIDE.
BOTTOM VIEW
bbb M C B MILLIMETERS
DIM MIN MAX
ÇÇÇÇ
A 3.000 3.400
Y DATUM
H PLANE A1 0.025 0.125
ÉÉÉ
ÇÇÇÇ
b1 A2 2.900 3.100
A A2 D 15.800 16.000
D1 11.700 12.600
ÉÉÉ
ÇÇÇÇ
c c1 D2 0.900 1.100
D3 ––– 1.000
SEATING E 13.950 14.450
C PLANE b E1 10.900 11.100
E2 2.500 2.700
aaa M C A E3 6.400 7.300
E4 2.700 2.900
E5 ––– 1.000
GAUGE SECTION W–W L 0.840 1.100
PLANE L1 0.350 BSC
L1
W b 0.220 0.350
b1 0.220 0.320
c 0.230 0.320
W c1 0.230 0.280
bbb C L e 0.650 BSC
q
A1
h ––– 0.800
q 0_ 8_
(1.600) aaa 0.200
bbb 0.100
DETAIL Y

GoDEVICE
DATA 39
33394 Inc.
PACKAGE DIMENSIONS
FC SUFFIX
44–LEAD QFN
PLASTIC PACKAGE
CASE 1310–01
ISSUE D
PIN 1
INDEX AREA
0.1 C
A 9 2X M
0.1 C G 0.1 C
2X
1.0 1.00 0.05 C 5
0.8 0.75
9
(0.325)
0.05 (0.65)
0.00 C SEATING PLANE
DETAIL G
VIEW ROTATED 90 ° CLOCKWISE
M
B
0.1 C A B
6.85 DETAIL M
6.55 PIN 1 IDENTIFIER
34 44 EXPOSED DIE
ATTACH PAD
NOTES:
33 1 1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
6.85 PACKAGE IS: HF–PQFP–N.
6.55 4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
0.1 C A B REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER
0.65 40X LEADS AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES,
23 11 MAXIMUM DRAFT ANGLE IS 12°.
N
22 12
44X
0.75 0.37
0.50 44X
0.23
0.1 M C A B
VIEW M–M
0.05 M C
(45 ° )
(3.53)
0.60
0.24
0.065 0.60
44X 0.24
0.015 (0.25)
DETAIL N DETAIL N
PREFERRED CORNER CONFIGURATION CORNER CONFIGURATION OPTION
4 4
3.4
°
DETAIL T 3.3 BACKSIDE (90 )

PIN 1 INDEX
0.475
0.425
2X 0.39
0.31
R 0.25
0.15 2X
0.1
0.0
DETAIL M DETAIL M DETAIL T
PREFERRED BACKSIDE PIN 1 INDEX BACKSIDE PIN 1 INDEX OPTION PREFERRED BACKSIDE PIN 1 INDEX

33394 Inc.
PACKAGE DIMENSIONS
DWB SUFFIX
54–LEAD SOICW–EP
PLASTIC PACKAGE
CASE 1377–01
ISSUE B
10.3
5 9
7.6
C NOTES:
7.4 B 2.65
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.35 2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
52X 3. DATUMS B AND C TO BE DETERMINED AT THE
1 54 PLANE WHERE THE BOTTOM OF THE LEADS
0.65
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
PIN 1 INDEX NOT EXCEED 0.15 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
4 NOT EXCEED 0.25 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
18.0 CL WHERE THE BOTTOM OF THE LEADS EXIT THE
9 17.8 PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
B B WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD SHALL NOT LESS THAN
0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
27 28 9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
SEATING DETERMINED AT THE OUTERMOST EXTREMES
A PLANE OF THE PLASTIC BODY EXCLUSIVE OF MOLD
5.15
FLASH, TIE BAR BURRS, GATE BURRS AND
2X 27 TIPS 54X
INTER–LEAD FLASH, BUT INCLUDING ANY
0.3 A B C 0.10 A MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
A
R0.08 MIN 0 ° MIN
C C 0.25
GAUGE PLANE (1.43)
A
0.1
0.9
8° 0.5
0.0
0°
6.6 SECTION B–B
5.9
0.30 A B C
ÉÉÉÉ
ÇÇÇÇ
(0.29) BASE METAL
4.8
4.3
0.30
0.25 ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
(0.25)
0.38
0.30 A B C PLATING
6 0.22
0.13 M A B C 8
SECTION A–A
ROTATED 90_ CLOCKWISE
VIEW C–C

GoDEVICE
DATA 41
33394 Inc.
NOTES

33394 Inc.
NOTES

GoDEVICE
DATA 43
Freescale Semiconductor, Inc... Freescale Semiconductor,
33394 Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2001.

How to reach us:
USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334
Technical Information Center: 1–800–521–6274
HOME PAGE: http://www.motorola.com/semiconductors/

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Inc. this document from Analog Marketing

Switch Mode Power Supply with 33394

5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V

VBAT SW1 CS VDDL_FB

KA_VBAT SW1 DI VDDL_B

This document contains information on a new product. Specifications

 Motorola, Inc. 2002 For More Information On This Product,

For More Information On This Product,

For More Information On This Product,

13 VSEN Switched battery output

For More Information On This Product,

15 VPRE_S Switching pre–regulator output sense

For More Information On This Product,

CANTXD, CANRXD –0.3 +7.0 V

For More Information On This Product,

Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V IVBAT(13.3) 1.2 A

For More Information On This Product,

DC Open Loop Gain (Note 1) AVOL 80 dB

For More Information On This Product,

Thermal Shutdown Junction Temperature (Note 1) TSDIS 150 190 °C

For More Information On This Product,

For More Information On This Product,

VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V IstbVREF 40 mA

For More Information On This Product,

VKAM Reset Lower Threshold Voltage (Notes 2, 5) 1.2 V

For More Information On This Product,

High–Level Output Voltage VOH VDDH VDDH V

For More Information On This Product,

Figure 2. CAN Delay Timing Waveform

For More Information On This Product,

DI LSB IN DATA MSB IN

Figure 3. SPI Timing Diagram

For More Information On This Product,

For More Information On This Product,

Figure 4. Switching Regulator Block Diagram

For More Information On This Product,

For More Information On This Product,

For More Information On This Product,

Figure 5. 33394 Timing Diagram

0V POWER UP SEQUENCE POWER DOWN SEQUENCE

*NOTE: VDDL = 2.6 V for MPC565

Figure 6. 33394 Power Up/Down Sequence

For More Information On This Product,

33394 SPI Registers:

Figure 7. SPI Input Data/ Control Register

For More Information On This Product,

Bit 3 — VSEN–I: – Will be set (1), if a current limit condition exists

Figure 8. SPI Output Data/ Status Register

Common Mode Choke

Figure 9. CAN Load Characteristics

For More Information On This Product,

Figure 10. CAN Transceiver Block Diagram

For More Information On This Product,

VIGN ICANL VIGN ICANL

For More Information On This Product,

DVC + DIo C Dt + 0.4100

For More Information On This Product,