Report on Hands-on workshop “RTL Verification using

System Verilog Part-I”

By
ChipEdge

At
Department of Electronics and Communication
Engineering
P.E.S. College of Engineering, Mandya.

Technical Expertise:

Expertise Names Company Name

1. Bhanu Marcharla
2. Rajesh G ChipEdge

Teaching Hours: 36 Hours

Academic year: 2023-2024
Date: 06/05/2024 to 11/05/2024
Semester: 6th Semester
Total students attended session: 82
ChipEdge Training Session on RTL Verification using System Verilog part-I

CHAPTER 1

Introduction:

Hands-on workshop training session on “RTL Verification using System Verilog part-I”
conducted for the 6th semester students of Electronics and Communication Engineering in the
academic year 2023-2024.

The Department of Electronics and Communication at P.E.S College of Engineering, Mandya

successfully organized a comprehensive 5-days hands-on training program on “RTL
Verification using System Verilog part-I” under the support and supervision of Head of the
Department Dr. Punith Kumar M. B and under the guidance of department skill development
co-ordinator M. Subramanyam. The overview and exposure related to academics towards the
session was given by Dr. Mahesh Koti. The faculty co-ordinator Yashwanth. B facilitated the
complete session along with faculties Minugu B, Dimple R and Anisha A.
The following are the expertise from the company ChipEdge

Trainer’s Name Company Experience Session hour’s

conducted
Bhanu Marcharla 10+ years
Rajesh G ChipEdge 6+ years 24

The session was conducted by industry experts from Skill Lync, namely Bhanu Marcharla,
from ChipEdge, brings over a decade of rich experience in the field, having conducted 24
hours of sessions spanned for 6 days. Alongside, Rajesh G, with more than 6 years of
expertise, further enriches the training program. Their extensive experience and knowledge
promise to provide invaluable insights and practical guidance to all participants, ensuring a
fruitful learning experience.

The following is the delivery plan from 6th to 11th May 2024.

Date 9:30 AM to 11.30 AM 12:00 AM to 1:00 PM 2:00PM to 4:30 PM 4.30 PM to 5.00 PM

Review of OOP'S
concept's, Polymorphism,
Virtual class, pure virtual
class, Abstract class,
Typedef, Shallow copy Parametrized class,
Monday, and Deep copy, Scope Encapsulation and
06 /05/ 2024 resolution operator. Dynamic casting. Lab Sessions Assessment
Randomization - Basics
of randomization, Direct Continuation of
Vs Random testing, Constraints - Conditional
Constrained Random, (if),
Constraints - inside, iterative (foreach), inline
Tuesday, implication and solve constraint, soft constraint,
07 /05/ 2024 before. Rand case. Lab Sessions Assessment
Inter-process
communication - Fork
join, fork join_any, fork Triggered event, wait
Wednesday, join_none, Disable fork. event, @ event, Mailbox,
08 /05/ 2024 wait fork. "Events - Semaphores Lab Sessions Assessment

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ChipEdge Training Session on RTL Verification using System Verilog part-I

Blocking event ( ->) non-

blocking event ( ->>)
Assertions - SV event
regions, Program block,
advantages of assertions,
Introduction to
Thursday, assertions, Types of Continuation of types of
09 /05/ 2024 assertions. assertions. Lab Sessions Assessment
Coverage - Functional
Friday, coverage, Cover groups, Cover bins and cross
10 /05/ 2024 Cover points. coverage. Lab Sessions Assessment
Students has to create
Saturday, Test bench creation for complete architecture for Continuation of test
11 /05/ 2024 full adder. full adder. bench creation. Assessment

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ChipEdge Training Session on RTL Verification using System Verilog part-I

CHAPTER 2

About ChipEdge:

ChipEdge, located in Bengaluru, stands as a prominent institution specializing in

semiconductor design and verification training. With its strategic presence in the Silicon
Valley of India, ChipEdge plays a pivotal role in nurturing talent and fostering innovation in
the semiconductor industry. The institute offers a comprehensive array of courses and
workshops covering various aspects of chip design, verification, and system-on-chip (SoC)
development, catering to both aspiring professionals and seasoned engineers seeking to
enhance their skills and stay abreast of industry trends.

At ChipEdge, emphasis is placed not only on theoretical learning but also on hands-on
practical experience, ensuring that students are well-equipped to tackle real-world challenges
in semiconductor design. The institute boasts state-of-the-art labs equipped with industry-
standard tools and simulation software, providing students with a conducive environment to
experiment, innovate, and refine their skills under the guidance of experienced mentors.
Through a combination of lectures, case studies, and project work, ChipEdge fosters a
dynamic learning ecosystem that encourages creativity, critical thinking, and collaboration
among participants.

Moreover, ChipEdge serves as a hub for industry-academia collaboration, facilitating

partnerships between leading semiconductor companies and academic institutions. The
institute regularly organizes industry seminars, guest lectures, and networking events,
providing students and professionals with valuable opportunities to interact with industry
experts, exchange ideas, and explore potential career avenues. Additionally, ChipEdge
actively engages with the semiconductor community through its participation in industry
conferences, research collaborations, and technology forums, contributing to the
advancement of semiconductor technology and the growth of the ecosystem in Bengaluru and
beyond. In essence, ChipEdge plays a vital role in shaping the future of the semiconductor
industry by empowering individuals with the knowledge, skills, and connections needed to
drive innovation and excellence in chip design and verification.

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ChipEdge Training Session on RTL Verification using System Verilog part-I

CHAPTER 3

Overview of the Training:

The training session on RTL Verification using System Verilog Part-II was organized with a
structured schedule spanning six days. Beginning with a Review of OOP'S concept's,
Polymorphism, Virtual class, pure virtual class, Abstract class, Typedef, Shallow copy and
Deep copy, Scope resolution operator, the schedule gradually progressed through
fundamental topics such as Introduction to assertions, types of assertions, coverage -
functional coverage, cover groups, cover points, test bench creation for full adder. Each day
was divided into two sessions, starting from 9:30 AM and extending till 5:00 PM, allowing
for comprehensive coverage of the curriculum. Lab sessions were strategically integrated into
the afternoon sessions of the schedule, allowing participants to engage in practical exercises
and hands-on learning experiences. The daily assessments acted as checkpoints to evaluate
participants' understanding, while the well-designed schedule ensured a comprehensive
understanding of RTL verification, equipping them with essential skills for future success.
Training Schedule:
An outline detailing the topics covered during each day of the training is provided below:

Day 1: Review of OOP'S concept's, Polymorphism, Virtual class, Pure virtual class, Abstract
class, Typedef, Shallow copy and Deep copy, Scope resolution operator, Parametrized class,
Encapsulation and Dynamic casting:

The training session started on Monday, 06/05/2024, initiating with an introductory session
on, review of OOP'S concept's, polymorphism, virtual class, pure virtual class, abstract class,
typedef, shallow copy and deep copy, Scope resolution operator critical for understanding the
foundation of OOP’S. Subsequently, participants delved into a detailed exploration of
parametrized class, encapsulation and dynamic casting in System Verilog, essential for
accurately representing hardware components in digital design.

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ChipEdge Training Session on RTL Verification using System Verilog part-I

The day completed with lab sessions meticulously designed to reinforce understanding
through practical exercises, providing participants with hands-on experience in implementing
data types within verification environments, thus solidifying their comprehension and
application of the learned concepts.

Day 2: Randomization - Basics of randomization, Direct Vs Random testing, Constrained

Random, Constraints - inside, implication and solve before, Continuation of Constraints -
Conditional (if), iterative (foreach), inline constraint, soft constraint, Rand case.:
On Tuesday, 07/05/2024, participants delved into the exploration of more intricate subjects,
namely randomization, random testing, and constraints, crucial for robust digital design and
RTL verification. These topics offered participants a deeper insight into organizing and
managing data within hardware designs effectively. Through dedicated lab sessions focusing
on constraints, participants gained hands-on experience on using constraints, sharpening their
skills for real-world application in system Verilog. The day completed with an assessment
aimed at evaluating participants aptitude in implementing and leveraging randomization,
random testing, and constraints, thereby consolidating their understanding and proficiency in
these foundational concepts.

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ChipEdge Training Session on RTL Verification using System Verilog part-I

Day 3: Inter-process communication - Fork join, fork join_any, fork join_none, Disable fork.
wait fork. "Events - Blocking event ( ->) non-blocking event ( ->>), triggered event, wait
event, @ event, Mailbox, Semaphores:

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ChipEdge Training Session on RTL Verification using System Verilog part-I

Progressing to Wednesday, 08/05/2024, the focus shifted towards events, fork and join
concepts, integral components of System Verilog methodologies. Participants delved into the
significance of mailbox and semaphore in facilitating communication between different
modules, a crucial aspect of designing complex digital systems. Additionally, the exploration
of events equipped participants with the ability to design modular, reusable, and scalable
modules, enhancing efficiency and maintainability. Through hands-on lab sessions dedicated
to fork and join and events, participants gained practical experience in implementing and
utilizing them effectively, preparing them to tackle challenges in System Verilog projects.
The day concluded with an assessment aimed at evaluating participants ability to apply
acquired knowledge in designing robust verification environments, thereby reinforcing their
understanding and proficiency in the above concepts.
Day 4: Assertions-SV event regions, Program block, advantages of assertions,
Introduction to assertions, Types of assertions:

Proceeding on Thursday, 09/05/2024, the training session delved into an in-depth exploration
of Assertion concepts, reinforcing participants' grasp on this critical aspect of System
Verilog. Through focused lab sessions, participants gained practical exposure to assertion,
empowering them to implement design methodologies effectively in their verification
projects. This hands-on experience enabled participants to utilize encapsulation, inheritance,
and polymorphism to create modular and scalable verification environments, enhancing their
efficiency in System Verilog tasks. The session concluded with a final assessment, providing
participants with an opportunity to reflect on their learning journey and assess their overall
proficiency in System Verilog, thus highlighting the practical application and significance of
assertion concepts in real-world verification scenarios.

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ChipEdge Training Session on RTL Verification using System Verilog part-I

Day 5: Coverage - Functional coverage, cover groups, cover points, coverage - functional
coverage, cover groups, cover points.

The training session on Friday, 10/05/2024, commenced with a brief explanation of

Functional Coverage to test your design works as expected, Cover Groups to categories for
specific functionalities (e.g., vending machine coin insertion), Cover Points for individual
aspects you test within a cover group. Participants were provided with a detailed exploration

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ChipEdge Training Session on RTL Verification using System Verilog part-I

of the coverage concepts. In the afternoon, participants engaged in practical exercises,

executing programs designed to implement coverages.

Day 6: Test bench creation for full adder

The training session on Saturday, 11/05/2024, began with a brief explanation on test bench
creation. It provides various functionalities such as Stimulus Generation is that the test bench
generates different input signals (test cases) to exercise your System Verilog design, Driving
Inputs is that in which test cases are fed as inputs to your design under test (DUT),
Monitoring Outputs is the test bench observes the outputs produced by the DUT, Verification
& Coverage is the test bench compares the DUT's outputs with expected results and tracks
which functionalities have been tested (coverage).
Overall, the session successfully gave the opportunity of creating test benches and gave
hands-on experience with System Verilog coding, especially with verification methodologies.
we gained a deeper understanding of how System Verilog constructs are used for verification
purposes. Developing test cases and analyzing results for our problem-solving skills, a
valuable asset in any engineering field.

The training session on RTL Verification using System Verilog Part-II was attended by 82
enthusiastic students from the Department of Electronics and Communication, providing a
comprehensive platform for skill development. Through a structured curriculum, hands-on
lab experiences, and assessments, students gained a deeper understanding of System Verilog
and its applications in RTL verification. Feedback from students was overwhelmingly
positive, expressing gratitude for the valuable learning experience. They found the sessions
extremely useful, praising the effective coverage of essential topics, engaging hands-on lab
experiences, and insightful assessments. Additionally, students commended the trainers'
knowledge and expertise in delivering complex concepts clearly. Overall, the session
successfully met its objectives, equipping students with essential skills and knowledge to
excel in RTL verification, and received high praise from all participants.

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ChipEdge Training Session on RTL Verification using System Verilog part-I

CHAPTER 4

Student Feedback:

The chart below shows the aggregate of student’s feedback for each day’s activity. Each
student's feedback on the session was also recorded.

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