memory

UNIT 4
(BEC 41)
VLSI DESIGN
Lecture 1
PRESENTED BY
Prof. R. K. Chauhan
FACULTY ECE DEPARTMENT
M.M.M UNIVERSITY OF TECHNOLOGY GORAKHPUR
Semiconductor Memories
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)
Read/Write Memory Read Only Memory

Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)
Serial In Parallel In First In Last In

Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)
Mask ROM Programmable Erasable Electrically Flash ROM

ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)
Dynamic Read-Write Memory (DRAM) Circuits
• As the trend for high-density RAM arrays forces the memory cell size to
shrink, alternative data storage concepts must be considered to
accommodate these demands.
• In a dynamic RAM cell, binary data is stored simply as charge in a
capacitor, where the presence or absence of stored charge determines
the value of the stored bit.
• Note that the data stored as charge in a capacitor cannot be retained
indefinitely, because the leakage currents eventually remove or modify
the stored charge.
• Thus, all dynamic memory cells require a periodic refreshing of the
stored data, so that unwanted modifications leakage are prevented
before they occur.
Dynamic Read-Write Memory (DRAM) Circuits
Fig. Various configurations of the dynamic RAM cell.
(a) Four-transistor DRAM cell with two storage

nodes.
(b) Three-transistor DRAM cell with two bit lines and

two word lines.
(c) One-transistor DRAM cell with one bit line and

one word line.
DRAM Array
SRAM Cell
• Basic building block: SRAM Cell bit bit_b
• Holds one bit of information, like a latch
• Must be read and written word
• 6T SRAM Cell
• Used in most commercial chips
• Data stored in cross-coupled inverters
• Read:
• Precharge bit, bit_b
• Raise wordline
• Write:
• Drive data onto bit, bit_b
• Raise wordline
SRAM Read bit bit_b
word
P1 P2
N2 N4
• Precharge both bitlines high A A_b

N1 N3
• Then turn on wordline
• One of the two bitlines will be pulled down by the cell
A_b bit_b
• Ex: A = 0, A_b = 1
• bit discharges, bit_b stays high 1.5
• But A bumps up slightly 1.0

word bit
• Read stability 0.5
• A must not flip A
• N1 >> N2 0.0
0 100 200 300 400 500 600
time (ps)
SRAM Write
bit bit_b
• Drive one bitline high, the other low word
• Then turn on wordline N2
P1 P2
N4
• Bitlines overpower cell with new value A A_b
• Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 N1 N3
• Force A_b low, then A rises high

• Writability
A _b
A
• Must overpower feedback inverter
1 .5
b it_ b
• N2 >> P1 1 .0
0 .5
w o rd
0 .0
0 100 200 300 400 500 600 700
tim e ( p s )
SRAM Sizing
• High bitlines must not overpower inverters during reads
• But low bitlines must write new value into cell
bit bit_b
word
weak
med med
A A_b
strong
SRAM Column Example
Bitline Conditioning
2
Bitline Conditioning
More
Cells 2
word_q1
More
bit_b_v1f Cells
bit_v1f
SRAM Cell
word_q1
H H
bit_b_v1f
out_b_v1r out_v1r
bit_v1f
1 SRAM Cell
2
word_q1 write_q1
bit_v1f
out_v1r
data_s1
1-D Memory Architecture
2- D Memory Architecture
SRAM vs DRAM
• SRAM is made up of flip flop

• DRAM is made up of Transistor and Capacitor
• DRAM is at least ten times slower than SRAM
• SRAM is faster and typically used for cache
• DRAM is less expensive and has a higher
density and has a primary use as main
processor memory.
• SRAM does not use capacitors so refreshing
circuitry is not required
• Both are volatile.
SRAM vs DRAM
SRAM DRAM
Speed Faster Slower
Size Small Large
Cost Expensive Cheap
Used in Cache memory Main memory

Density Less dense Highly dense
Construction Complex and uses transistors Simple and uses capacitors
and latches. and very few transistors.
Single block of memory 6 transistors Only one transistor.
requires
Charge leakage property Not present Present hence require power
refresh circuitry
Power consumption Low High

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UNIT 4

Random Access Memory Serial Access Memory Content Addressable Memory

Read/Write Memory Read Only Memory

Serial In Parallel In First In Last In

Mask ROM Programmable Erasable Electrically Flash ROM

Fig. Various configurations of the dynamic RAM cell.

(a) Four-transistor DRAM cell with two storage

(b) Three-transistor DRAM cell with two bit lines and

(c) One-transistor DRAM cell with one bit line and

• Precharge both bitlines high A A_b

• But A bumps up slightly 1.0

• Read stability 0.5

• A must not flip A

• Force A_b low, then A rises high

• SRAM is made up of flip flop

Used in Cache memory Main memory

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