The document outlines the design, simulation, and implementation of an AND gate using Xilinx ISE Navigator versions 9.2i and 14.7. It details the procedures for creating a new project, writing Verilog code, synthesizing the design, and programming the FPGA Spartan-3E Starter Board. The final result confirms successful design and simulation of the AND gate using the specified software and hardware tools.
The document outlines the design, simulation, and implementation of an AND gate using Xilinx ISE Navigator versions 9.2i and 14.7. It details the procedures for creating a new project, writing Verilog code, synthesizing the design, and programming the FPGA Spartan-3E Starter Board. The final result confirms successful design and simulation of the AND gate using the specified software and hardware tools.
The document outlines the design, simulation, and implementation of an AND gate using Xilinx ISE Navigator versions 9.2i and 14.7. It details the procedures for creating a new project, writing Verilog code, synthesizing the design, and programming the FPGA Spartan-3E Starter Board. The final result confirms successful design and simulation of the AND gate using the specified software and hardware tools.
The document outlines the design, simulation, and implementation of an AND gate using Xilinx ISE Navigator versions 9.2i and 14.7. It details the procedures for creating a new project, writing Verilog code, synthesizing the design, and programming the FPGA Spartan-3E Starter Board. The final result confirms successful design and simulation of the AND gate using the specified software and hardware tools.
NO: STUDY EXPERIMENT : DESIGN ENTRY, SIMULATION AND
IMPLEMENTATION OF AND GATE DATE :
AIM: To study the Simulation and synthesis tools of XILINX ISE NAVIGATOR 9.2i and 14.7 with an example program of AND Gate.
THEORY: • Simulation is functional emulation of the circuit design through software programs that uses models to replicate how a system will perform in terms of timings and results. • Xilinx ISE tool supports the following simulation tools: • HDL Bencher is an automated test bench creation tool. It is fully integrated with Project Navigator. • ModelSim from Model Technology, Inc, is integrated in Project Navigator to simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model Technology,Inc.’s ModelSim application, can be installed from the MTE CD included in ISE Tool • Synthesis describes the process of transformation of the model of a design, from one level of abstraction in one domain [say HDL] to a lower level of abstraction in same or other domain. SIMULATION Procedure: 1. To start ISE, double-click the desktop icon, or start ISE from the Start menu by selecting: Start All Programs Xilinx ISE 9.2i Project Navigator 2. Create a new ISE project which will target the FPGA device on the Spartan- 3 Startup Kit demo board. 3. To create a new project: I. Select File > New Project... The New Project Wizard appears. II. Type andgate in the Project Name field. III. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. IV. Verify that HDL is selected from the Top-Level Source Type list. V. Click Next to move to the device properties page.
Reg.No:61072112113 4. Choose the Device(XC3S400), Family(Spartan3) ,package(TQ144), Simulator(ISE Simulator),Language(Verilog) and click on Next button.
Reg.No:61072112113 5.From the New Source Wizard, select Verilog Module and give the filename as andgate in the specified project location.
6.Specify the input and output ports required for the design.
Reg.No:61072112113 7. Enter the Verilog code in the workspace and Save the program. 8. Click the “+” next to the Synthesize-XST process to expand the process group. 9. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.
10.Right click on the project name and create a new Testbench Waveform with the name andgate_tbw and click on Next button.
Reg.No:61072112113 11. Provide the timing control and Length of simulation as below and click on Finish button.
12. Force the inputs(A,B) to the Testbench waveform. On the Sources tab, select Behavioral Simulation. Click on Processes tab to expand Xilinx ISE Simulator.
Reg.No:61072112113 13. Click on Simulate behavioral Model so that the following Simulation Waveform appears.
14. Close the Simulation window. On the Processes tab expand on Implement Design tab. Double click on it so that Translate, Map, Place & Route operations are complete with the Green mark
Reg.No:61072112113 15. Expand on User Constraints and click on Assign Package Pins to assign Pin Numbers on Xilinx Pace window.
16. An UCF file with the specified I/O Pin assignments is created.
Reg.No:61072112113 17. Make necessary Power and JTAG cable connections between the Xilinx kit and the Personal Computer and Power on the Kit.
18. Select Boundary scan and right click nd add Xilinx device in your system. Then go to output file type and select the xsvf file and create a xsvf file and save it as follows.
Reg.No:61072112113 18.1. Then go to output file type and select the xsvf file and create a xsvf file and save it as follows.
Reg.No:61072112113 19. Assign New Configuration File. Click on andgate.bit and open the file.Then right click on device and program it as follows.
20. A Boundary Scan window appears. Right click on the Xilinx xc3s400 device and click Program. Once the program is downloaded to the FPGA, Program Succeeded appears.
Reg.No:61072112113 20.1. After programming the bit file from the device, the program succeed message will be displayed.Then save file and close the window and go to Topview Programmer for FPGA Board Implementation.
Reg.No:61072112113 21. Open the Topview Programmer application from your system.
22. Now select file name or Browse for the xsvf file that is created as generating file to configure in FPGA Board in your save files.
Reg.No:61072112113 23. Then click on “GetDeviceID” to check the status of your FPGA Board.
24. Then click “Configure” to configure the file then check the downloading status. 21. Inputs are set on the board and the corresponding outputs are verified on the Add on card LED’s.
RESULT: Thus, AND GATE is designed and Simulation is done using XILINX ISE Software(14.7) and Implementation is done using FPGA Spartan- 3E Starter Board.
