Module 4

Control unit design

MICRO-PROGRAMMED APPROACH

Rithesh Kini, Computer Engg Dept., TSEC

Functional Requirement of a Processor*
1. Operations (Opcodes)
2. Addressing Modes
3. Registers
4. I/O Module Interface
5. Memory Module Interface
6. Interrupts

*the list of things needed to specify the function of a processor

Functional Requirement of a Processor
How to control
various How to
1. Operations (Opcodes) elements of Perform
processor? these
2. Addressing Modes Functions?
3. Registers
4. I/O Module Interface
5. Memory Module Interface
6. Interrupts
CONTROL UNIT

Rithesh Kini, Computer Engg Dept., TSEC

Control unit

• Component of a computer's central processing unit (CPU)

• Directs the operation of the processor

• Tells the computer's memory, ALU and input/output devices how to

respond to a program's instructions

• Directs the flow of data between the CPU and the other devices
Control unit operations

• The control unit is responsible for initiating the sequence of

“microoperations” that comprise instructions.

• When these control signals are generated by hardware, the control unit is
hardwired.

• When these control signals originate in data stored in a special unit and
constitute a program (on the small scale), the control unit is
microprogrammed.
Control unit – operations

• Execution of a program consists of the sequential execution of instructions.

• Each instruction is executed during an instruction cycle.

• Each instruction cycle is made up of shorter sub cycles.

• The execution of each sub cycle involves one or more shorter operations, that
is, micro-operations.

• Micro-operations are the functional, or atomic, operations of a processor.

Micro – operations Constituent Elements of
a Program Execution

Program Execution

Instruction Cycle Instruction Cycle ... Instruction Cycle

Fetch Indirect Execute Interrupt

µ Op µ Op µ Op µ Op
Micro – operations

• Purpose of CU is to issue control signals or instructions to the data processing

part.
• It initiates sequences of micro-operations available in a given system.
• Each instruction is executed during an instruction cycle made up of shorter sub
cycles
• Fetch
• Indirect
• Execute
• Interrupt

Rithesh Kini, Computer Engg Dept., TSEC

 Fetch Cycle (Ref: Book by W Stallings)
Occurs at the beginning of each instruction cycle and causes
an instruction to be fetched from memory.
The 4 Micro operations can be
Remember, at the beginning of the fetch cycle the address of written as,
next the instruction is in PC. t1 : MAR ← PC
Sequence of event are : t2 : MBR ← Memory

1. Address in PC is moved to MAR which is connected to bus PC ← PC + 1

2. Address in MAR placed on the address bus; CU issues a t3 : IR ← MBR

READ command on control bus and the result appears on the

Note: It is assumed that every
data bus; result is copied into MBR instruction is 1-byte instruction.
Hence, PC is incremented by 1.
3. Increment PC by 1 to get ready for next instruction
 Indirect Cycle (Ref: Book by W Stallings)
• Once instruction is fetched, next step is to fetch source
operand.
Micro operations can be written as
• If the instruction specifies an indirect address, the indirect
cycle precede the execute cycle. t1 : MAR ← (IR (Address))

Sequence of the events are: t2 : MBR ← Memory

1. Address field of the instruction is transferred to the MAR. t3 : IR (Address) ← (MBR (Address))
2. It is used to fetch the address of the operand.

3. Lastly, the address field of the IR is updated from the MBR,

Now IR contains a direct rather than an indirect address and

it is ready for the execute cycle
 Execute Cycle (Ref: Book by W Stallings)
• In execute cycle for a machine with N different
opcodes,
Micro operations can be written as
• There are N different sequence of micro-
operations that occur. t1 : MAR ← (IR (Address))
Example:
t2 : MBR ← Memory
Consider the execute cycle for the instruction
ADD R1, X t3 : R1 ← (R1) +(MBR)

which adds the contents of the location X to

register R1
Interrupt Cycle (Ref: Book by W Stallings)
• A test is made to determine whether any interrupt is enabled at
the end of execution cycle. Micro operations can be
written as,
• If interrupt is enabled then the interrupt cycle occurs.
t1 : MBR ← PC
Sequence of the events are :
t2 : MAR ← Save Address
1. Contents of the PC are transferred to the MBR
PC ← Routine Address
2. MAR is loaded with the address at which the contents of the PC
t3 : Memory ← (MBR)
are to be saved
3. PC is loaded with the address of the start of the interrupt-
processing routine
4. Store the MBR, which contains the old value of the PC, into
memory.
Control of the Processor

Three-step process to characterize the 1. Basic Elements of Processor

control unit :
 ALU
1. Define Basic Elements of Processor
 Registers
2. Describe micro-operations the processor  Internal data paths
performs  External data paths
 Control Unit
3. Determine functions control unit must
perform (Functional Requirements)
 Control of the Processor
Three-step process to characterize the 2. Types of Micro-operation
control unit :
1. Define Basic Elements of Processor  Transfer data between registers

2. Describe micro-operations processor  Transfer data from register to external

performs interface

3. Determine functions control unit  Transfer data from external interface to

must perform register

 Perform arithmetic or logical operations

 Control of the Processor
Three-step process to characterize the 3. Functions of Control Unit
control unit :
 Sequencing:
1. Define Basic Elements of Processor
Causes the CPU to step through a series
2. Describe micro-operations processor
of micro-operations
performs
 Execution:
3. Determine functions control unit
must perform Causing the performance of each micro-
operations

This is done using Control Signals

 General Model of Control Unit

Instruction Register

Control Bus
Flags Control Signals to Control Bus
Control
Unit
Control Signals from Control Bus

Clock
Control Signals
within CPU
Control Unit Inputs
 Clock
• One micro-operation (or set of parallel micro-operations) per clock cycle
 Instruction register
• For op-code & addressing mode for current instruction
• Determines which micro-operations to perform.
 Flags
• Status of CPU &
• Results of previous ALU operations
 Control signals from control bus
• Interrupts
• Acknowledgements
Control Unit – Outputs
 Control signals within CPU

• Cause data movement between registers

• Activate Specific ALU Function

 Control signals to Control Bus Three types of control signals are used :

• To memory 1. Activate an ALU function

2. Activate a data path

• To I/O Modules
3. The external system bus or external interface
 Data path & control signals
Control signals go to 3 separate destinations:
1. Data path:
• CU controls the internal flow of data e. g.
IRMBR during Instruction fetch
2. ALU:
• CU controls operation of ALU by a set of
control signals
• Activate various logic gates & devices within
ALU
3. System bus:
• CU sends control signals out onto the
control lines of system bus (e.g., memory
READ)
Rithesh Kini, Computer Engg Dept., TSEC
 Fundamental Concepts
 Processor fetches one instruction at a time and perform the operation
specified.
 Instructions are fetched from successive memory locations until a branch or
a jump instruction is encountered.
 Processor keeps track of the address of the memory location containing the
next instruction to be fetched using Program Counter (PC).
 Instruction Register (IR)
 Fundamental Concepts
 Fetch the contents of the memory location pointed to by the PC.
 The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable, increment the contents of
the PC by 4 (fetch phase).
PC ← [PC] + 4
 Carry out the actions specified by the instruction in the IR (execution phase).
 Internal processor

Single Bus Organization of bus

Control signals

Data Path PC

Instruction
Address
decoder and
lines
MAR control logic
MDR HAS Memory
ALU & all registers TWO bus

interconnected via a INPUTS MDR

Data
single common AND TWO lines IR

OUTPUTS
internal processor
Y
bus Constant 4 R0

Temporary register
Select MUX

Add
A B
This architecture assumes that - ALU Sub R( n - 1)
control
a. Each instruction comprises 4 bytes & is lines
ALU

stored in 1 memory word. Carry-in

XOR TEMP
b. Memory is byte addressable.
So, Constant 4 is used to increment PC by 4. Z

Scratch pad
Rithesh Kini, Computer Engg Dept., TSEC
Executing an Instruction

Different operations performed during instruction execution :

1. Transfer a word of data from one processor register to another or to the ALU.

2. Perform an arithmetic or a logic operation and store the result in a processor

register.

3. Fetch the contents of a given memory location and load them into a processor
register.

4. Store a word of data from a processor register into a given memory location.
 Internal processor
bus
Riin
Register Transfers
Ri

Riout
Yin

Y
Constant 4

Select MUX

A B
ALU

Zin

Suppose we want to transfer the content of Zout

Register R1 to R4
Figure: Input and output gating for the registers.
Rithesh Kini, Computer Engg Dept., TSEC
Performing an Arithmetic or Logic Operation
Internal processor
bus
Control signals
Suppose we want to add the contents
PC
of Register R1 to R2 and store the
Instruction
result in R3 Address
lines
decoder and
MAR control logic
Memory
Sequence of operations : bus

1. R1out, Yin Data

lines
MDR
IR
2. R2out, Select Y, Add, Zin
3. Zout, R3in Constant 4
Y
R0

Select MUX
Signals whose names are given in any
step are activated for the duration of Add
A B
Sub R( n - 1)
clock cycle corresponding to that step. ALU
control ALU
lines
Carry-in
XOR TEMP

Z
Fetching a Word from Memory
Address into MAR; issue Read operation control signal; data into MDR.

Memory-bus Internal processor

data lines MDRoutE MDRout bus

MDR

MDR MDRin
inE

Connection and control signals for register MDR.

E subscript in MDR inE & MDR outE => External

 Fetching a Word from Memory
• The response time of each memory access varies (cache miss,…).

• To accommodate this, the processor waits until it receives an indication that the requested
operation has been completed (Memory-Function-Completed, MFC).

E.g., MOVE R2, (R1)

• The contents of memory address in R1 should be read and loaded into R2
Actions needed:

1. MAR ← [R1]

2. Start a Read operation on the memory bus

3. Wait for the MFC response from the memory

4. Load MDR from the memory bus

5. R2 ← [MDR]
 Step 1 2 3

Assume MAR o/p

Clock
is always available
on the address lines
of the memory bus.
MARin MAR ← [R1]

Simultaneously Address

As step 1-2 & 3-4 can be Read

Start a Read operation on the memory bus
combined we require only
MR
3 steps for Mem. Read:
MDRinE

1. R1out, MARin, Read Data

2. WMFC, MDRinE Wait for the MFC response from the memory
MFC
3. MDRout, R2in
MDR out Load MDR from the memory bus R2 ← [MDR]

Figure 7.5. Timing of a memory Read operation.

Rithesh ini, Computer Engg Dept., TSEC
 Storing a Word in Memory
Memory-bus Internal processor
data lines MDRoutE MDRout bus

MOVE (R1), R2
• The contents of R2 should
be stored in the memory
address given by R1 MDR

1. R1out, MARin
2. R2out, MDRin , Write
MDR MDRin
3. MDRoutE, WMFC inE
Execution of a Complete Instruction
Add R1, (R3)
• Fetch the instruction
• Fetch the first operand (the contents of the memory location pointed
to by R3)
• Perform the addition
• Load the result into R1
 Internal processor
bus

R i in

Architecture used Ri

R i out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Internal processor
bus

Execution of a Complete Instruction PC

Control signals

Instruction
Add R1, (R3) Address
decoder and
lines
MAR control logic
Step Action Memory
bus

MDR
1 PCout , MARin , Read,Select4,Add, Zin Data
lines IR
Opcode 2 Zout , PCin , WMFC
Fetch
3 MDRout , IRin Y
Constant 4 R0
4 R3out , MARin , Read
Execute 5 R1out , Yin , WMFC Select MUX
R1<-R1+(R3) 6 MDRout , SelectY,Add, Zin Add
A B
7 Zout , R1in , End ALU Sub R( n - 1)
control ALU
lines
Carry-in
XOR TEMP

Z
Figure7.6. Control sequence
for executionof the instruction Add (R3),R1.
 Internal processor
bus

Execution of a Complete Instruction PC

Control signals

Instruction
Add R1, R2 Address
decoder and
lines
MAR control logic
Step Action Memory
bus

MDR
1 PCout , MARin , Read,Select4,Add, Zin Data
lines IR
Opcode 2 Zout , PCin , WMFC
Fetch 3 MDRout , IRin Y
Constant 4 R0

Execute 4 R1out , Yin Select MUX

R1<-R1+R2 5 R2out , SelectY, Add, Zin Add

A B
6 Zout , R1in , End ALU Sub R( n - 1)
control ALU
lines
Carry-in
XOR TEMP

Z
Figure7.6. Control sequence
for executionof the instruction Add (R3),R1.
 Execution of Branch Instructions
• A branch instruction replaces the Step Action
contents of PC with the branch target
1 PCout , MAR in , Read, Select4,Add, Z in
address, which is usually obtained by Fetch 2 Zout , PCin , Yin , WMF C
adding an offset X given in the branch 3 MDR out , IR in
instruction. 4 Offset-field-of-IRout, Add, Z in
5 Z out , PCin , End
• The offset X is usually the difference
between the branch target address
Figure 7.7. Control sequence for an unconditional
and the address immediately branch instruction.

following the branch instruction.

• Conditional branch
Multiple-Bus Organization
Step Action

1 PCout, R=B, MARin , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4 , R5 , Select-A,Add, R6 in , End
outA outB

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
Multiple-Bus Organization
• Add R4, R5, R6
Add the numbers in register R4 & R5 and store the result in R6

Step Action

1 PCout, R=B, MARin , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4 , R5 , Select-A, Add, R6in , End
outA outB

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
Control unit implementation

Two categories for CU implementation:

1. Hardwired Implementation : the digital circuits generate the control

signals.

2. Microprogrammed (Softwired) Implementation : the control signals are

stored as bit patterns in a read only memory, inside the control unit.
Microprogrammed Control
 Overview
Add R1, (R3)
Step Action

1 PCout , MARin , Read,Select4,Add, Zin

Fetch 2 Zout , PCin , WMFC
3 MDRout , IRin
4 R3out , MARin , Read
Execute 5 R1out , Yin , WMFC
6 MDRout , SelectY,Add, Zin
7 Zout , R1in , End

Figure 7.6. Control sequence for execution of the instruction Add (R3),R1.
Overview

Control signals are generated by a program similar to machine language

programs.

Control Word (CW) : a word whose individual bits represent control signal.
Microroutine : A sequence of CWs corresponding to the control sequence of
a machine instruction.

Microinstruction : the individual control words in the microroutine

Rithesh Kini, Computer Engg Dept., TSEC

 The microroutine of all instructions in the instruction set of a computer are stored
in a special memory called control store.
 The CU can generate control signals for any instruction by sequentially reading
the CWs of the corresponding microroutine from the control store.
 From the Fig 7.16 , to read control words sequentially from the control store, a
microPC(µPC) is used.
 Every time a new instruction is loaded into IR, the output of the block “starting
address generator” is loaded into the µPC.
 The µPC is then automatically incremented by the clock , causing successive
µinstruction to be read from the control store.
 This simple organization cannot work when the control unit is required to check
the status of the condition codes or external inputs to choose between
alternative courses of action.
 To handle this use conditional branch microinstruction.
 In addition to the branch address, these microinstructions specify which of the
external inputs, condition codes, or possibly bits of the instruction register,
should be checked as a condition for branching to take place.
 An instruction Branch < 0 may be implemented by a microroutine such as that
shown in Figure 7.17
Microinstructions
 A straightforward way to structure microinstructions is to assign one bit
position to each control signal.
 However, this is very inefficient.
 The length can be reduced: most signals are not needed simultaneously,
and many signals are mutually exclusive.
 All mutually exclusive signals are placed in the same group in binary coding
Microinstructions
 A straightforward way to structure microinstructions is to assign one bit
position to each control signal.
 However, this is very inefficient.
 The length can be reduced: most signals are not needed simultaneously,
and many signals are mutually exclusive.
 All mutually exclusive signals are placed in the same group in binary coding
What is the price paid for this scheme?
Summary
 Single Bus Organization
 Microprogram for single bus organization
 Multiple (3) Bus organization
 Microprogram for 3-bus organization
 Microprogrammed Approach
References
1. Computer Organization and Architecture, 10th Edition by William
Stallings (Upto slide 21)
2. Computer Organization by Safwat Zaky, V. Carl Hamacher, Zvonko G.
Vranesic (from slide 22)