Object-Oriented Programming in SystemVerilog
Introduction
This example demonstrates Object-Oriented Programming (OOP) in SystemVerilog using class in-
heritance. The ‘add‘ class performs addition, and the ‘mul‘ class extends it to include multiplication.
SystemVerilog Code
Class Definition and Inheritance
class add ;
bit [3:0] a ;
bit [3:0] b ;
bit [4:0] c ;
function new ( bit [3:0] a , bit [3:0] b ) ;
this . a = a ;
this . b = b ;
this . c = this . a + this . b ; // Ensure correct init ializati on
endfunction
endclass
// / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
class mul extends add ;
bit [7:0] r ; // Mul tiplicat ion result
function new ( bit [3:0] a , bit [3:0] b ) ;
super . new (a , b ) ; // Call parent constructor correctly
this . r = a * b ; // Multipl ication using inherited variables
endfunction
endclass
Testbench
module tb ;
mul t ;
bit [4:0] a ; // Matching c ’ s width
bit [7:0] m ; // Matching r ’ s width
initial begin
t = new (4 ’ b0001 , 4 ’ b0010 ) ;
a = t . c ; // Accessing superclass variable
m = t . r ; // Accessing subclass variable
$ display ( " Addition result : %0 d , Mul tiplicat ion result : %0 d " , a , m ) ;
end
endmodule
Expected Output
Addition r e s u l t : 3 , M u l t i p l i c a t i o n r e s u l t : 2
1
Explanation
The ‘add‘ class contains variables ‘a‘, ‘b‘, and ‘c‘, where ‘c = a + b‘.
The ‘mul‘ class extends ‘add‘ and introduces ‘r = a * b‘.
The testbench instantiates an object of ‘mul‘, calls the constructor, and prints the results.
Package File: add pkg.sv
package add_pkg ;
class add ;
bit [3:0] a ;
bit [3:0] b ;
bit [4:0] c ;
function new ( bit [3:0] a , bit [3:0] b ) ;
this . a = a ;
this . b = b ;
this . c = this . a + this . b ; // Ensure correct init ializati on
endfunction
endclass
endpackage
Main File: tb.sv
‘include " add_pkg . sv " // Include the package file
import add_pkg ::*; // Import the package
class mul extends add ;
bit [7:0] r ; // Mul tiplicat ion result
function new ( bit [3:0] a , bit [3:0] b ) ;
super . new (a , b ) ; // Call parent constructor correctly
this . r = a * b ; // Multipl ication using inherited variables
endfunction
endclass
// / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
module tb ;
mul t ;
bit [4:0] a ; // Matching c ’ s width
bit [7:0] m ; // Matching r ’ s width
initial begin
t = new (4 ’ b0001 , 4 ’ b0010 ) ;
a = t . c ; // Accessing superclass variable
m = t . r ; // Accessing subclass variable
$ display ( " Addition result : %0 d , Mul tiplicat ion result : %0 d " , a , m ) ;
end
endmodule
2
Compilation Instructions
To compile and run the testbench, follow this sequence:
v l o g add pkg . sv // Compile package f i r s t
v l o g tb . sv // Compile t h e main f i l e
vsim tb // Run s i m u l a t i o n
Expected Output
Addition r e s u l t : 3 , M u l t i p l i c a t i o n r e s u l t : 2
Explanation
The ’add’ class is encapsulated in ’add pkg.sv’ for modularity.
The ‘mul‘ class extends ‘add‘ and introduces ‘r = a * b‘.
The testbench instantiates ‘mul‘, calls the constructor, and prints the results.
