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Verilog Task and Function

The document outlines the differences between functions and tasks in Verilog. Functions are defined with 'function' and 'endfunction', cannot include timing delays, and always return a single value, while tasks are defined with 'task' and 'endtask', can include timing delays, and can pass values through multiple arguments. Both have specific syntaxes and calling conventions, with functions primarily used for combinational logic and tasks for both combinational and sequential logic.

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mohit topiya
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6 views6 pages

Verilog Task and Function

The document outlines the differences between functions and tasks in Verilog. Functions are defined with 'function' and 'endfunction', cannot include timing delays, and always return a single value, while tasks are defined with 'task' and 'endtask', can include timing delays, and can pass values through multiple arguments. Both have specific syntaxes and calling conventions, with functions primarily used for combinational logic and tasks for both combinational and sequential logic.

Uploaded by

mohit topiya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VERILOG-Task and Function

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Function
• A function is enclosed within keyword ‘function’ and
‘endfunction’.
• functions can’t include timing delays.
• It can take any number of argument as inputs but only
one output (Function Name).
• it must have at least one input argument
• It can call another function but not another task.
• function always returns a value and return type of
function is function name itself.
• Variable declare in function is local to that function.
• Can be Used to design combinational logic.
Continue….
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Function
• Syntax :
function [width] function_name (input arguments );
begin
function_body;
end
endfunction

• Calling a function
function_name (<expression_1>,<expression_2>….);
(note : while calling a function order of arguments must be same
as given while declaring a function)

• Synthesizable.

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Task
• A task is enclosed within keyword ‘task’ and ‘endtask’.
• tasks can include timing delays.
• It can take any number of argument as inputs, outputs
and inouts. (it can also have zero argument)
• It can call another task as well as function.
• task never returns a value but can pass values to output
and inouts arguments.
• Variable declare in task is local to that task.
• Used to design both combinational and sequential
logic.

Continue….
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Task
• Syntax :
task task_name (input/inout/output arguments );
begin
task_body;
end
endtask

• Calling a task
task_name (<expression_1>,<expression_2>….);
(note : while calling a task order of arguments must be same
as given while declaring a task)

• Task without delay is Synthesizable.

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Thank You

Questions ??

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