Tasks and Functions
Dr.Ravi Sindal
IET,DAVV,Indore
Today program
Reusing code
Tasks and Functions
Dr.Ravi Sindal,IET,DAVV,Indore
Introduction
Procedures/Subroutines/Functions in SW
programming languages
The same functionality, in different places
Verilog equivalence:
Tasks and Functions
Used in behavioral modeling
Part of design hierarchy Hierarchical name
Dr.Ravi Sindal,IET,DAVV,Indore
Contents
Functions
Tasks
Differences between tasks and functions
Dr.Ravi Sindal,IET,DAVV,Indore
Tasks and Functions
Functions
Functions
Keyword: function, endfunction
Can be used if the procedure
does not have any timing control constructs
returns exactly a single value
has at least one input argument
Dr.Ravi Sindal,IET,DAVV,Indore
Functions (cont’d)
Function Declaration and Invocation
Declaration syntax:
function <range_or_type> <func_name>;
<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction
Dr.Ravi Sindal,IET,DAVV,Indore
Functions (cont’d)
Function Declaration and Invocation
Invocation syntax:
<func_name> (<argument(s)>);
Dr.Ravi Sindal,IET,DAVV,Indore
Functions (cont’d)
Semantics
much like function in Pascal
An internal implicit reg is declared inside the
function with the same name
The return value is specified by setting that
implicit reg
<range_or_type> defines width and type of
the implicit reg
<type> can be integer or real
default bit width is 1
Dr.Ravi Sindal,IET,DAVV,Indore
Function Examples
Parity Generator
module parity; function calc_parity;
reg [31:0] addr; input [31:0] address;
reg parity; begin
calc_parity = ^address;
initial begin end
… endfunction
end
endmodule
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end
Dr.Ravi Sindal,IET,DAVV,Indore
Function Examples
Controllable Shifter
module shifter; function [31:0] shift;
`define LEFT_SHIFT 1'b0 input [31:0] address;
`define RIGHT_SHIFT 1'b1 input control;
reg [31:0] addr, left_addr, begin
right_addr; shift =
reg control; (control==`LEFT_SHIF
T) ?(address<<1) :
initial (address>>1);
begin end
… endfunction
end
endmodule
always @(addr)
begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end Dr.Ravi Sindal,IET,DAVV,Indore
Tasks and Functions
Tasks
Tasks
Keywords: task, endtask
Must be used if the procedure has
any timing control constructs
zero or more than one output arguments
no input arguments
Dr.Ravi Sindal,IET,DAVV,Indore
Tasks (cont’d)
Task declaration and invocation
Declaration syntax
task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask
Dr.Ravi Sindal,IET,DAVV,Indore
Tasks (cont’d)
Task declaration and invocation
Task invocation syntax
<task_name>;
<task_name> (<arguments>);
input and inout arguments are passed into
the task
output and inout arguments are passed
back to the invoking statement when task is
completed
Dr.Ravi Sindal,IET,DAVV,Indore
Tasks (cont’d)
I/O declaration in modules vs. tasks
Both used keywords: input, output,
inout
In modules, represent ports
connect to external signals
In tasks, represent arguments
pass values to and from the task
Dr.Ravi Sindal,IET,DAVV,Indore
Task Examples
Use of input and output arguments
module operation; task bitwise_oper;
parameter delay = 10; output [15:0] ab_and, ab_or,
reg [15:0] A, B; ab_xor;
reg [15:0] AB_AND, AB_OR, AB_XOR; input [15:0] a, b;
begin
initial #delay ab_and = a & b;
$monitor( …); ab_or = a | b;
ab_xor = a ^ b;
initial end
begin endtask
…
end
endmodule
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end
Dr.Ravi Sindal,IET,DAVV,Indore
Task Examples
Use of module local variables
module sequence; task init_sequence;
reg clock; clock = 1'b0;
endtask
initial
begin task asymmetric_sequence;
… begin
end #12 clock = 1'b0;
#5 clock = 1'b1;
initial #3 clock = 1'b0;
init_sequence; #10 clock = 1'b1;
end
always endtask
asymmetric_sequence;
endmodule
Dr.Ravi Sindal,IET,DAVV,Indore
Tasks and Functions
Differences between
Tasks and Functions
Differences between...
Functions Tasks
Can enable (call) just Can enable other tasks
another function (not and functions
task) May execute in non-
Execute in 0 simulation zero simulation time
time May contain any timing
No timing control control statements
statements allowed May have arbitrary
At lease one input input, output, or
Return only a single inout
value Do not return any value
Dr.Ravi Sindal,IET,DAVV,Indore
Differences between… (cont’d)
Both
are defined in a module
are local to the module
can have local variables (registers, but not nets) and
events
contain only behavioral statements
do not contain initial or always statements
are called from initial or always statements or other
tasks or functions
Dr.Ravi Sindal,IET,DAVV,Indore
Differences between… (cont’d)
Tasks can be used for common Verilog code
Function are used when the common code
is purely combinational
executes in 0 simulation time
provides exactly one output
Functions are typically used for conversions and
commonly used calculations
Dr.Ravi Sindal,IET,DAVV,Indore