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    Microprocessor & Computer Architecture (Μpca) : I/O And Bus Architecture

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    Pranathi Praveen
    The document discusses I/O and bus architecture. It describes how I/O devices connect to the CPU via an I/O bus and I/O controllers. There are two main methods for interfacing with I/O devices: memory mapped I/O which uses memory addresses to access devices, and I/O mapped I/O which uses separate instructions. Interrupts are an important method for asynchronous data transfer, where a device triggers an interrupt to signal the CPU. The CPU then services the interrupt request by saving context and jumping to an interrupt service routine before returning.

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    Microprocessor & Computer Architecture (Μpca) : I/O And Bus Architecture

    Uploaded by

    Pranathi Praveen
    30 views28 pages
    The document discusses I/O and bus architecture. It describes how I/O devices connect to the CPU via an I/O bus and I/O controllers. There are two main methods for interfacing with I/O devices: memory mapped I/O which uses memory addresses to access devices, and I/O mapped I/O which uses separate instructions. Interrupts are an important method for asynchronous data transfer, where a device triggers an interrupt to signal the CPU. The CPU then services the interrupt request by saving context and jumping to an interrupt service routine before returning.

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    The document discusses I/O and bus architecture. It describes how I/O devices connect to the CPU via an I/O bus and I/O controllers. There are two main methods for interfacing with I/O devices: memory mapped I/O which uses memory addresses to access devices, and I/O mapped I/O which uses separate instructions. Interrupts are an important method for asynchronous data transfer, where a device triggers an interrupt to signal the CPU. The CPU then services the interrupt request by saving context and jumping to an interrupt service routine before returning.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    30 views28 pages

    Microprocessor & Computer Architecture (Μpca) : I/O And Bus Architecture

    Uploaded by

    Pranathi Praveen
    The document discusses I/O and bus architecture. It describes how I/O devices connect to the CPU via an I/O bus and I/O controllers. There are two main methods for interfacing with I/O devices: memory mapped I/O which uses memory addresses to access devices, and I/O mapped I/O which uses separate instructions. Interrupts are an important method for asynchronous data transfer, where a device triggers an interrupt to signal the CPU. The CPU then services the interrupt request by saving context and jumping to an interrupt service routine before returning.

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    of 28

    Microprocessor & Computer

    Architecture (μpCA)
    I/O and Bus Architecture

    UE19CS252

    Session 4.5
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Introduction

    • The method that is used to transfer information between internal storage


    and external I/O devices is known as I/O interface.
    • A typical link between the processor , memory and several peripherals.
    • These devices work at varying speeds.
    • Ex: Monitors, Mouse, Keyboards, Video cameras, etc.,
    • Data transfer rate can either be regular or irregular.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Introduction

    CPU

    Cache

    Bus

    …
    Memory Disk Network USB DVD

    3
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – I/O Hierarchy

    CPU

    Cache

    Disk
    Memory Bus

    I/O
    Controller I/O Bus
    Memory

    …
    Network USB DVD

    4
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Intel Example

    P4
    Processor
    System bus 800 MHz, 604 GB/sec

    Memory 2.1 GB/sec Graphics output


    Main DDR 400 Controller
    Memory 3.2 GB/sec Hub
    (North Bridge) 266 MB/sec 1 Gb Ethernet

    266 MB/sec
    Serial ATA
    150 MB/s
    Disk CD/DVD
    100 MB/s
    I/O Tape
    Controller 100 MB/s
    USB 2.0 Hub
    60 MB/s (South Bridge)

    5
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Introduction
    • There exists special hardware components between CPU and peripherals to supervise
    and synchronize all the input and output transfers that are called interface units.
    • The I/O Bus consists of data lines, address lines and control lines.
    • The I/O bus from the processor is attached to all peripherals interface.
    • To communicate with a particular device, the processor places a device address on
    address lines.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Memory Mapped Device Interface

    • Memory Mapped I/O device interface:


    • Same address decoder selects memory and I/O ports.
    • Some memory address space is occupied by the I/O devices.
    • All data transfer instructions to / from memory an be used to
    transfer to/from I/O devices.
    • Processor need not have separate instructions for I/O.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - I/O Mapped device interface

    • I/O Mapped I/O device interface:


    • Separate instructions for I/O data transfer [ IN / OUT].
    • Processor signal identifies whether a generated address refers to
    memory or I/O device.
    • Separate address decoder for selecting memory and I/O ports.
    • Complete memory address space can be utilized.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Data Transfer Techniques

    • Data transfer to and from the peripherals may be done in


    any of these ways:
    1. Programmed I/O: CPU executes a program and that transfers data between I/O device
    and Memory

    a. Synchronous : Fixed rate of transfer


    b. Asynchronous : Handshaking – polling for sending /
    receiving the data
    c. Interrupt- Driven :( next slide)
    2. Direct memory access( DMA): An external controller directly transfers data between I/O
    device and Memory without CPU intervention.
    MPCA - I/o and Bus Architecture
    WHAT IS INTERRUPT/EXCEPTION?

    • Main ()
    • {
    Phone rings

    • : Can happen anytime


    Depends on types of interrupts
    • Doing something
    Phone rings _isr() // Interrupt service routine
    • (e.g. {
    • browsing)
    • : some tasks (e.g. answer
    telephone)
    • } ring
    } //when finished,
    //goes back to main
    MPCA - I/o and Bus Architecture
    INTERRUPTS
    MPCA - I/o and Bus Architecture
    DEVICES WITH SEPERATE INTR AND INTA LINES
    MPCA - I/o and Bus Architecture
    DAISY CHAIN
    MPCA - I/o and Bus Architecture
    Priority Interrupts
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – INTERRUPT/EXCEPTION?
    c. Interrupt- Driven:
    • CPU initiates the data transfer and proceeds to perform some other task.
    • When I/O module is ready for data transfer, it informs the CPU by activating a
    signal (Interrupt request).
    • The CPU suspends the task it was doing, services the request from the device and
    return back to the task it was doing.
    • Advantages:
    • CPU time is not wasted by polling the device
    • CPU time is required only during the data transfer plus some overheads for
    transferring and returning the control.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Data Transfer Techniques

    c. What happens when an interrupt request arrives?


    • At the end of the execution of the current instruction, PC and the status register contents are
    saved in the stack automatically.
    • Interrupt is acknowledged, interrupt vector is obtained based which the control transfers to the
    appropriate ISR.
    • After handling the interrupt, the ISR executes a special instruction return from interrupt(RTI).
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Data Transfer Techniques

    c. What happens when an interrupt request arrives?


    • At the end of the execution of the current instruction, PC and the status register contents are
    saved in the stack automatically.
    • Interrupt is acknowledged, interrupt vector is obtained based which the control transfers to the
    appropriate ISR.
    • After handling the interrupt, the ISR executes a special instruction return from interrupt(RTI).

    ARM Interrupt Vector Table


    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Interrupt request during the execution of an instruction.

    Accessing I/O Devices :


    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Multiple devices interrupting CPU

    • Common solution is to use a Priority Interrupt Controller.


    • Interrupt controller interacts with CPU on one side and multiple devices on the
    other side.
    • For simultaneous interrupt requests, interrupt priority is defined.

    • Interrupt controller is responsible for sending the interrupt vector to the CPU.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - How is interrupt nesting handled?
    Consider a scenario.
    • A device D0 has interrupted and the CPU is servicing the (executing the ISR) device D0.
    • In the meantime, device D1 has interrupted.
    • Two possible scenarios are here:
    1. D1 will interrupt the ISR for D0, get processed first, and then the ISR for device D0 will
    be resumed.
    This creates problem for multi nesting.
    2. Disable the interrupt system automatically whenever an interrupt is acknowledged.
    This will not require nested interrupts to be handled.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Polling Technique

    • Each device can have a status bit whether the device has interrupted?
    • CPU can poll the status bit to check for the device which has interrupted.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Daisy Chain Technique

    • In Daisy chain technique, INTR line is common to all the devices.


    • INTA line is connected in a daisy chain fashion [ as shown].
    • This allows to propagate serially through the devices.
    • A device when it receives INTA, passes the signal to the next device only if it has not
    interrupted.
    • Else, it stops the propagation of INTA and puts the identifying code on the data bus.
    • Thus the device that is electrically closest to the CPU will have the highest priority.
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Basic Interrupt Stack Design and Implementation


    Stack Layouts:
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices - Basic Interrupt Stack Design and Implementation
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Interrupt Handling Schemes Non-Nested Interrupt Handler


    Various stages in a NNIH –

    Enable Interrupts

    spsr ← spsr_{interrupt request mode}

    pc is restored
    MPCA - I/o and Bus Architecture
    Accessing I/O Devices – Interrupt Handling Schemes Non-Nested Interrupt Handler
    For Interrupts, I/O organization please refer to
    Carl Hamecher, Computer organization text book
    Chapter 4: Input output organization

    Difference between Memory mapped io and io mapped io


    Difference Between Memory mapped I/O and I/O mapped I/O (with compariosn
    chart) - Circuit Globe

    What is the Difference Between Memory Mapped IO and IO Mapped IO - Pediaa.Com

    Non-maskable interrupt – Wikipedia

    Difference Between Vectored And Non-Vectored Interrupts - Viva Differences


    THANK YOU

    Team MPCA
    Department of Computer Science and Engineering

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