Verilog Programming
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Wendell ObnascaVerilog Programming
Uploaded by
Wendell ObnascaVerilog Programming
module andgate (a,b,y);
input a,b;
output y;
Basic things to know. assign y = a & b;
endmodule
Module – fundamental building block for Verilog designs
This is the basic entity.
Used to construct design hierarchy
Cannot be nested (Means a module cannot be inside another module)
One circuit is represented by set of “modules” (Means module makes everything).
For an instance it can have a Gate, Register, ALU etc.
Module is Keyword. A name has to follow the term module.
Module andgatedemo
a,b and y are the ports (can be input or output)
A module has to be end with endmodule (just like for ( ) closure with [ ]).
module andgate (a,b,y);
input a,b;
output y;
How to declare a module? assign y = a & b;
endmodule
module module_name (module_port, module_port….);
Example: module full_adder (A,B,c_in, c_out,S);
module andgate (a,b,y);
input a,b;
output y;
How input/output declared? assign y = a & b;
endmodule
Input can be a scalar or a vector
input list of input identifiers;
Example: input A,B,c_in;
Output again can be a scalar or a vector
output c_out, 0V, MINUS;
output [7:0] ACC, REG_IN;
module andgate (a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
End module
endmodule – ends a module – not a statement
No “;”
It is like opening the loop and closing it to show the finish
module andgate (a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule
With Assign, inputs and outputs are connected via AND gate.
A ANDed with B and will be connected to Y.
Nothing is stored in this scenario and hence there is no need for a register at
all. In case we store, we need a register.
Test Bench
We need to test what we have written, right?
Yes, for that we have testbench. It is also Verilog code which will send the
inputs to the circuit to be tested. It is in a very simple way, a tester.
Things to remember – used in test bench
The wire is a net data type
A wire cannot store a value
Its value is determined by its driver, such as a gate, a module output or continuous
assignment
The reg is a variable data type
Can store a value from one assignment to the next
Used only in procedural blocks, such as the initial block
C:\iverilog\bin>iverilog -o AND_gate andgate.v andgate_tb.v
C:\iverilog\bin>vvp a.out Executable name module testbench
C:\iverilog\bin>vvp AND_gate
000
010
100
111