Applied Electronics II

1
 CHAPTER - 1
FEEDBACK AMPLIFIERS
o Introduction:
What do we mean by open loop systems? What about a feedback system?
• Open loop systems are systems which are open ended and no attempt is
made to compensate for changes in circuit conditions or load conditions
due to changes in circuit parameters such as gain and stability,
temperature, supply voltage variations and/or external disturbances.
• But the effect of these open loop variations can be eliminated or at least
considerably reduced by the introduction of feedback.
• Thus, feedback system is one in which the output signal is sampled and
then fed back to the input to form an error signal that drives the system.
• Feedback Systems are very useful and widely used in amplifier circuits,
oscillators, process control systems as well as other types of electronic
systems.
• Block diagram of the feedback system is shown below.

2
 Xi + Xo
Open loop
Xe gain(A)
𝑿𝒐 𝑨
+/-
=
Feedback
𝑿𝒊 𝟏± 𝑨 β
factor(β)

o This basic feedback loop of sensing, controlling and actuation is the main concept
behind a feedback control system and there are several good reasons why
feedback is applied and used in electronic circuits.
o There are two ways of “feeding back” the output to the input terminal namely:
I. Positive(regenerative) feedback: feedback signal is added to the input signal as
the feedback is in phase with the input.
- its effect is to increase the gain.
- the output quickly saturates b/c “more leads to more” and “less leads to less”.
II. Negative(degenerative) feedback: feedback signal is subtracted from the
input signal as the feedback is out of phase with the input.
- its effect is to reduce the gain.
- produces stable circuit responses because with negative feedback loops,
3
“more leads to less” and “less leads to more”.
2.1 CLASSIFICATION OF AMPLIFIERS:
a) Voltage amplifier: it is thevenin’s equivalent circuit @ its input and o/p.
a)
if Ri >> Rs  Vi ΞVs and
b) RL >> Ro  Vo=AvVi = AvVs
c)  thus for such type of amplifier,
output voltage is proportional to input
voltage, independent of the source
and load resistances, and hence the
name voltage amplifier.
 ideal voltage amplifier has Ri infinity
and Ro zero.
b) Current amplifier:  if amplifier input resistance is zero, then Ii = Is.
 if Ro  infinity, then IL = AiIi.
thus such type of amplifier provides an output current which is
proportional to the input current and is independent of source and output
resistance.  current amplifier.
4
 It has Norton's equivalent circuit at its input and output terminals.
 fig. Norton's equivalent circuit of current amplifier
c) Transconductance amplifier:
 here, output current is
proportional to input voltage
and proportionality factor is
independent of source and
output resistance values.
it has thevenin’s equivalent @ the input and Norton's equiv. @ the o/p.
 this type of amplifier is called transconductance amplifier.
 this amplifier has infinite input resistance, Ri and infinite output
resistance Ro.  Ri >> Rs and Ro >> RL.
5
 d)Trans-resistance amplifier:
here, the output voltage is
proportional to the input
current, independent of
source and output resistance
values.
It has Norton's equivalent at the input and thevenin’s equivalent at the o/p.
 Rs >> Ri and RL >> Ro.  trans-resistance amplifier.

Transfer ratio/ Gain

 It is the ratio of the output signal to the input signal.
 Av = V/Vi  voltage gain  transfer gain of basic amplifier
 Ai = I/Ii  current gain without feedback.
 Gm = I/Vi  trans-conductance  use of symbol A in the next
 Rm = V/Ii  trans-resistance section represents any one of
them.
6
 Amplifiers with feedback
o In the above section, we have seen different amplifier circuits with out feedback. In this section we
will see different amplifiers with feedback.
o Feedback connection has three networks.
I. Sampling network: to sample the output voltage or current.
II. Feedback network: to apply the sampled output to the input thr’ this two port network.
III. Mixer network: to combine the feedback signal with the input and the combined signal is fed to the
amplifier.

fig. block diagram of amplifier with feedback.

1) Sampling network: there are two ways to sample the output.

 Output voltage- is sampled by connecting the feedback network in shunt across the output.  called
voltage or node sampling.
 Output current – is sampled by connecting the feedback in series with the output.  called current or7
loop sampling.
2) Feedback network:
 It may consist of resistors, capacitors, inductors and so on.
 Provides reduced portion of the output as a feedback signal to the input mixer
network. It is given by:
Vf = βVo. Where β  0 to 1 is feedback factor or feedback ratio.
3) Mixer network: like sampling, there are two ways of mixing feedback signal with
input signal.
 Series (loop) input connection
 Shunt (node) input connection
the input and output variables can be modeled as either a voltage or a current. thus,
there are four basic classifications of single-loop feedback amplifiers in which the
output signal is fed back to the input.

8


Amplifiers with negative feedback: if feedback is subtracted from input signal.

fig 1. schematic representation of negative feedback amplifier

9
Advantages of negative feedback:
 Controls input and output impedances.
 Gain stability
 Increased bandwidth
 Reduced non linear distortion
 Reduced noise
Disadvantage of negative feedback:
 Reduce voltage gain by a factor of 1+ Aβ.
The four basic feedback topologies

fig a. voltage amplifier with voltage series feedback

10
 fig b. trans-conductance amplifier with current series feedback

Fig c. current amplifier with fig d. trans-resistance with voltage

current shunt feedback shunt feedback

11
 Gain with feedback:
 A – transfer gain of basic amplifier without feedback.
 Af– transfer gain of basic amplifier with feedback.
A = , Af = where, Xo  is output voltage or output current
Xi  input voltage or input current
Xs  source voltage or source current
 As it is a negative feedback, relationship b/n Xi and Xs is given by:
Xi = Xs – Xf ,  Xs = Xi + Xf., Xf- feedback voltage/current
 Af = , dividing by Xi to numerator and denominator, we get,
 Af= = but A =  open loop gain
= =  Af = where, β = = feedback factor
N.B. gain with feedback is smaller than gain without feedback.
 if |Af|< |A| - feedback is negative or degenerative
 If |Af| > |A| - positive or regenerative feedback

12
 Loop gain:
 The difference signal, Xd  multiplied by A in passing thr’ amplifier
multiplied by β in passing thr’ feedback ntwk multipied by -1 in the mixing
network/ difference network.
 This path makes a loop with gain of the loop = -βAwhich is called loop
gain or return ratio.
 The difference b/n unity and loop gain is called return difference, D.
D = 1+βA.
De-sensitivity of Gain:
• The transfer gain of the amplifier is not constant as it depends on factors
such as operating point, temperature etc.
• This lack of stability can be reduced by introducing negative feedback.
• We know that, Af =
• Differentiating both sides wrt A, =
dividing both sides by Af,

=
13
Where, is fractional change in amplification with feedback
is fractional change in amplification without feedback
 Thus, from the above equation, change in transfer gain with feedback is
less than gain without feedback by a factor of
 the fraction is called sensitivity of transfer gain.
 The desensitivity of gain is given by, D =1 + βA.
 If D increases, stability of amplifier increases.
i.e. if 1 <<βA, then Af = w/c is dependent only on the feedback network.
 Since A represents either AV , GM, AI or RM, Af represents the corresponding
transfer gain with feedback.
Avf= ……………… Voltage gain is stabilized.
 Gmf= ………….. Transconductance gain is stabilized
 RMf= ……………… Transresistance gain is stabilized
 AIf= ……………….. Current gain is stabilized

14
 Cut –off frequency with feedback:
 fLf = …….lower cut-off frequency with feedback
 fHf = ……… upper cut-off frequency with feedback
where, fL and fH are lower and upper cutt-off frequencies without feedback.

fig. effect of negative feedback on gain and bandwidth

15
 Input and Output resistances
1) Input resistance:
 if the feedback signal is added to the input in series with the applied
voltage regardless of the sampler network, then its input resistance
increases.
reason:Vf opposes Vs  Ii(input current) decreases.
thus, Rif = increases
 If the feedback is applied in shunt with the source regardless of the
sampling network, it decreases the input resistance.
reason: Is=If + Ii  Is increases with feedback
thus Rif = decreases.

fig. amplifier with series mixer fig. amplifier with shunt mixer. 16
Examples:
1) Voltage series feedback:-
2) N.B. Rif=

 Applying KVL to the input side,

Vs– IiRi –Vf =0
Vs = IiRi + Vf  Vs = IiRi + βVo …………(1)

Vo =  Av == …….this is true if Ro value is significant

output voltage is given by:

=> but most of the time, RL>> Ro.  Vo = . ……. (2) which is
open circuit voltage gain without feedback.
 Substitute equation (2) in (1);
Vs = IiRi + βAvVi = IiRi + βAvIiRi.
= Ii(Ri+ βAvRi) 17
Exercise: try to drive the formula for Rif for current series feedback in the
same way as the above. N.B. Rif = and make us of Io, GM, finally
Rif = Ri(1 + βGM)
2) Current-shunt feedback:
N.B. Rif =
 applying VCL to the input loop;
Is = I i + I f
Is = Ii + βIo. …… (1)

but Io = when current thr’ Ro is significant.

But most of the time Ro  infinity . This implies that Io= AvIi…… (2)
 Now substituting equation (2) in (1);
Is = Ii + βIo = Ii + βAiIi= Ii(1+ βAi)
now, Rif = ……………….. Because Ri =
Exercise: try to drive the formula for voltage shunt feedback.

18
 Output resistance:
 The negative feedback which samples the output voltage( i.e voltage
sampler), regardless of the mixer network tends to decrease the output
resistance.
 The negative feedback which samples the output current( i.e current
sampler), regardless of the mixer network tends to increase the output
resistance.

fig 1. voltage sampler fig 2. current sampler

1) Voltage series feedback:
 Ro – measured by setting Vs = 0 and disconnecting RL.
 Applying KVL to the output side, we get;
AvVi + IRo – V = 0
19
 I = …….. (1)
 the input voltage is given as;
Vi = -Vf = - βV …….. (2)
 Substituting equation (2) in (1),
I = = , ….. ButRof =
 Thus, rearranging the above equation,
Rof = which decreases with feedback
Exercise: for voltage shunt feedback, prove that Rof = .
2) Current shunt feedback:
 By open circuiting the input source, Is =0. and disconnecting the load.

20
 Apply KCL to the output node, we get:
…………………..(1)
 The input current is given as, = = βI……….(2)
 Substituting equation (2) in (1), we get:
 V = RoI( 1 + βAi)
thus, w/c increases with feedback
Exercise: prove that for current series feedback, .

21
 Summary of effects of negative feedback on amplifiers
parameters Voltage Current Current shunt Voltage shunt
series series
Gain with feedback decreases decreases decreases decreases
Stability improves improves improves improves
Frequency improves improves improves improves
response
Frequency reduces reduces reduces reduces
distortion
Noise and non reduces reduces reduces reduces
linear distortion
Input resistance increases increases decreases decreases
Output resistance decreases increases increases decreases

22
 Methods of identifying feedback topology and analysis of the feedback
amplifier
 Go through the following steps.
Step 1: identify topology (type of feedback)
a) to find the type of sampling network:
I. By shorting the output (i.e Vo = 0), if feedback signal, Xf becomes zero
it is voltage sampling
II. by opening the output loop (i.e Io=0), if the feedback signal becomes
zero  it is current sampling.
b) to find the type of mixing network:
III. If the feedback signal is subtracted from the externally applied signal as
a voltage in the input loop  it is series mixing.
IV. If it is subtracted as a current  shunt mixing.
 thus, by identifying the type of sampling and mixing networks, the type
of the feedback amplifier can be determined.
Step 2: find the input circuit
I. For voltage sampling, make Vo = 0 by shorting the output.
II. For current sampling, make Io = 0 by opening the output.
23
Step 3: find the output circuit
I. For series mixing, make Ii = 0 by opening the input loop
II. For shunt mixing make Vi = 0 by shorting the input.
 Steps 2 and 3 insures that the feedback is reduced to zero.
Step 4: replace each active device by its h-parameter model (optional).
Step 5: find the open loop gain(gain without feedback), A.
Step 6: indicate Xf and Xo on the ckt and evaluate β= Xf/Xo.
Step 7: from A and β, evaluate D, Af, Rif, Rof, e.t.c
Analysis of feedback amplifiers
1) Transistor Emitter Follower(voltage series feedback):
step 1: a) by shorting output voltage(Vo = 0) Vf
becomes zero  voltage sampler.
b) Vf is subtracted from Vs  series
mixing. Hence it is voltage series
feedback amplifier.

24
Steps 2 and 3:
 make Vo = 0 by shorting Re(Ro)  Vs appears in series with Rs between B
and E(input circuit) .
 Set Ii = Ib = 0, Re appears only in the output loop (output circuit)
Step 4: replace with h-parameter equivalent circuit.

fig 1. steps 2 and 3 fig 2. step 4

N.B. note the polarity of Vo in the h-parameter model.
Step 5 : find open loop voltage gain:
…………………….(1)
 Applying KVL to the input loop, we get;
……………………..(2)
 Substituting equation (2) in (1), we get:
25
Step 6: indicate Vo and Vf and calculate β.
….. b/c both are present on Re.
Step 7: calculate other parameters;
 D = 1 + βAv  Ri = Rs + hie
 Rif = Ri D
2) Voltage series feedback pair:
 the output of the 2nd stage is fed to
the input of the 1st stage through
feedback network in opposition to
the input signal Vs.
 step 1: it is voltage series amplifier.

Steps 2 and 3:

26
Step 4 : gain is multiplication of the two cascaded gains.
Step 5:
Step 6: find the other parameters
3) Current series feedback: common emitter configuration with
unbypassedRo.

open output loop Vf=0. thus
current sampler.
 looking at the circuit, Vf is
subtracted from Vs, thus series
mixing.

 Steps 2 and 3: 

27
Step 4: h-parameter equivalent circuit


= -0.015

Step 5: indicate Vo and Vf and calculate β.

 β=
Finally, calculate the remaining parts.

28
 Exercise: for the following circuits,
a) state topology with justification

fig 1 fig 2

Solutions:
for fig 1
 by opening the output loop at emitter of Q2(Io=0), feedback signal becomes zero.
current feedback.
 Is=Ii + If shunt mixer
For fig 2
 By shorting output voltage, feedback signal becomes zero  voltage sampler
 Is=Ii + If  shunt mixing

29
Exercises:
1) A feedback amplifier has open loop gain of 600 and feedback factor of
β=0.01. find closed loop gain with negative feedback.Ans:85.71
2) Distortion in an amplifier with negative feedback is found to be 3% when
feedback ratio is 0.04. when the feedback is removed , distortion
becomes 15%. Find the open and closed loop gains. (N.B. )
Ans: A = 100
3) An amplifier with open loop gain of is available.it is necessary to have an
amplifier whose voltage gain varies by not more than 0.2%. Calculate β
and Af. N.B. use ans: Af = 53.33
4) For the ff circuit,
hfe= 100, hie =1K, hre= hoe=0
Calculate:
RMf=Vo/Is, Avf=Vo/Vs, Rif
Ans: RMf=-8.031K , Avf=-8.03
Rif =901.5Ω

30
 Chapter 2
Differential amplifiers
1. Block diagram of an op-amp:

it has four cascaded blocks.

a) Input stage :
the main requirements of the input stage are.
 high voltage gain
 High input impedance
 Two input terminals
 Small input offset voltage
 Small input offset current
 High CMRR
 Low input bias current
2) Intermediate stage:
 Provides additional voltage gain
 It is a cascaded amplifiers called multistage amplifier.
31
3) Level shifting amplifier:
 Brings dc level down to ground potential, when no signal is applied at the
input terminal.
 Then the signal is fed to the last stage(output stage).
4) Output stage:
This supplies the load and provides low output impedance. the requirements
of good output stage are:
 Large output voltage swing capability
 Large output current swing capability.
 Low output impedance.
 Short circuit protection.
 Low power dissipation.

fig.1 block diagram of an op-amp

32
 Fundamentals of differential amplifier
Why differential ?  b/c it amplifies the difference voltage.
 Differential gain
 Common mode gain we will see it in the coming classes in
detail.
 CMRR

 Features of differential amplifier:

 High differential voltage gain
 Low common mode gain
 High CMRR
 Two input terminals
 High input impedance
 Large bandwidth
 Low offset voltage and offset current
 Low output impedance

33
 Transistorized differential amplifier
 It uses emitter biased identical circuits with identical characteristics.

 The two transistors have exactly matched characteristics.

 RC1 = RC2, RE1 = RE2, Vcc = -VEE,
 Such an amplifier is called emitter coupled differential amplifier.
 Let us study the circuit operations in two modes namely:
 differential mode of operation
 common mode opreration

34
 fig. dual input balanced output fig. differential mode of operation
differential amplifier
a) Differential mode:
 The two input signals are different from each other.
 assume the two input signals have same magnitude but out of phase by
1800.  use center tapped transformer as shown in the above figure.
 A positive going signal is applied on the base of Q1 and a negative going
signal is applied on base of Q2.
35
 Thus, Vs1 is +ve going  Vc1 is a –ve going and amplified version of Vs1,
 as Vs1 increases, current thr’ RE also increases  +ve going signal is
developed across RE.
 And Vs2 is –ve going  a Vc2 is +ve going and amplified version of Vs2.
 a –ve going signal develops across RE.
 Signal voltages across RE due to the effect of Q1 and Q2 are equal and
out-of-phase due to matched transistors  they sum up to zero  no
signal across the emitter resister.
 Vo is taken across the two collector terminals  these signal are equal in
magnitude and opposite in phase.  but Vo = Vc1 – Vc2, which is twice
the signal measured from either of the collector terminals to ground.
 This is differential mode.
Common mode of operation
 The two base voltages are equal in magnitude and phase  thus signals
at the emitter of the two transistors add up  this current across RE
produces negative feedback which reduces the common mode gain of the
differential amplifier.

36
 fig. common mode operation
Types of differential amplifiers
 It can be used in four different configurations.
 Dual input , balanced output differential amplifier.
 Dual input, unbalanced output differential amplifier.
 Single input, balanced output differential amplifier.
 Single input, unbalanced output differential amplifier.
 The differential amplifier uses two transistors in common emitter
configuration.
 Balanced (double ended) output: if the output is taken between the two
collector terminals. 37
 Unbalanced (single ended) output: if the output is taken between one
collector with respect to ground.
 Dual input: if signal is given to both the input terminals.
 Single input: if one of the input terminals is grounded.
N.B. out of these four configurations, the dual input, balanced output is the
basic differential amplifier configuration.
DC analysis of differential amplifier
 DC analysis means to obtain the operating point values, ICQ and VCEQ for the
transistors used.
 This is done by making the ac input signal zero and connecting each input
terminal to ground.
Assumptions:  RS1 = RS2 denoted by RS.
 The transistors Q1 and Q2 are matched transistors. So for a matched
transistor we have:
both transistors have the same characteristics
 RE1 = RE2 hence RE = RE1 || RE2
 RC1 = RC2 denoted by RC
 |VCC| = |VEE| and both are measured wrt ground. 38
  since the two transistors are
exactly matched, it is enough to
find the operating point values
( ICQ and VCEQ) for any one of
the two transistors.
 applying KVL to the base-emitter
loop, we have:
–IBRS –VBE –2IERE + VEE = 0
Ic = βIB, Ic = IE.
fig. DC equivalent circuit I B = IE/β…….substituting this,
 - IERS/β –VBE –2IERE + VEE = 0


where VBE = 0.6 – 0.7v for silicon transistor

= 0.2 for germanium transistor 39
 In practice, RS/β << RE

Thus,
 For the known value of VEE, RE determines the value of IE.
 IE is independent of collector resistance, Rc.
 Now, let us determine VCE.
since IC = IE,
VC = VCC – ICRC.
 Neglecting the drop across RS, VE = -VBE.

 hence , IC = IE = ICQ, and VCE =VCEQ for a given values of VCC and VEE.
N.B. In the above equation, the sign of VEE is already considered to be
negative while driving the formula. So to solve any problem using this
equation, use the magnitude of VEE only.
40
 Thus for both the transistors, we can determine the operating point values
as follows.

 Example: for the circuit shown below, calculate the operating point values.
VBE = 0.7V
ans: ICQ = 1.712 mA
VCEQ = 4.653 V
thus, Q point is:
(1.712mA , 4.653V)

41
 AC analysis of differential amplifiers using h-parameters
 here, we will calculate the differential gain, Ad, the common mode gain,
Ac, input resistance, Ri, and output resistance, Ro.
a) Differential Gain, Ad:
 For the differential calculation, the two input signals must be d/t from
each other.
 Let the two ac input signals be equal in magnitude & out of phase by
1800.
 The two emitter currents Ie1 & Ie2 are equal and out of phase  they cancel
each other. Thus, for the ac purpose, the emitter terminal can be
grounded.
 The ac small signal differential amplifier circuit with grounded emitter is
shown below.
 Assume that, VS1 = VS2 = VS/2.
 We will analyze the circuit using only
one transistor  half circuit concept
of analysis.

42
 the approximate hybrid model for the above circuit is shown below.

figure. approximate hybrid model

 Applying KVL to the input loop;


………………(1)

applying KVL to the output loop;

……………………..(2)

substituting equation (1) in (2), we get:

43


 The –ve sign indicates the phase difference between the input and the out
put terminals.
 Now the two input signals are equal in magnitude but out of phase.
 thus, VS1 = VS2 = VS/2  Vd = Vs1 – VS2 = VS/2 –(–VS/2) = VS.
 Hence, the magnitude of the differential gain, Ad is:

where, Vs is differential input.

N.B. this Ad is for circuit where the output is measured wrt ground. i.e .
Unbalanced output.
 Thus the gain for the balanced output is twice of the gain for unbalanced
output assuming that the two transistors are perfectly matched.

44
b) Common mode gain:
 Both input signals are equal in magnitude and are inphase.
 Thus, Vd = 0, Vc = average value of the two.

 Thus total current flowing through RE is 2Ie.

 After complex derivation(refer textbook) , we get:

N.B. the common mode gain, Ac, remains the same whether the output is
balanced or unbalanced.
c) CMRR:
 The expression for CMRR can be obtained from Ad and Ac.

45
 This CMRR is for dual input balanced output amplifier circuit.
d) Differential input impedance, Ri :
 It is the equivalent resistance b/n one of the input and the ground when
the other input terminal is grounded.
 Hence, Ri = Vs/Ib.
 But referring to equation (1), Ri can be written as:

 For one transistor and input pair, Ri = RS + hie. But for two input circuit, the
total input resistance is twice .
e) Output impedance, Ro :
 It is defined as the equivalent resistance between one of the output
terminals with respect to ground. thus,
46
Conclusion: summary for differential amplifier circuit configurations
 Dual input , balanced output
 Dual input, unbalanced output for all of them R o = Rc
 Single input, balanced output R in = 2(Rs + hie)
 Single input, unbalanced output

 Dual input , balanced output

 Single input, balanced output

 Dual input, unbalanced output

 Single input, unbalanced output

47
 Methods of Improving CMRR

• The higher the value of CMRR, the better is the performance of the
differential amplifier.
• Effect of RE :
- To improve the CMRR, the common mode gain, AC, must be reduced.
- The common mode gain approaches zero as RE tends to infinity.
- This is because RE introduces negative feedback in the common mode
operation which reduces the common mode gain, Ac.
- Thus, the higher the value of RE, the lower is the value of Ac and the
higher is the value of CMRR.
- The differential gain, Ad, is independent of RE.
• but practically RE can not be selected very high due to certain limitations
such as;
- Large RE requires high biasing voltage to set the operating Q point of the
transistor.
- This increases the overall chip area.
48
o Hence, practically instead of increasing RE, various other methods are used
which provide the effect of increased RE without any limitations. Such two
methods are given below.
I. Constant current bias method
II. Use of current mirror circuit.

Exercise: please try to examine the above two methods of increasing CMRR in
detail.

49
 Chapter 3
Operational Amplifier Basics
• What is an operational amplifier ?
 An Operational Amplifier (Op-Amp) is an integrated circuit that uses
external voltage to amplify the input through a very high gain.
• Why is it called operational ?
 b/c they were originally used to perform mathematical operations such as
adding, subtracting, integrating, differentiating signals …

v1

v2

a. without power supply b. with power supply

fig. op amp symbol 50
o basic circuit is made using a difference amplifier having two inputs (plus and
minus) and at least one output.
o the plus (+) input produces an output that is in phase with the signal
applied,
o while an input to the minus (-) input results in an opposite polarity output.
o the input signal applied between the two input terminals sees an input
impedance, Ri, typically very high.

o The output voltage , Vo = AdVd, is taken through an output impedance, Ro,

which is typically very low.
o we will use the ideal op amps characteristics to drive the formulas for
various practical circuits in the coming classes.

51
 Practical op amp
o Schematic representation of practical op amp and its ac equivalent circuit
are shown below.
Ro
V1
+
_

Vd Ri AV d Vo
+
V2 _

a. Practical op amp representation b. it’s ac equivalent circuit

 The above practical op amp has the following characteristics.
 a very high differential gain (open loop gain).
 high input impedance (negligible input current).
 low output impedance.
 High CMRR(Common Mode Rejection Ratio).
52
 Ideal OP AMP

Circuit model
(ideal)
a. Ideal op amp representation b. it’s ac equivalent circuit

 an ideal op amp has:

 Infinite input impedance( Ri open circuited).
 Zero output impedance(Ro is shorted).
 Infinite differential gain.
 Infinite CMRR.
53
o Finding Amplifier Gain:
i. Using Superposition theorem.
ii. Using Virtual ground concept

iii. Amplifier gain using superposition

 Let us take the following Op amp with feedback (inverting amplifier).
 Assume that the op amp used is ideal.
 Then drive the formula for the gain of the amplifier from its ac equivalent
circuit using super position theorem.

54
• Its ac equivalent circuit is shown below.

a) ac equivalent circuit

b) ideal op-amp equivalent circuit c) redraw equivalent circuit

55
 solving the circuit using superposition theorem,
i. For source V1 only (-AvVi set to zero):

ii. For source –AvVi (seting V1 to zero):

=> The total voltage is then:

=> solving for Vi,

56
• If Av >> 1, and AvR1 >> Rf, then:

Þ Solving for Vo/Vi , we get:

Þ And finally, the gain of an op-amp with a feedback resistor is:

 Now if Rf = R1  it voltage gain is unity

 If Rf is integer multiple of R1  constant gain amplifier

Note: we can also calculate this relationship using the virtual ground
concept as shown below.

57
 ii. Finding the amplifier gain using virtual ground concept:
 We have said that, Av is very large number and Vo = AvVi. thus, to obtain,
say for example 10 V, output voltage, we need very small input voltage, Vi.
 The value of Vi is very small and thus may be considered as 0-V.
 Thus Vi ≈ 0  the amplifier has a virtual ground( virtual short circuit) at the
input of the amplifier.
 There is no current flow through the virtual short circuit.

 Thus, we can write the equation for current as follows.

 Which can be re-arranged as;

58
 Common-Mode Operation
• Same voltage source is applied +
at both terminals
• Ideally, two input are equally
V o

amplified
• Output voltage is ideally zero
due to differential voltage is
V i ~
zero
• Practically, a small output
signal can still be measured Note for differential circuits:
Opposite inputs : highly amplified
Common inputs : slightly amplified
 Common-Mode Rejection

59
Common-Mode Rejection Ratio (CMRR)
Differential voltage input :
Noninverting
Vd V  V Input +
Output
Common voltage input : Inverting 
1 Input
Vc  (V  V )
2 Common-mode rejection ratio:
Ad A
Output voltage : CMRR  20 log10 d (dB)
Ac Ac
Vo  AdVd  AcVc
Note:
When Ad >> Ac or CMRR 
Ad : Differential gain
 Vo = AdVd
Ac : Common mode gain

60
 CMRR Example
What is the CMRR?

100V + 100V +
80600V 60700V
 
20V 40V
Solution :

Vd 1 100  20 80V Vd 2 100  40 60V

(1) (2)
100  20 100  40
Vc1  60V Vc 2  70V
2 2
From (1) Vo 80 Ad  60 Ac 80600V
From (2) Vo 60 Ad  70 Ac 60700V
Ad 1000 and Ac 10  CMRR 20 log(1000 / 10) 40dB

61
 practical op-amp circuits
 An op-amp can be connected in various connection types to provide
different characteristics.
1) Inverting amplifier:
 is the most commonly used constant gain amplifier circuit.
 Its gain depends on input and feedback resistor values (R1 and Rf).
 Output is inverted and amplified version of the input signal.

fig. inverting amplifier

62
Example: given that, the above figure has it’s parameter values as follows.
R1 = 100 kΩ, Rf = 500 kΩ, V1 = 2 V, then find Vo.
Solution:
Vo = -10 V

2) Non-inverting amplifier:
 here is the non-inverting amplifier circuit with its equivalent ac
representation.

fig. a) non-inverting amplifier b) ac equivalent circuit

63
 Clearly, the relation ship between the input and output voltages is given by:

 Re-arranging the equation gives:

Example: for the above non-inverting amplifier, find the output voltage given the
following parameters.
V1 = 2 V, Rf = 500 kΩ, R1 = 100 kΩ
Solution: Vo = + 12 V

3) Unity Follower(Buffer):
 Has unity gain with no phase reversal.
 The circuit operates like an emitter (source) follower.
 Used to isolate circuits or devices from one another and prevents undesired
interaction.

64
 fig. a) unity follower b) in it’s virtual ground equivalence

4) Summing Amplifier:
 Let us take a three input summing amplifier as shown below.
 Also called inverting adder.

fig. three input summing amplifier

65
 I1
I2
I3

b) virtual ground representation

 To drive the formula for Vo:
 find the total current It = I1 + I2 + I3 , N.B. Vi = 0 V.
 Find Io.
 Equate Io with It (Io = - It ).
 Finally solve for Vo.

 As the number of inputs increases, the gain of the amplifier decreases.

66
Example: find the output voltage of a summing amplifier for the following
sets of input parameters. Use Rf = 1 MΩ

Solution: Vo = -7 V
5) Integrator:
 This occurs when the feedback component used is a capacitor.

a) integrator circuit b) virtual ground connection

 The capacitive impedance of the capacitor is given by:

67
 Where s = jω is the Laplace notation.
 Now solving for Vo/V1 yields,

=>
 Rewriting the above equation in time domain:

 The integration operation is summing the area under a given waveform

over a given period of time.
example: if the input signal has fixed value, then the output voltage is a
ramp voltage with opposite polarity than the input and scaled
by a factor of 1/RC.
eg. For the following integrator circuit, draw the output waveform.

68
Solution:

a) 1 MΩ b) 100 k Ω
 The output voltage for 100 k Ω is more steeper than 1 M Ω.
 more than one input can be applied to an integrator with the resulting
output voltage in the form of the following.

fig. summing - integrator circuit

69
6) Differentiator:

fig. differentiator
 The resulting output voltage is given by:
 The scale factor is –RC.
 High frequency noise can produce a derivative whose magnitude is
comparable to that of the signal.
 Most of the time high pass filter is used to eliminate the noise.

70
 Op-amp specifications – DC offset parameters
 Ideally, when input voltage is zero, output voltage has to be zero as well.
But in practice there is some offset voltage at the output.
 This is because during manufacturing, the differential input transistors of
real op-amps may not be exactly matched.
 thus even though the external input sources are the same, there is an
output offset(error) voltage due to this input offset voltage.

This is the same as a voltage source connected

to the amplifier’s non-inverting input.

 Thus, taking the commonly used practical circuit , we will drive the
formula for Vo(offset).

71
 it is clear that the formula for the output offset voltage due to this input
offset voltage is given by:

OUTPUT OFFSET VOLTAGE DUE TO INPUT OFFSET CURRENT, IIO

 Output offset voltage also results due to any difference in DC bias currents
at both inputs still due to transistor mismatch.

and
 The compensating resistance Rc is approx. equal to R1. now taking the
total output offset voltage due to the two input currents, we get:
72
 b/c Rc =R1.

 But the main consideration is based on the input bias current, we define
IIO as;

 Thus, the formula for output offset voltage becomes as:

TOTAL OFFSET DUE TO VIO AND IIO

 Thus the total offset output voltage is due to the factors of the input offset
voltage and current. The absolute magnitude is used. 73
• Example: calculate the total offset voltage for the following circuit. The op-
amp specification lists VIO = 4mV, IIO = 150 nA.
Ans:
VO(offset total) = 479 mV

INPUT BIAS CURRENT, IIB

 And 

 you can determine the separate input bias currents using the specified
values of IIO and IIB using the above formulas.

74
 Op-amp specifications – frequency parameters
 An op-amp is designed to have a high gain, wide bandwidth amplifier.
 This operation tends to be unstable (oscillate)due to positive feedback.
 To insure stable operation op-amps are designed with internal
compensating circuitry, which also causes the very high open loop gain to
diminish with increasing frequency.
 This gain reduction is called roll-off.
 Example: the following figure illustrates the plot of gain vs frequency for a
typical op-amp.
 at low frequency down to DC operation,
the value of the gain is the one listed on
the manufacturers specification, AVD
which is typically very large.
 as frequency of the input signal increases,
the open loop gain drops off until it finally
reaches unity.
 N.B. AVD is the DC gain.
75
 The frequency at this gain value is specified by the manufacturer as a unity gain
bandwidth B1 which is the frequency at which the gain is 1.
 The frequency value at which gain value drops by 3 dB (to 0.707 of AVD)is called
cut-off frequency, fc.

• Example: Determine the cutoff frequency of an op-amp having specified values

B1 = 1 MHz and AVD =200 V/mV.
ans: 5Hz
Slew Rate, SR
 Slew rate = maximum rate at which amplifier output can change in volts per
microsecond (V/s)

 Example: For an op-amp having a slew rate of SR = 2 V/ɥs, what is the maximum
closed-loop voltage gain that can be used when the input signal varies by 0.5 V in
10 ɥs?
Ans: Vo = ACLVi and and finally, ACL= 40
76
 Commonly used Terms:
Linear versus non-linear circuits
a. Linear circuit: a circuit in which circuit
parameters ( resistance, capacitance,
inductance, waveform, frequency e.tc.)
are constant i.e. a circuit whose
Fig1. Linear circuit
parameters are not changed with
respect to current and/or voltage.
b. Non-linear circuit: a circuit whose
parameters vary (not constant) with
respect to current and voltage.

Fig2. Non-linear circuit

 Active versus passive circuit elements

a. Active elements: elements that generate(produce) energy in the form of
voltage or current. Example: Op-amps, transistor, batteries, generators etc.
- they supply energy to the circuit.
b. Passive elements: components that store or drop energy in the form of current
or voltage. Example: Capacitor, inductor, resistor.
-they take energy from the circuit. 77
 Op-amp applications
 As an active filter:
 Low pass filter
 High pass filter
 Band pass filter
 Band stop filter
 As a function generator( oscillators)
 Wien bridge oscillator
 RC phase shift oscillator
 LC oscillator
 As a comparator( Schmitt trigger):
 Square wave generator, example, in timers or clock.
 Triangular wave generator
 As voltage controlled oscillator(VCO):
 Non linear op amp applications:
 Active half wave rectifier
 Active peak detector
 Active clipper
 Active clamper
 Logarithmic amplifier 78
 Op-amp applications ----- cont’d
1. As an active filters:
 are formed with RC – circuits and op amps.
 Active filters are preferred to passive filters because:
- the inductors which are bulky and expensive at low critical
frequencies are estimated.
- they offer voltage gain. The signal never attenuates as it passes
the filter.
- they provide different response characteristics.
 Before going to the active filters, let us look at RC circuit low frequency
response.
VO
VO

HPF
LPF

79
 Looking at the HPF RC circuit, the output voltage is given by:

 At high frequency, Xc≈ 0 Ω thus, 
 At very low frequency, Xc≈ ∞ Ω, and hence .  Av=0.
 At (),

 Thus, the corresponding low frequency response of this RC circuit is

illustrated below.

AV----------------  at ,
------------
1
where,
fc = critical frequency
0.707

= cutoff frequency
= corner frequency
f
fc

80
 But, gain Av is given by:
 Now the magnitude of Av is given by:

 For
 Voltage gain roll off: is the rate of decrement in voltage gain with
frequency.
 Thus, the roll-off of
the RC circuit is
-20dB/decade.

1 0
2 -6
4 -12
10 -20
81
 here is the bode plot (gain in dB versus frequency).

fc
f
-3

-6

-12

-20

Av(dB)
No of RC circuits Roll-off(dB per decade)
1 -20
2 -40
3 -60
 Decade: a 10 times change in frequency.
82
a. Active low pass filter
I. First order(single pole) low pass filter
using single resistor and single capacitor.
 Has a practical slope of -20dB.
 Voltage gain below cutoff frequency
is constant ,
 Cutoff frequency,
Active Low Pass Filter

b.
a.
Fig. Low pass filter response a. practical b. ideal

83
II. Two pole( Sallen key) Low pass filter:
 Also called second order active filter.
 Formed by cascading two RC elements.
 Has -40dB/decade roll-off closer to ideal characteristics.
 Voltage gain and cutoff frequency are the same as first order active LPF.
 But the response drops at a faster rate for second order filter.

Fig. Active 2nd order(Sallen key) low pass Filter

N.B. N-Pole filter- contains N RC circuits.

84
b. Active high pass filters: R2

+V
C2 C1
+
vin
R1 vout
- Rf1
-V

Rf2
b.
a.
Fig. Active high pass Filters , a. 1st order b. 2nd order(Sallen key)
 Cutoff frequency , for both.
 Voltage gain above cutoff
frequency,

85
c. Active band pass filter:
 By cascading HPF and LPF.
 Two cutoff frequencies, namely, lower and upper cutoff frequencies.
 and .
 <

Fig. a. Active band pass Filters b. its response

86
 d. Active band stop(Notch) Filter:
 it is designed using HPF, LPF and a summing amplifier.

Low pass
filter

Summing
f1 amplifier

High pass 
filter
v in v out

f2

Fig. a. Block diagram of BSF b. example of Notch filter

87
Fig. Active Band stop filter response

88
  Cascading filters for greater roll-off rate:

 The roll-off rate of a filter is determined by its order.

 By cascading filters, the order can be increased and thus the response of
the filter can be improved.

Sallen key Sallen key

Vin Low(high) pass Low(high) pass Vout
filter filter

 A 4th order filter is formed by cascading two 2nd order filters.

Damping factor:
 Regardless of whether it is a LPF, HPF, BPF or BSF , the damping factor of
an active filter determines which response characteristic the filter exhibits.
 The DF is determined by the negative feedback circuit and is defined as;

89
 Vo
 The value of the DF designed to
produce a desired response
characteristic depends on the
order of the filter.
 For multiple stage filter, Fig. General form of an Active filter
the value of for each
stage is different.
 Values of DF for each section(stage) of a cascaded filter is obtained from
reference tables.

Examples:
1. design a 4-pole Butterworth LPF with 250Hz cutoff frequency.
use C = 220 nF
Note: DF for 1st section is 1.848 and for the 2nd section(stage) is 0.765.

90
2. Design a 2-pole butterworth BPF to have the critical frequency of 400Hz
and 4KHz. Note: DF for 2nd order active LPF and HPF is 1.414.

2. Non linear OP Amp applications:

a. As Active half wave rectifier:

 The high gain of the op amp eliminates the voltage drop on the diode.
Example: if A= 100,000 and VD= 0.7V, then the input that just turn on the
diode is .
 When , the diode turns on and the circuit acts as a voltage follower. The
effect of VD is reduced.
 Active half wave rectifiers enables us to rectify low amplitude signals.

91
b. As Active peak detector:
 A circuit whose output is the peak value of the input waveform.
 To peak-detect small amplitude signals.
 Vc= Vp(peak)

Vout

92
c. As Active Clipper:
 When Vin > Vref, the op amp output is negative and turns off the diode and
opens the loop. Thus, Vout = Vin.
 When Vin < Vref, the op amp output is positive which turns ON the diode.
Thus, Vout = Vref.

Exercise: modify the above circuit so as to be used as a positive clipper.

93
d. As Active Clamper:
 the 1st negative half cycle produces positive op amp output which turns
on the diode. This allows the capacitor to charge to approximately equal
to Vp with polarity shown.
 Beyond the negative peak, the diode turns off. This clamps the output
waveform up by Vp.
 This clamper can be used to clamp up or down very small amplitude
signals.

Fig. a. active positive clamper b. clamper output

Exercise: modify the above circuit for an active negative clamper.

94
3. As comparator:
 compares the input signals at the inverting and non inverting terminals of
the op amp and gives a rectangular output waveform accordingly.
 read more about it. Eg. Output bounding in comparators.
Exercise: read about Window Comparator.

4. As oscillators:
 See next chapter.

5. As VCO:
 Read ……….

95
 Chapter 4
Oscillators
Introduction:
 In the last chapter, we have seen amplifiers where negative feedback is
used.
 In this chapter we will see devices which works on the basis of positive
feedback.
Definition: oscillator is a circuit which basically acts as a generator ,
generating the output signal which oscillates with constant amplitude and
constant desired frequency. It does not require any input signal.
 In short, an oscillator is an amplifier, which uses a positive feedback and
with out any external input signal, generates an output waveform at a
desired frequency.
The concept of positive feedback

96
 Expression for gain with +ve feedback:
 Open loop gain:
 gain with feedback:
 For the above +ve feedback amplifier, ………………. (1)
 the feedback voltage is, ………………(2)
 Substituting equation (2) in (1);

substituting this for Afand dividing by Vi;

 thus, without an input, the output starts to oscillate whose frequency

depends up on the feedback network or the amplifier or both. Such a
circuit is called oscillator.
 Note that, the feedback is a friction of the output, so β< 1, thus the
feedback network is an attenuation network.
 To start with the oscillation, Aβ>1.

97
 But the network adjusts itself to Aβ=1, while working as an oscillator.
BARKHAUSEN CRITERION

fig. basic block diagram of oscillator circuit

 consider a fictitious voltage Vi applied at the input of the amplifier , we
get,
 The feedback signal is ,
 For the oscillator feedback must derive the amplifier and hence Vf must
act as Vi. From the above equation, Vf is sufficient to act as Vi when
||=1. and phase of Vf should be same as Vi.
98
 Thus Barkhausen criterion states that:
1) The total phase shift around the loop is precisely 0 0 or 3600.
2) The magnitude of the product of the open loop gain of the amplifier and the
feedback factor is unity.
 Satisfying these two conditions, the circuit works as an oscillator producing
sustained oscillations of constant frequency and amplitude.
 In reality no input signal is required to start the oscillation. Aβ is made greater
than 1 to start the oscillation and the circuit adjusts it self to get ||=1 , finally
resulting in to self sustained oscillation.
 ||=1  sustained oscillation
 ||>1 growing oscillation
 ||<1 decaying oscillation
Starting voltage:
 We have said that, no external supply voltage is required to start oscillation. So
how does the oscillator start oscillation ? Where does the starting voltage come
from ?
Ans: every resistance has some free electrons. Under the influence of normal room
temperatures, these free electrons move randomly in various directions . This
generates a voltage called noise voltage.  when the above two conditions meet,  it
is amplified the part of the output signal is sufficient to drive the input of the 99
amplifier circuit. It adjusts itself to ||=1 and sustained oscillation.
 Classification of oscillators:
1) Based on output wave form:
sinusoidal oscillators: gives pure sinusoidal output
non-sinusoidal oscillators: gives output as triangular, square, saw tooth,…
2) Based on circuit components used:
RC oscillators: if resistor and capacitor components are used. They are used
at low(audio) frequency range.
LC oscillators: if inductor and capacitor are used.  used at high frequency
range.
 Crystal oscillators
3)Based on range of operating frequencies
 low(audio) frequency oscillators- if they generate oscillations at
low(audio) frequency level. i.e. 20Hz – 200kHz
 High frequency oscillators- from 200kHz up to gigahertz frequency range
1) RC PHASE SHIFT OSCILLATORS:
 Contains resistors and capacitors in its feedback network arranged in a
ladder fashion.
 Let us take the RC ladder circuit shown below.
100
 Taking a single RC circuit from the above,
 and since C and R are in series
…total impedance
 assume the r.m.s input voltage is Vi volts. Hence the current is given by ;

the input voltage by 𝜙, the out put voltage also leads the input
 The output voltage , , is in phase with the current. Thus, as the current leads

voltage by 𝜙.
N.B. by using proper values of R&C, the angle 𝜙 is adjusted in practice to
600 , as required by RC phase shift oscillator.

101
 Thus, the feedback will introduce a phase shift of 1800 to obtain a total phase

 Thus, three cascaded RC circuits with 𝜙=600 each will give a total of
shift of 3600, as required by oscillators.

1800 phase shift across the feedback.

 Feedback network is also called ladder network.
a) Phase shift oscillator using op-amp
 Op-amp in inverting mode, and Aβis slightly greater than 1 to start oscillation.

 To drive the value of β, let us consider the feedback network.

 we are also going to find the frequency value at which the circuit oscillates as
well as the minimum value of the inverting amplifier to start oscillation.
102
 Applying KVL to the various loops,
We get;
….......(1)
….. (2)
…………(3)
 re-arranging in matrix form and solving these equations, we obtain the values
of βand f as follows.
 and 
now, to have the oscillations, |Aβ|>=1.
Thus, 
Note: to start oscillation, the gain of the op-amp must be equal to or greater than
29, which can be adjusted by using Rf and Ri.
Exercise: try to examine the transistorized phase shift oscillator.
 minimum value of hfe = 44.54 which is required to start oscillation.
frequency of oscillation , which is the same as using an op-amp.

103
 Advantages of RC phase shift oscillator:
 The circuit is simple to design
 Can produce output over audio frequency range.
 Produces sinusoidal output waveform.
 It is fixed frequency oscillator
Disadvantage of RC phase shift oscillator
 Frequency of oscillator is changed by changing values of R and C. but the RC
values of all three sections must be changed simultaneously to satisfy the
oscillating condition, which is practically impossible.  fixed frequency
oscillator.
Exercise: try to illustrate the phase shift oscillator using FET transistor and come up
with the formulas for |A| and |β|.
2)Wien Bridge oscillator:
 It uses a non-inverting amplifier.
 Thus, the feedback network does not bring a phase shift.
 It can be implemented using op-amp or BJT transistor.

104
 The basic circuit of Wien bridge oscillator is shown below.
 Using this circuit, let us drive the formulas
for β and f.
 The input to the feedback is at terminals
1 and 3 while the output is at terminals
2 and 4.
 Let us see the feedback network in detail.
the two arms of the bridge, namely R1 , C1 and
R2, C2 are called frequency sensitive arms, b/c
the components of the two arms determines
the frequency of the oscillator.
 such feedback network is called lead-lag
network, b/c at low frequency, it acts like a
lead while at high frequency, it acts like a lag.

Derivation for frequency of oscillation:

and

105

 thus,
 Substituting the values of Z1 and Z2 in the
above equation for βand simplifying the result,
we get the values of β and fas follows.
 
 If R1=R2=R and C1=C2=C,

 the gain of the feedback network is ,  positive sign indicates 00 phase shift.
This equation is true only if R1=R2 and C1=C2.
 gain of the amplifier for oscillation is:
|Aβ|
The general formula for β and A is;
and

106
a) Wien Bridge oscillator using op-amp:

 Gain of the op-amp is adjusted using R3 and R4.

 According to the oscillating condition, . thus , this ratio provides sufficient loop
gain for the circuit to oscillate at the frequency calculated as:

Example: determine if the above circuit with R3=6k Ω, R4= 2k Ω, R=5.1kΩ and
C=0.001ɥF works as an oscillator or not. If yes, determine the frequency of
oscillation. Ans: A=4 >3 yes, and f =31.2kHz
107
 Comparison of RC phase shift and Wien bridge oscillators

RC phase shift oscillator Wien Bridge oscillator

1 Used for low frequency range Used for low frequency range
2 The feedback network is Rc network The feedback network is lead-lag network
with three RC sections called Wien bridge circuit
3 The feedback network introduces Feedback Does not introduce any phase
1800 phase shift shift
4 Amplifier circuit introduces 1800 Amplifier does not introduce phase shift
phase shift
5 The frequency of oscillation is The frequency of oscillation is

6 The amplifier gain condition is |A| The amplifier gain condition is |A|

7 Frequency variation is difficult Frequency variation is possible by varying

the two capacitors on a common shaft and
varying their values.

108
 Tuned(LC) oscillator circuits:
 Oscillators that uses L and C to produce oscillation.
 The circuit that using L and C is called tank(oscillatory) circuit.
 Used for high frequency range  from 200kHz up to few gigahertz.
 These oscillators are used for sources of RF(radio frequency) due to high
frequency.
Operation of LC tank circuit:
 Capacitor initially charges from
external DC source, thus electro-
static energy is stored in the capacitor.
 Now, C starts to discharge  current fig. initial charging fig. LC tank ckt
starts to flow through L magnetic field gets setup in the inductor when
capacitor fully discharges, electrostatic energy is stored as magnetic energy in
the inductor. at this time, as per Lenz's law, this starts charging the capacitor
in opposite polarity making the lower plate of the capacitor +++ until it is fully
charged.
 In such a way the process repeats resulting in oscillatory current damped
oscillation, where there is loss of energy during energy transfer from C to L and
from L to C.
109
 To make the damped oscillation un-damped (sustained), the amplifier supplies
the loss of energy at proper time.
 The frequency of oscillation obtained by this LC tank circuit is given by:
where, L is in henries and C is in farads
Basic form of LC oscillator circuit:
 It has amplifier stage such as op-amp, BJT, FET…
 The LC tank circuit contains Z1,Z2 and Z3 which
are either capacitive or inductive impedances.
 Assume that the input impedance of the
amplifier is infinity. (op-amp or FET).
 Now replacing this with its linear equivalent
circuit;
 From this circuit,
, where ZL=(Z1+Z3)||Z2. thus
 and
 the –ve sign inverting

110
 Condition for oscillation is but we know the values of A and β from the above
equations. Thus, substituting and solving we get,
where,
N.B. Z=jX
 According to the barkhausen criterion, must be positive and greater or equal to
1. since Av is +ve, will be positive only if both X1 and X2 have same sign. this is
true only if X1 and X2 have same reactance.(i.e. both capacitive or inductive).
 To have phase shift of 00,  X3 must be inductive if X1 and X2 are capacitive or X3
must be capacitive if X1 and X2 are inductive.
Summary

111
 1) Hartley oscillator:

fig 1. using op-amp fig 2. using BJT transistor

 The amplifier gives 1800 phase shift. Thus, the tank circuit gives additional 1800
phase shift.
 Going through a some procedure, we get the formula s as :
………….frequency of oscillation
 At this frequency , the value of hfe can be determined. ,which is value of hfe to
satisfy oscillation conditions.
112
 Now, let is the equivalent inductance of L1& L2 connected in series. Then, the
formula for the resonance frequency is given by:

 In practice, L1& L2 may be wound on a single core so that there exists a mutual
inductance b/n them denoted by M.
 In such cases, the equivalent inductance is determined as;
, and (for BJT transistor amplifier)
Note: if L1& L2 assists each other, the sign of M is +ve, otherwise it is –ve.
 If the amplifier used is op-amp, it’s gain will be;
.
 if mutual inductance exists in between them (wound on a single core),

Example: in a Hartley oscillator, if L1=20ɥH, L2=2mH and C is variable. Find the

range of C if frequency is to be varied from 1 MHz to 2.5 MHz. Neglect mutual
inductance.
Ans: C must vary from 2.0244 pF up to 12.6525 pF

113
 Colpitts oscillator:
 An LC oscillator that uses two capacitive reactances and one inductive
reactance at it’s feedback.
 Both Amplifier and tank circuit introduces 1800 phase shift.

fig 1. using op-amp fig 2. colpitts oscillator using BJT transistor

 Looking at the transistorized colpitts oscillator, hfeIb is used as a source to the
tank circuit while Ib acts as an out put current from the tank circuit.
 RFC(radio frequency choke) at the collector of BJT- has high reactance for high
frequency signal (open circuit) and low reactance for dc supply (short circuit).
114
 The frequency at which the oscillator oscillates is given by;
where, is equivalent capacitance
of C1& C2 in series.
 For BJT transistorized colpitts oscillator,
 For colpitts oscillator using an op-amp, the gain of the amplifier is
Example: design the value of an inductor to be used in colpitts oscillator to
generate a frequency of 10MHz. The circuit uses a value of C1=100pF and C2=50pF.
Ans: L = 7.6 ɥH
Clapp oscillator:
 It is modification of colpitts oscillator to achieve frequency stability.
 Here, capacitor C3 is added in series with L to the tank circuit of colpitts
oscillator as shown below.
N.B. the value of C3 is much smaller than C1 and C2.
thus, CeqΞ C3.
is the equivalent capacitance in series.

115
 And . But since C3 is smaller than C1& C2, CeqΞ C3.
Therefore, which depends only C3.
 now, across C3, there is no transistor parameter (i.e. hfe is independent of C3)
hence stable frequency.
Advantages:
 The frequency is stable and accurate.
 The stray capacitances have no effect on C3 which decides the frequency.
 Keeping C3 variable, the frequency of oscillation can be varied to the desired
value.
Exercise: read about tuned collector oscillator and come up with the formulas.
Factors affecting the frequency stability
1. Change in values of inductors and capacitors of tank circuit due to change in
temperature.
2. Change in parameters of active devices used like FET & BJT due to change in
temperature which in turn affects frequency.
3. Variation in power supply.
4. Change s in atmospheric condition, aging and unstable transistor parameters
116
5. The changes in the load connected affects the effective resistance of tank ckt.
6. The capacitive effect in transistor and stray capacitances affect the capacitance
of the tank circuit and hence the frequency.
Exercise: try to read ways of improving stability of oscillators.
3) Crystal oscillators:
 it is a tuned-circuit oscillator using piezoelectric crystal as its tank circuit.
 This is used when high frequency stability is required. Thus, the crystals are
used in watches, communication transmitters and receivers e.t.c.
 Piezoelectric effect means to generate voltage across the faces of the crystal
under the influence of mechanical pressure(force).
 Every crystal has its own resonating frequency.
 Examples are quartz, Rochelle salt, tourmaline
CM- mounting capacitance – when
there is no mechanical
vibration.

fig1. symbolic representation fig2. ac equivalent circuit

117
 The equation for the resonant frequency fr is;
 But most of the time , quality factor is very large.
thus,
 Series and parallel resonance:
a) Series resonance: when the reactances of the series RLC leg are equal(Xc=XL).
 The impedance offered by this branch at resonance is minimum which is R.
 The series resonance frequency is given by:
b) Parallel resonance: when the reactances of the series leg are equal to the
reactance of the mounting capacitor CM.
 Under this condition, the impedance offered by the crystal to the external
circuit is maximum.
 Here, and the parallel resonant frequency is given by;

118
 When C is very smaller than CM,then fsΞ fp=fr. there is one resonant frequency.
 Due to good frequency stability, it is used in
computers, counters, basic timing devices in
electronic wrist watches e.t.c.

fig. frequency versus crystal impedance

Pierce crystal oscillator:
 Is modified version of the colpitts oscillator by replacing the inductor in the
tank circuit by crystal.
 The crystal behaves like inductor for frequency slightly higher than the series
resonant frequency fs.
 the basic working principle is the same as colpitts oscillator.
 The practical transistorised pierce crystal oscillator circuit is shown below.

119
 resistances R1, R2 and RE provides d.c. bias.
 CE emitter bypass capacitor
 RFC(radio frequency choke)-provides
isolation b/n d.c. and a.c. operation.
 CC1 & CC2 –coupling capacitors
 The resulting circuit frequency is set by
the series resonant frequency of the crystal.
 Change in supply voltage, temperature,
transistor parameters have no effect on the
circuit operating conditions fig. pierce crystal oscillator
i.e. good frequency stability is obtained.
 The base-collector (gate-drain in case of FET) junction is reverse biased and
there exists an internal capacitance which is dominant at high frequencies.
 Thus, this oscillator circuit can be modified by using internal capacitors of the
transistor instead of C1 and C2.(C1 & C2 are not required).
 Such circuit using FET and transistor are shown below.

120
 fig a. using FET fig b. using transistor
 Similar to the modifications of colpitts oscillator, the Hartley oscillator can be
modified to get Millers crystal oscillator circuit.
 One of the inductors in the tank circuit of the Hartley oscillator is replaced by a
crystal which acts as inductor for frequencies slightly greater than the series
resonant frequency.

fig. Miller crystal oscillator

121
 Example: a crystal with L=0.4 H, C= 0.085 pF, CM = 1pF, and R =5kΩ find;
a) series resonant frequency …………..0.856 MHz
b)parallel resonant frequency………….0.899 MHz
c) by what percent does the parallel resonant frequency exceed the series
resonant frequency……………….
d) find the Q-factor of the crystal…………………..
Amplitude stabilization:
 The oscillator output amplitude if not stabilized, attains the extreme levels of
saturation i.e. This can cause distortion in the output waveform.
 Thus, it is necessary to minimize distortion and reduce the output amplitude to
the acceptable range.
 We use oscillator amplitude stabilization circuit.
 It makes oscillation damped(not sustained) if amplitude increases beyond a
particular value.

122
when the output is below some
acceptable level( not enough to
forward bias the diodes), the gain
is which is high.

 when output amplitude exceeds

some acceptable level, it makes the
diodes D3 and D4 forward bias.
R3 gets shorted. Gain decreases.

 thus, amplitude stabilization

operatesby ensuring that oscillation is not sustained if the output exceeds a
predetermined value. i.e the oscillator becomes a self-controlling circuit.

123
 Chapter- 5
Multivibrators and Wave shaping circuits
• Multivibrator :- is a circuit designed to have zero, one or two stable output
states. It is a wave shaping circuit.
• There are three types of multi-vibrators:
 Astable(Free running Multivibrator)
 Monostable( or One shot)
 Bistable (or Flip Flop)
a. Astable ( Free Running Multivibrator):
 A switching circuit that has no stable output state.
 The astable multivibrator is a rectangular-wave oscillator.

124
b. Monostable Multivibrator:
 A switching circuit with one stable output state.
 Also referred to as a one-shot.
 The one-shot produces a single output pulse when it receives a valid input
trigger signal.

c. Bistable Multivibrator ( also called Flip Flop):

 A switching circuit with two stable output states.
 The output changes state when it receives a valid input trigger signal, and
remains in that state until another valid trigger signal is received.

125
 Comparators
• it accepts inputs of linear Voltages and provides
a digital output.
• The output voltage stays at the high voltage
level when the non inverting input is greater
than the voltage at the inverting input.
• it then goes to the lower voltage level when
the non-inverting input voltage goes below
the inverting input voltage.
• Assume that the inverting input is grounded and voltage signal , Vi, is applied at
the non-inverting input.
• For the given input Vi, a corresponding
digital output signal is generated as
as shown in the figure.

+Vsat, if Vi > 0v
• Vout =
-Vsat, if Vi <0v 126
• Exercise: for the following two configurations, the reference voltage is
connected to the inverting and non-inverting inputs respectively. In each of
the two connections, at what condition does the LED turned ON?

fig 1 fig 2

N.B. Vref = 6v

127
 Schmitt Trigger using OP-AMP
• Two types:
 Inverting Schmitt trigger.
 Non-inverting Schmitt Trigger.

• Inverting Schmitt Trigger:

 here, the input signal is applied to the inverting terminal.
 Feedback network is achieved using resistors R1 and R2 as shown below.

fig a. Inverting Schmitt trigger

128
• The voltage V+ is related to the output voltage Voby the simple voltage divider
formed by resistors R1and R2.

• As V+ depends on Vo, Vo also depends on the difference between V+ and V-.

• To analyze the circuit, let us assume an initial condition. The possible values
Vo can take are VH and VL where VH> VL , also assume that VL <0.
• By assuming that the initial state of Vo is VH, then:
H

• And the output is:

• Now from the above equation for Vo, as long as Vin< the output will remain
at VH.
• The transition from VH to VL will occur when Vin>.

129
• This part of operation is shown in the figure-1 below where H .
• When Vin > VTU, Vo= VL and L.
• Now let us see what happens when Vin starts decreasing. In order for the
transition to happen again the term ( )has to change sign. This will happen
when Vin<. Where VTL = .
• For this part, the voltage transfer operation is shown in figure-2 below.

fig-1 fig-2

130
• The complete voltage transfer characteristic is obtained by combining the
above two figures as shown below.

fig. voltage transfer characteristics of inverting Schmitt trigger.

NOTE: in the above figure,

 VTU (or UTP) – upper triggering voltage upper and lower
 VTL (or LTP) – lower triggering voltage triggering points.

131
 Non-inverting Schmitt Trigger
• When the input is applied to the non-inverting terminal as shown below, it is
called non-inverting schmitt trigger.

• The voltage V +at the non-inverting terminal is a combination of the output

voltage, V o , and the input voltage, Vin.
• Now drive the formula for V+ using superposition theorem, you get:

• Since and V_= 0, the transition will occur when V+ crosses zero.

132
, where VT is the transition(triggering ) voltage.

• Let us assume that the initial state Vo = VL. Then .

• Since VL< 0, is positive and we call it (upper triggering voltage). The
corresponding part of the characteristic plot is shown in fig-1 below.
• Now the output is at VHand will stay at this state until the voltage V +crosses
zero. This will happen at the transition voltage VT which must satisfy . This is
the lower transition voltage VTL given by :

• The characteristic plot for this part is shown in fig-2 below.

figure-1 figure-2
133
• The complete voltage characteristics is shown below.

NOTE: in the above figure:

 VTU (or UTP) – upper triggering voltage upper and lower
 VTL (or LTP) – lower triggering voltage triggering points.

134
 Application of Schmitt Trigger:
A. Schmitt trigger for comparator chattering: chattering is defined as
production of multiple output transitions as the input signal swings through
the threshold region of the comparator.
• this happens due to the fact that ac noise is present in practical circuits.
• The following shows input signal with ac noise and how comparator output
chatters.

• This problem is eliminated by using schmitt trigger. This is because they

exhibit hysteresis.

135
• By making hysteresis width greater than the maximum peak amplitude of the
noise, a dead zone is created such that noise with in this zone no longer causes
multiple output transitions.

B. Schmitt trigger in ON/OFF controllers: in ON/OFF controllers, such as

Temperature controller, when temperature is below set-point, heater is made
ON and when it is above set-point, heater is made OFF. But if comparator is
136
used, heater will turn ON and OFF many times, which is not desirable.
 Wave Shaping Circuits
Introduction:
 Capacitors and inductors have the ability to store energy in the form of
electric and magnetic fields respectively.
 A capacitor consists of two electrodes separated by an insulating material
called dielectric.
 In a linear capacitor(when their values are time invariant), the electric
charge q on the electrode is proportional to the voltage across the
capacitors. i.e.
Current through capacitor:
 Current is the rate of change of an electric charge.
i.e , C = time invariant constant(capacitance)
 The reference polarities of the voltage v(t) and the direction of the current
i(t) are as shown below.

 Note that when the voltage across the capacitor is constant, dv/dt =0. and
i(t) is zero. For DC voltage, current through capacitor is zero.
137
 Given the current through the capacitor, the voltage across it is given by:

 If the voltage at some instant of time t=to is v(to), the above equation leads
to :

 Frequently, the voltage across the capacitor is known at the beginning of

the time of observing its response i.e. t=0. thus the equation becomes:

 If it is initially uncharged v(0)=0.

Voltage and current through Inductor:
 For inductor:
 The voltage due to electromagnetic self induction is given by:
 If the voltage across the inductor is given, the current is
 If the current at time t=to is i(to), then

138
Sinusoidal sources:
 Sinusoïdal voltage &currentsources produce voltages/currentthat vary
sinusoidally with time.
 We can express the sinusoidal function of a voltage or current source as
either a sine or a cosine function. The cosine function is commonly used.
 Thus: , where is the phase angle of the sinusoid and
 Note: The quantity (ωt) is always expressed in radians, but the phase
angle is usually (almost always!) expressed in degrees, not radians!

The Phasor:
 A phasoris a complex numberthat carries the amplitude and phase angle
information of a sinusoidal function.
 This concept comes from Euler’s identity which relates the exponential
function to the trigonometric function:
.
thus,

139
 Since we use the cosine function in analyzing steady state sinusoidal
circuits, then:

 Note that in the above, is a complex number that carries the amplitude
and phase angle information of the sinusoidal function. (The term gives
only the time-varying behavior).
 Thus, is the phasor representation(phasor transform) of the sinusoidal
function [ i.e. } ]
 Thus, +𝜙
𝑽𝝓 𝒎 𝑽 𝒎 𝒔𝒊𝒏𝝓
Polar form Rectangular form
𝑽 𝒎𝒄𝒐𝒔 𝝓
V-I relationship for Resistor, Inductor and Capacitor
a. For Resistor:
 If the current through R is ,
Then 𝒊
140
 Converting the above formula to phasor form, we get:
, where V and I are in phasor representations.
both are in-phase.
b. For Inductor:
 Still assume that the current through the inductor is:
,
 Then,

 Converting to cosine function, we get:

 Converting to phasorform:
 This is equivalent to the following:

finally, where V and I are in phasor forms.

is in rectangular form

141
 If we wish to represent in s-domain, go through the following steps.
 For an inductor, we know that
 Now taking the Laplace transform on both sides and remembering the
operational transform of derivatives , we get:

or

. ForCapacitor:
 Again, assume that the voltage across the capacitor is given by:

 Then, current i(t) through the capacitor is :

 Again converting to cosine function,
 The phasor representation is:

142
 Finally, , where I and V are in phasor forms.

 Therefore,

 Again, if you want to represent it in s-domain, you will obtain the

following equation:

where, sC is an admittance
 Finally, rearranging the above equation, we get:
where, Vo is initial voltage stored in the capacitor

143
 In general,
 s-domain:
 𝛚-domain:

Frequency-Selective Circuits (Filters):

 When the radian frequency, 𝛚, is variable.
 There are generally four kinds of filters:

I. Low-pass– Circuits that permit all electronic signals below a certain

frequency to be transmitted past their outputs.
II. High-pass– Circuits that permit all electronic signals above a certain
frequency to be transmitted past their outputs.
III. Band pass – Circuits that allow all electronic signals between two
frequencies (or in a frequency band) to be transmitted past their
outputs.
IV. Band-stop– Circuits that allow all electronic signals above and below a
frequency band to be transmitted past their outputs.
144
 One term that is very important with respect to filters: the cutoff
frequency. It is defined as follows:
o In a low-pass filter- the frequency above which signals are attenuated.
o In a high-pass filter- the frequency below which signals are attenuated.
 Both band-pass and band-stop filters have two cutoff frequencies.
o In a band-pass filter- signals are attenuated both below the lower cutoff
frequency, and above the higher cutoff frequency.
o In a band-stop filter- signals are attenuated between the lower and higher
cutoff frequencies.
 In the last chapter, we have seen what active filters are. Here we will see
passive filters.
 Passive filters are made with simple passive circuit components (resistors,
inductors, and capacitors). They generally produce gradual signal
attenuation with frequency and reduce the overall signal in the passband
somewhat (since they have no amplification).

145
 a. Low pass Filters:
 Passive low-pass filters are generally either series RL or series RC circuits.
i. The series RL circuit as Low pass filter:
 Consider how this circuit behaves when ω
is very low. In this case, the reactance of the
inductor  0, and the output voltage V0 is the
same as the source voltage.
 Now consider the voltage V0 as the radian
frequency, ω increases. For large ω, the inductive Fig. RL low pass filter
impedance will become very large compared to R. Then V0 will  0.
 Also noticed that as ω  0, then the phase angle will approach 0 (with only
a resistive load, voltage and current are in phase).
 On the other hand, as ω  ∞, the full load begins to look like a completely
inductive load (>>R), so that the phase angle approaches −90°.
 In the graphs shown below, the cutoff frequency, ωC, is indicated by the
dotted line. How do we compute ωC?

146
 𝜭
A

A(j𝛚)

 Defining the cutoff frequency:

o Engineers define the cutoff frequency as the point where the transfer
function magnitude is equal to ( ) of its maximum value:

o At this point, the signal is ~ 70.7% of its maximum value.

 Laplace transfer analysis of the RL filter:
o By transforming the above circuit to its s-domain
we obtain the following circuit.

Fig. RL low pass filter 147

o The output voltage is given by:

o now, the transfer function is given by:

o Now by setting s=j𝛚 , we can transfer back to 𝛚-domain.

o Thus, and
o Now consider the behavior of and as a function of 𝛚.

148
• As ω0, |A(jω)|1, and θ(jω)0°. Thus the circuit “passes” low-frequency
signals completely. But
• As ω∞, |A(jω)|0, and θ(jω)−90°. At sufficiently high frequencies, the

o Now , we know that at 𝛚c:

signal is completely attenuated.

or
o Re-arranging the above equation, we get the following
formula.
------------->

Example:
a. design RL low pass filter which has a cutoff frequency of
10Hz.
b. Then compute the output voltage at 1, 10, and 60 Hz.
N.B. choose L = 100mH. Ans: R = 6.28Ω and |Vo|= 99%, 71% and
10% of |Vi|
149
 ii. The Series RC Circuit as Low-Pass Filter:
o Similar to the above RL circuit, we will drive the formula for the transfer
function of the lowpass RC circuit shown below.

o And finally, it can be expressed as:

o Again, the magnitude of the transfer gain in 𝛚-domain is given by:

Fig. RC low pass filter

150
o Again at cutoff frequency, |A(j𝛚)|=
o where,
o Thus at cutoff frequency , or

o Simplifying the above equation, we get:

o Example: specify a low pass RC filter with . Choose C = 1μF.

ans: R= 53.05 Ω

151
Summary:
 the two standard passive low-pass filters are:

𝑅 1
𝐿 𝑹 𝑅𝐶 1
𝐴 ( 𝑠 )= , 𝝎 𝒄= 𝐴 ( 𝑠 )= , 𝛚𝑐=
𝑠+( )
𝑅
𝐿
𝑳
𝑠+ (
𝑅𝐶
1
) 𝑅𝐶

 Not that the general formula for the transfer ratio, A, for either circuit is:

 Other common relationships: τ, the time constant for both filter circuits
is equal to the reciprocal of the cutoff frequency. That is;

152
 b. High pass filters:

o If 𝛚  ∞,
I. The Series RC circuit as High Pass filter:

o however, if

o Again, we can analyze the circuit as we have done before.

we get:

Then converting it to 𝛚-domain.

153
o finally, we express the transfer gain and phase shift as;
.
o To solve for the cutoff frequency, we know that

o Therefore, is the cutoff frequency, regardless of whether the RC circuit is

a low- or high-pass filter.

II. The series RL circuit as a high pass filter:

o Likewise, we can arrange an RL filter
as a high-pass filter:
o Solving as before, we will find that:

o Finally,

154
Summary:
o the two standard passive high pass filters are:

𝑠 𝑹 𝑠 1
𝐴 ( 𝑠 )= , 𝝎 𝒄= 𝐴 ( 𝑠 )= , 𝛚𝑐=
𝑠+( )
𝑅
𝐿
𝑳
(
𝑠+
1
𝑅𝐶 ) 𝑅𝐶

o Again, not that the general formula for the transfer function, A, for either
circuit is:
, where for high pass RL filter and
for high pass RC filter.
Exercises:
1. A series high-pass RL filter has R=15KΩ, L=3.5 mH. Calculate the cutoff
frequency.

155
2. A series RL low-pass filter is needed with fC=2000Hz. The chosen resistor
is 5 KΩ. Find L, the absolute value of the transfer function at 50 KHz, and
the phase angle at 50 KHz.
3. A series RC high-pass filter has C=1μF. Find the cutoff frequency for R
values of 100, 5000, and 30,000 Ω.

Series RLC circuits:

o Before we proceed to series RLC, let us see some characteristics of a
bandpass filter.
o Some characteristics of bandpass filter:
 The lower and upper cutoff frequencies are related to the
center(resonant) frequency, , by the formula:

 At the transfer function of the filter circuit is real (no complex

component).
 The bandwidth of the filter is given by: . Note that β is often expressed
in Hz.

156
 Series RLC Bandpass filter:
o now, let us continue to the series RLC circuit. Consider the following
simple RLC circuit.
o Clearly, as the capacitor behaves
like an open circuit, so .
o Just as clearly, as , the inductor
in the circuit will create essentially an
“open circuit,” so that once again,
o There is some center frequency band where Ais > 0 and therefore the
output signal is > 0. Thus:

o Multiplying the numerator and denominator by we get:

o and, letting s=jω we get the following.
o and finally

157
o Now calculate the remaining parameters as follows:
i. Center(resonant) frequency, ω0: At ω0, the transfer function is real. Then

 At ,. Check it pls.
ii. Cutoff frequencies: we now that at and |A|=. So
solving this and eliminating the negative
frequencies you will get.

158
iii. Bandwidth, β :

iv. Quality factor, Q:

o Note that we can also write the formulas for the cutoff frequencies in
terms of the center frequency and the bandwidth. That is:
o Exercise: express the formulas for cutoff frequency in terms of Q.
o Example: Design a graphic equalizer audio bandpasscircuit with fC1 = 1KHz
and fC2 = 10 KHz. Choose C=1μF.
Solution: , then
mHz.

159
• Exercise: for the above series RLC circuit if C= 0.1 μF Find L and R for
ωO= 2π(12,000) and Q=6.ans: L=1.67 mH , R=22.1Ω

Band-Reject or Band-Stop Filters:

o These filters are characterized by the same parameters as the
bandpassfilters: ωC1, ωC2,ωO, β, and Q.
o Again, two of the five must be specified. The others are then defined by
the various relations that we will develop below, as we did for the
bandpassfilter.
o Consider the circuit to the left, in the ω domain.
 as , , and the output
voltage equals the input voltage.
 As , , and once again, 𝑉 𝑜 (𝛚 )
the output is essentially the same as
-
the input.
 In between these limits, the impedances of the L and C will be much
smaller, so that the output may only be a fraction of the input. Thus there
is a central “stop” band.
160
o Moreover, at the resonant frequency, , we will have :

o At , |A(j𝛚)|=0. solving we get:

• Exercise:
1. Please drive the formula for the other parameters of this band stop filter,
such as .
2. Read about parallel RLC circuits and come up with similar analysis as
before.

161
 Chapter six
Introduction to Digital Electronics
6.1. Realization of logic gates using FETs:
o The following chart shows the major IC technologies and logic-circuit
families that are currently in use.

o ECL-Emitter Coupled Logic, BiCMOS - combination of BJT and CMOS.

o CMOS technology is the most dominant of all the IC technologies available
for digital-circuit design.
o We will concentrate with the study of CMOS digital logic circuits.

162
o Some of the reasons for CMOS displacing bipolar technology in digital
applications are as follows:
i. CMOS logic circuits dissipate much less power than bipolar logic circuits and thus one
can pack more CMOS circuits on a chip than is possible with bipolar circuits.

ii. The high input impedance of the MOS transistor allows the designer to use charge
storage as a means for the temporary storage of information in both logic and memory
circuits. This technique cannot be used in bipolar circuits.

iii. The feature size (i.e., minimum channel length) of the MOS transistor has decreased
dramatically over the years, with some recently reported designs utilizing channel
lengths as short as 0.06 ɥm. This permits very tight circuit packing and,
correspondingly, very high levels of integration.
o To start with, let us see the following two types of MOSFETs.

163
o Biasing of the two MOSFETs is given below.

𝐃
𝐒
𝐆 𝐆𝐒
𝐃
Fig 1. An N-channel Enhancement type
Fig 1. An P-channel Enhancement type MOSFET with and applied, And
MOSFET with and applied, And directions of current flows.
directions of current flows.

CMOS lOGIC-GATE CIRCUITS

o The CMOS logic gate consists of two networks:
 the pull-down network (PDN) constructed of NMOS transistors, and
 the pull-up network (PUN) constructed of PMOS transistors.
o The two networks are operated by the input variables, in a complementary
fashion.

164
o Thus, for the three-input gate represented in the following fig, the PDN
will conduct for all input combinations that require a low output (Y = 0)
and will then pull the output node down to ground, causing a zero voltage
to appear at the output, = O. Simultaneously, the PUN will be off, and no
direct dc path will exist between and ground.
o On the other hand, all input combinations that call for a high output (Y = 1
) will cause the PUN to conduct, and the PUN will then pull the output
node up to , establishing an output voltage = • Simultaneously, the PDN
will be cut off, and again, no de current path between VDD and ground
will exist in the circuit.

165
o Example: An Inverter:

Fig . a)the CMOS inverter b) its representation as a pair of

switches operated in a complementary fashion.
o the PDN comprises NMOS transistor, and since the NMOS transistor
conducts when the signal at its gate is high, the PDN conducts.
o In a dual manner, the PUN comprises PMOS transistor, and a PMOS
transistor conducts when the input signal at its gate is low; thus the PUN is
activated when the inputs are low.

166
o Examples of pull down networks are given below.

o And the following are examples of pull-up networks.

167
 More Logic-Gate circuits
1. The Two-Input NOR Gate: 2. two input NAND Gate:

Exercise: draw the 3-input NOR and 3-input NAND gates.

168
3. The Exclusive-OR function:
 the complate X-OR realization is given below:
……PUN

……PDN

169
o Example: A more complex Gate: consider the following.

o now, obtain the PUN and PNDs.

PDN…………

PUN ……….. = ……… check it.

o Finally, the complete

realization is:

170
 Summary of the Synthesis Method

1. The PDN can be most directly synthesized by expressing Y as a function of

the un-complemented variables. If complemented variables appear in this
expression, additional inverters will be required to generate them.
2. The PUN can be most directly synthesized by expressing Y as a function of
the complemented variables and then applying the un-complemented
variables to the gates of the. PMOS transistors. If un-complemented
variables appear in the expression, additional inverters will be needed.
3. The PDN can be obtained from the PUN (and vice versa) using the duality
property.

171
Thank You &
Good Luck !!!
172