Skip to content

Commit a02b1a8

Browse files
bors[bot]David-OConnoradamgreig
authored
Merge #580
580: L4 and WB fixes r=adamgreig a=David-OConnor Fixes #555, #563, #565, #567, #570, #572, and #575. See #578; "unrecoverable" git errors. Not currently working: - Last 3 (by address) added L412 RTC regs are not adding - WB HSEM and IPCC renamed regs are not changing - BCDR field added to USB Removed the L4x2 `USB_FS` rename to `USB`: the RM calls it `USB_FS`. Previous justification, from a code comment: > we call the resulting peripheral `USB` instead of `USB-FS` to be aligned with `mvirkkunen/stm32f103-usb` The *peripheral* is called `USB`; the interrupt is called `USB_FS`. Co-authored-by: David O'Connor <david.alan.oconnor@gmail.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
2 parents 6be86d6 + 9537a15 commit a02b1a8

File tree

7 files changed

+604
-136
lines changed

7 files changed

+604
-136
lines changed

‎devices/common_patches/stm32l4x2_l412.yaml

Lines changed: 132 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
# Common patches and includes for L4x2 and L412.
2+
3+
# SVD incorrectly labels APB1ENR1 bit 18 as USART1EN instead of USART3EN.
4+
# SVD incorrectly labels APB1ENR1 bit 26 as USBF instead of USBFSEN.
5+
# SVD incorrectly labels APB1ENR1 bit 14 as SPI1EN instead of SPI2EN.
6+
# SVD incorrectly omits APB1ENR1 bit 1 (TIM3RST), which is present for
7+
# STM32L45xx and STM32L46xx devices.
8+
RCC:
9+
APB1ENR1:
10+
_modify:
11+
USART1EN:
12+
name: USART3EN
13+
description: USART3 clock enable
14+
USBF:
15+
name: USBFSEN
16+
description: USB FS clock enable
17+
SPI1EN:
18+
name: SPI2EN
19+
description: SPI2 clock enable
20+
APB1RSTR1:
21+
_modify:
22+
USART1RST:
23+
name: USART3RST
24+
description: USART3 reset
25+
_add:
26+
TIM3RST:
27+
description: TIM3 timer reset
28+
bitOffset: 1
29+
bitWidth: 1
30+
access: read-write
31+
32+
_modify:
33+
USB_SRAM:
34+
name: USB
35+
# without quotes, get less readable value 1073768448
36+
baseAddress: "0x40006800"
37+
38+
# The SVD calls ADC1 ADC.
39+
ADC:
40+
name: ADC1
41+
42+
ADC1:
43+
_modify:
44+
_interrupts:
45+
ADC1:
46+
name: ADC1_2
47+
48+
_add:
49+
ADC2:
50+
derivedFrom: ADC1
51+
baseAddress: "0x50040100"
52+
53+
USB:
54+
_add:
55+
_interrupts:
56+
USB_FS:
57+
description: USB event interrupt through EXTI
58+
value: 67
59+
60+
_delete:
61+
- USB_FS
62+
63+
# Merge the thousands of individal bit fields into a single field for each
64+
# CAN filter register. This is not only much easier to use but also saves
65+
# a huge amount of filespace and compilation time etc -- as much as 30% of all
66+
# fields in many devices are just these CAN filter bank fields.
67+
"CAN*":
68+
"F?R?":
69+
_merge:
70+
- "FB*"
71+
"F??R?":
72+
_merge:
73+
- "FB*"
74+
75+
# TIM3 is 16-bit, whilst TIM2 is 32-bit
76+
_copy:
77+
TIM3:
78+
from: TIM2
79+
80+
# NB: Paths here are relative to the common_patches directory.
81+
_include:
82+
- 4_nvic_prio_bits.yaml
83+
- merge_USART_CR1_DEATx_fields.yaml
84+
- merge_USART_CR2_ADDx_fields.yaml
85+
- merge_USART_CR2_ABRMODx_fields.yaml
86+
- merge_USART_CR1_DEDTx_fields.yaml
87+
- rename_USART_CR2_DATAINV_field.yaml
88+
- merge_LPUART_CR1_DEATx_fields.yaml
89+
- merge_LPUART_CR1_DEDTx_fields.yaml
90+
- rename_LPUART_CR2_DATAINV_field.yaml
91+
- merge_LPUART_CR2_ADDx_fields.yaml
92+
- merge_USART_BRR_fields.yaml
93+
- can/can.yaml
94+
- can/can_filter_bank.yaml
95+
- ../../peripherals/can/can.yaml
96+
- sai/sai_v1.yaml
97+
- dfsdm/dfsdm_v2.yaml
98+
- ../../peripherals/gpio/gpio_v2.yaml
99+
- crc/crc_rename_init.yaml
100+
- ../../peripherals/crc/crc_advanced.yaml
101+
- ../../peripherals/crc/crc_idr_8bit.yaml
102+
- ../../peripherals/crc/crc_with_polysize.yaml
103+
- ../../peripherals/wwdg/wwdg.yaml
104+
- ../../peripherals/rcc/rcc_l4.yaml
105+
- tim/common.yaml
106+
- ../../peripherals/tim/tim_basic.yaml
107+
- ../../peripherals/tim/tim16.yaml
108+
- ../../peripherals/tim/tim6.yaml
109+
- ../../peripherals/tim/tim2345_mixed.yaml
110+
- tim/tim2345_mixed_l.yaml
111+
- ../../peripherals/tim/tim_advanced.yaml
112+
- tim/tim_ccr.yaml
113+
- tim/v2/l4.yaml
114+
- ../../peripherals/tim/v2/ccm.yaml
115+
- ../../peripherals/dma/dma_v1_with_remapping.yaml
116+
- ../../peripherals/iwdg/iwdg_with_WINR.yaml
117+
- ../../peripherals/exti/exti.yaml
118+
- ../../peripherals/i2c/i2c_v2.yaml
119+
- ../../peripherals/usart/lpuart_v2A.yaml
120+
- ../../peripherals/usart/usart_v2B2.yaml
121+
- rtc/rtc_cr.yaml
122+
- tsc/tsc.yaml
123+
- fpu_interrupt.yaml
124+
- ../../peripherals/usb/usb_array.yaml
125+
- ../../peripherals/usb/usb_with_LPM.yaml
126+
- flash/flash_boot0s.yaml
127+
- ../../peripherals/sai/sai.yaml
128+
- l4_adc_common.yaml
129+
- l4_adc_smpr.yaml
130+
- l4_adc_sqr1.yaml
131+
- l4_spi.yaml
132+
- ../../peripherals/spi/spi_l4.yaml

‎devices/stm32l412.yaml

Lines changed: 231 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,231 @@
1+
# This SVD is a copy+paste of l4x2's.
2+
_svd: ../svd/stm32l412.svd
3+
4+
# This module is the same as l4x2, but with the RTC peripheral from L5 and G4.
5+
# Applies to L412 and L422 MCUs. Note that the RM (RM0394) includes two separate
6+
# RTC chapters: One that applies to L41x and L42x (Chapter 34), and one that
7+
# applies to the rest. (Chapter 36). This module includes the Chapter 34 RTC setup.
8+
9+
# TR, DR, PRER, WPR, TSSSR, SHIFTR, TSTR, TSDR, ALRMASSR,registers unchanged.
10+
# old CR at new address, and some fields added
11+
# WUTR has an additional WUTOCLR field.
12+
# CR has additional fields.
13+
# CALR, SSR, SHIFTR, ALRMAR and ALRMBR, ALRMASSR, ALRMBSSR at a diff address.
14+
# CALR has an added field.
15+
# ISR, TAMPCR, OR, BKP0R, and BKP31R removed.
16+
# SCR, MISR, SR, ICSR added
17+
18+
RTC:
19+
_delete:
20+
- ISR
21+
- TAMPCR
22+
- OR
23+
- BKP*R
24+
25+
_modify:
26+
SSR:
27+
addressOffset: 0x08
28+
29+
CR:
30+
addressOffset: 0x18
31+
32+
CALR:
33+
addressOffset: 0x28
34+
35+
SHIFTR:
36+
addressOffset: 0x2c
37+
38+
ALRMAR:
39+
addressOffset: 0x40
40+
41+
ALRMBR:
42+
addressOffset: 0x48
43+
44+
ALRMBSSR:
45+
addressOffset: 0x4c
46+
47+
WUTR:
48+
_add:
49+
WUTOCLR:
50+
description: Wakeup auto-reload output clear value
51+
bitOffset: 16
52+
bitWidth: 16
53+
access: read-write
54+
55+
CALR:
56+
_add:
57+
LPCAL:
58+
description: Calibration low-power mode
59+
bitOffset: 12
60+
bitWidth: 1
61+
access: read-write
62+
63+
CR:
64+
_add:
65+
TAMPTS:
66+
description: Activate timestamp on tamper detection event
67+
bitOffset: 25
68+
bitWidth: 1
69+
access: read-write
70+
TAMPOE:
71+
description: Tamper detection output enable on TAMPALRM
72+
bitOffset: 26
73+
bitWidth: 1
74+
access: read-write
75+
TAMPALRM_PU:
76+
description: TAMPALRM pull-up enable
77+
bitOffset: 29
78+
bitWidth: 1
79+
access: read-write
80+
TAMPALRM_TYPE:
81+
description: TAMPALRM output type
82+
bitOffset: 30
83+
bitWidth: 1
84+
access: read-write
85+
OUT2EN:
86+
description: RTC_OUT2 output enable
87+
bitOffset: 31
88+
bitWidth: 1
89+
access: read-write
90+
91+
_add:
92+
ICSR:
93+
description: RTC initialization control and status register
94+
addressOffset: 0x0c
95+
size: 0x20
96+
access: read-write
97+
resetValue: 0x00000007
98+
fields:
99+
WUTWF:
100+
description: Wakeup timer write flag
101+
bitOffset: 2
102+
bitWidth: 1
103+
access: read-only
104+
SHPF:
105+
description: Shift operation pending
106+
bitOffset: 3
107+
bitWidth: 1
108+
access: read-only
109+
INITS:
110+
description: Initialization status flag
111+
bitOffset: 4
112+
bitWidth: 1
113+
access: read-only
114+
RSF:
115+
description: Registers synchronization flag
116+
bitOffset: 5
117+
bitWidth: 1
118+
INITF:
119+
description: Initialization flag
120+
bitOffset: 6
121+
bitWidth: 1
122+
access: read-only
123+
INIT:
124+
description: Initialization mode
125+
bitOffset: 7
126+
bitWidth: 1
127+
RECALPF:
128+
description: Recalibration pending Flag
129+
bitOffset: 16
130+
bitWidth: 1
131+
access: read-only
132+
133+
SR:
134+
description: RTC status register
135+
addressOffset: 0x50
136+
size: 0x20
137+
access: read-only
138+
resetValue: 0x00000000
139+
fields:
140+
ALRAF:
141+
description: Alarm A flag
142+
bitOffset: 0
143+
bitWidth: 1
144+
ALRBF:
145+
description: Alarm B flag
146+
bitOffset: 1
147+
bitWidth: 1
148+
WUTF:
149+
description: Wakeup timer flag
150+
bitOffset: 2
151+
bitWidth: 1
152+
TSF:
153+
description: Timestamp flag
154+
bitOffset: 3
155+
bitWidth: 1
156+
TSOVF:
157+
description: Timestamp overflow flag
158+
bitOffset: 4
159+
bitWidth: 1
160+
ITSF:
161+
description: Internal timestamp flag
162+
bitOffset: 5
163+
bitWidth: 1
164+
165+
MISR:
166+
description: RTC masked interrupt status register
167+
addressOffset: 0x54
168+
size: 0x20
169+
access: read-only
170+
resetValue: 0x00000000
171+
fields:
172+
ALRAMF:
173+
description: Alarm A masked flag
174+
bitOffset: 0
175+
bitWidth: 1
176+
ALRBMF:
177+
description: Alarm B masked flag
178+
bitOffset: 1
179+
bitWidth: 1
180+
WUTMF:
181+
description: Wakeup timer masked flag
182+
bitOffset: 2
183+
bitWidth: 1
184+
TSMF:
185+
description: Timestamp masked flag
186+
bitOffset: 3
187+
bitWidth: 1
188+
TSOVMF:
189+
description: Timestamp overflow masked flag
190+
bitOffset: 4
191+
bitWidth: 1
192+
ITSMF:
193+
description: Internal timestamp masked flag
194+
bitOffset: 5
195+
bitWidth: 1
196+
197+
SCR:
198+
description: RTC status clear register
199+
addressOffset: 0x5c
200+
size: 0x20
201+
access: write-only
202+
resetValue: 0x00000000
203+
fields:
204+
CALRAF:
205+
description: Clear alarm A flag
206+
bitOffset: 0
207+
bitWidth: 1
208+
CALRBF:
209+
description: Clear alarm B flag
210+
bitOffset: 1
211+
bitWidth: 1
212+
CWUTF:
213+
description: Clear wakeup timer flag
214+
bitOffset: 2
215+
bitWidth: 1
216+
CTSF:
217+
description: Clear timestamp flag
218+
bitOffset: 3
219+
bitWidth: 1
220+
CTSOVF:
221+
description: Clear timestamp overflow flag
222+
bitOffset: 4
223+
bitWidth: 1
224+
CITSF:
225+
description: Clear internal timestamp flag
226+
bitOffset: 5
227+
bitWidth: 1
228+
229+
# Most of the other patches for this device are common with the L4x2 device.
230+
_include:
231+
- ./common_patches/stm32l4x2_l412.yaml

0 commit comments

Comments
 (0)