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L41x and L42x use diff RTC regs #555

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David-OConnor opened this issue May 23, 2021 · 2 comments · Fixed by #580
Closed

L41x and L42x use diff RTC regs #555

David-OConnor opened this issue May 23, 2021 · 2 comments · Fixed by #580

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@David-OConnor
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David-OConnor commented May 23, 2021 •
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L4 PAC RTC doesn't work on 41x and 42x. Distinction is on 3rd digit. RM has sep RTC sections. PAC only uses 43+ one. CR is on a diff address, so this is fundamentally incompatible.

I'm not sure how to address this: The PAC split on 3rd digit works for most other periphs. Probably add 2 sep RTC modules, like how the RM has 2 sep chapters.

My best thought on an approach: Use two separate RTC modules, in the vein of how the RM splits it up into 2 chapters.
@David-OConnor
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David-OConnor commented May 24, 2021 •
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Here's what the top of my take on the l41x / l42x module looks like, verified working on hardware:

#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - time register"]
    pub tr: TR,
    #[doc = "0x04 - date register"]
    pub dr: DR,
    #[doc = "0x08 - sub second register"]
    pub ssr: SSR,
    #[doc = "0x0c - initialization and status register"]
    pub isr: ISR,
    #[doc = "0x10 - prescaler register"]
    pub prer: PRER,
    #[doc = "0x14 - wakeup timer register"]
    pub wutr: WUTR,
    #[doc = "0x18 - control register"]
    pub cr: CR,
    _reserved6: [u8; 8usize],
    #[doc = "0x24 - write protection register"]
    pub wpr: WPR,
    #[doc = "0x28 - calibration register"]
    pub calr: CALR,
    #[doc = "0x2c - shift control register"]
    pub shiftr: SHIFTR,
    #[doc = "0x30 - time stamp time register"]
    pub tstr: TSTR,
    #[doc = "0x34 - time stamp date register"]
    pub tsdr: TSDR,
    #[doc = "0x38 - timestamp sub second register"]
    pub tsssr: TSSSR,
    _reserved1: [u8; 4usize],
    #[doc = "0x40 - alarm A register"]
    pub alrmar: ALRMAR,
    #[doc = "0x44 - alarm A sub second register"]
    pub alrmassr: ALRMASSR,
    #[doc = "0x48 - alarm B register"]
    pub alrmbr: ALRMBR,
    #[doc = "0x4c - alarm B sub second register"]
    pub alrmbssr: ALRMBSSR,
    #[doc = "0x50 - status register"]
    pub sr: SR,
    #[doc = "0x54 - masked interrupt status register"]
    pub misr: MISR,
    _reserved2: [u8; 4usize],
    #[doc = "0x5c - status clear register"]
    pub scr: SCR,
}

RM 0394. Chapter 34 is the RTC variant not currently supported by PAC. Chapter 36 is the one currently supported.

edit: Note that this is like newer variants, eg L5, and G. Ie, the first reserved 8 bytes is for security stuff on L5. Here's a G4 variant that's almost identical to L41x

@David-OConnor
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David-OConnor commented Jun 16, 2021 •
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It looks like the only L41x and L42x variants that exist (with relevance to the SVD and RM breakdown) is 412 and 422. So, we could do this by adding 1 module, called L412. It would be the same as L4x2, but with the RTC copy+pasted from L5 (minus security regs), or G4 (with a reg rename or 2).

This was referenced Jun 18, 2021
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