Fault Injection

This paper presents a fault injection platform that is currently developed and used to perform soft-error dependability analysis and hardening of complex SoCs. Primarily, it is oriented toward safety analysis, safety requirement conformance testing and hardening of complex SoCs. This platform makes use of clusters of hardware emulation resources available for SoC verification to achieve massive faults injection capabilities. It is able to distribute fault injection campaigns across multiple heterogeneous emulation platforms to achieve high fault coverage. It is able to virtually handle almost any circuit size and is designed to support all kind of designs. We present the first results obtained on a small design, the Leon2 IP, on which exhaustive fault injection have been performed.

ABSTRACT Microprocessor-based system's robustness under Single Event Effects is a very current concern. A widely adopted solution to make robust a microprocessor-based system consists in modifying the software application by adding redundancy and fault detection capabilities. The efficiency of the selected software-based solution must be assessed. This evaluation process allows the designers to choose the more suitable robustness technique and check if the hardened system achieves the expected dependability levels. Several approaches with this purpose can be found in the literature, but their efficiency is limited in terms of the number of faults that can be injected, as well as the level of accuracy of the fault injection process. In this paper, we propose FPGA-based fault injection techniques to evaluate software robustness methods under Single Event Upset (SEU) as well as Single Event Transient (SET). Experimental results illustrate the benefits of using the proposed fault injection method, which is able to evaluate a high amount of faults of both types of events.

Microcontrollers and serial-to-Ethernet converters are used in industrial control systems for communication and control of devices. The malfunctioning of these components can result in damage both in equipments and in the manufacturing process of products, bringing risks to the physical integrity of people who operate machines that depends of these embedded systems. The growing integration of microcontrollers and serial-to-Ethernet converters to the Internet and the increase of vulnerabilities involving industrial control systems make the security of these devices become a more and more important feature. This article presents the use of fault injection techniques through the network to evaluate the security of the TCP/IP stack of the microcontroller and serial-to-Ethernet converter Tibbo EM1206. The procedure followed for this evaluation can be used to conduct similar evaluations.

The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to attacks on hardware which guards such secure information. The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure. This paper examines various DFT based attack implementation method applied to cryptographic hardware. The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.

This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to

Static random-access-memory-based field-programmable gate array devices are an attractive option for onboard data processing in space systems due to higher computational capabilities and a lower power envelope than traditional processing devices. However, field-programmable gate arrays present unique reliability verification challenges because single-event upsets can trigger both data errors and configuration memory errors, which may cause deviations from the expected system functionality. To evaluate system reliability, traditional fault-injection testing uses numerous test vectors to observe the effects induced by a change of a single configuration memory bit at a time. This single-bit fault-injection methodology provides high fault coverage and testing repeatability, but it requires a long fault-injection time due to the large number of test vectors required to verify the entire design’s functionality. Long injection times are further exacerbated as configuration memory size and design complexity increase. To shorten injection time, a Simple, Portable Fault Injector platform is proposed for field-programmable gate arrays used in tandem with a novel multibit fault-injection methodology that modifies multiple configuration memory bits, referred to as a batch, during each test. The proposed methodology is optimized to efficiently detect the faulty bits within a batch, adaptively select the optimal batch size, and optimize the fault-injection sequence based on the design’s placement. Using relevant case studies, Simple, Portable Fault Injector for field-programmable gate arrays augmented with multibit fault-injection methodology reveals up to 50 times the speedup in fault-injection time.

Space technology is no longer used only for much specialised research activities or for sophisticated manned space missions. Modern society relies more and more on space technology and applications for every day activities. Worldwide telecommunications, Earth observation, navigation and remote sensing are only a few examples of space applications on which we rely daily. The European driven global navigation system Galileo and its associated applications, e.g. air traffic management, vessel and car navigation, will significantly expand the already stringent safety requirements for space based applications Apart from their usefulness and practical applications, every single piece of onboard software deployed into the space represents an enormous investment. With a long lifetime operation and being extremely difficult to maintain and upgrade, at least when comparing with "mainstream" software development, the importance of ensuring their correctness before deployment is immen...

Laser fault injections induce transient faults into IC s by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of MOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of IC s designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR drop that contribute to the fault injection process. This thesis describes our research on the assessment of this contribution. It shows by simulation and experiments that during laser fault injection campaigns, laser-induced IR
drop is always present when considering circuits designed in deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that uses standard CAD tools to allow the use of the enhanced electrical model to simulate laser-induced faults at
the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor as large as 3 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems. Furthermore, experimental and simulation results show that even though laser fault injection is a very local and
accurate fault injection technique, the induced IR drops have a global effect spreading through the supply network. This gives experimental evidence that the effect of laser illumination is not as local as usually considered.

— Testing digital circuits before their implementation is critical to design highly reliable systems. This allows the designer to detect faults and measure the effectiveness of the used fault-tolerance techniques. Fault injection is used to measure the robustness of fault-tolerant systems during the design process and determine the dependability parameters of the system. This paper proposes a fault injection system to inject both permanent and transient faults at different fault rates that vary with the time to simulate fault rate in space orbits. Simulation results illustrate that the calculated variations are close to the actual on-orbit rates.

Presents and discusses observed failure modes of a commercial off-the-shelf (COTS) database management system (DBMS) under the presence of transient operational faults induced by SWIFI (software-implemented fault injection). The Transaction Processing Performance Council (TPC) standard TPC-C benchmark and its associated environment is used, together with fault-injection technology, building a framework that discloses both dependability and performance figures. Over 1600 faults were injected in the database server of a client/server computing environment built on the Oracle 8.1.5 database engine and Windows NT running on COTS machines with Intel Pentium processors. A macroscopic view on the impact of faults revealed that: (1) a large majority of the faults caused no observable abnormal impact in the database server (in 96% of hardware faults and 80% of software faults, the database server behaved normally); (2) software faults are more prone to letting the database server hang or to causing abnormal terminations; (3) up to 51% of software faults lead to observable failures in the client processes