Chip

This paper describes a model of heat transfer for the convection section of a biomass boiler. The predictions obtained with the model are compared to the measurement results from two boilers, a 50 kW th pellet boiler and a 4000 kW th wood chips boiler. An adequate accuracy was achieved on the wood chips boiler. As for the pellet boiler, the calculated and measured heat transfer rates differed more than expected on the basis of the inaccuracies in correlation reported in the literature. The most uncertain aspect of the model was assumed to be the correlation equation of the entrance region. Hence, the model was adjusted to improve the correlation. As a result of this, a high degree of accuracy was also obtained with the pellet boiler. The next step was to analyse the effect of design and the operating parameters on the pellet boiler. Firstly, the portion of radiation was established at 3-13 per cent, and the portion of entrance region at 39-52 per cent of the entire heat transfer rate under typical operating conditions. The effect of natural convection was small. Secondly, the heat transfer rate seemed to increase when dividing the convection section into more passes, even when the heat transfer surface area remained constant. This is because the effect of the entrance region is recurrent. Thirdly, when using smaller tube diameters the heat transfer area is more energy-efficient, even when the bulk velocity of the flow remains constant.

AC-DC thermal converters are fabricated by depositing thin-film heaters on thin dielectric membranes on a silicon chip and by remotely sensing their temperature with radiation sensors through infrared transmissive fibers. This permits all degrees of freedom for the design of the heater for optimum frequency response. In the present design the sensitivity is quite small. With a temperature of the heater 100 K above ambient, only 5 W heats up the black spot target of the radiation sensor, resulting in an output voltage of 1.5 mV. The standard deviation of the mean of an ac-dc voltage transfer involving 12 measurements is approximately 20 2 10 06 to 50 2 10 06 .

This paper presents a new intensity-to-time processing paradigm suitable for very large scale integration (VLSI) computational sensor implementation of global operations over sensed images. Global image quantities usually describe images with fewer data. When computed at the point of sensing, global quantities result in a low-latency performance due to the reduced data transfer requirements between an image sensor and a processor. The global quantities also help global top-down adaptation: the quantities are continuously computed on-chip, and are readily available to sensing for adaptation. As an example, we have developed a sorting image computational sensor-a VLSI chip which senses an image and sorts all pixel by their intensities. The first sorting sensor prototype is a 21 2 2 2 26 array of cells. It receives an image optically, senses it, and computes the image's cumulative histogram-a global quantity which can be quickly routed off chip via one pin. In addition, the global cumulative histogram is used internally on-chip in a top-down fashion to adapt the values in individual pixel so as to reflect the index of the incoming light, thus computing an "image of indices." The image of indices never saturates and has a uniform histogram.

Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.

ErbB2 (HER2/neu) is overexpressed in about 25-30% of breast malignancies, and up-regulation of ErbB2 in breast cancer patients is associated with poor prognosis. It is known that the carboxyl terminus of heat shock cognate 70 interacting protein (CHIP) efficiently down-regulates ErbB2 in vitro. Human tumourous imaginal disc 1 (Tid1, DnaJa3), a co-chaperone of heat shock protein 70 (Hsp70), also suppresses ErbB2 expression in breast cancer cell lines. However, the intracellular interactions among Tid1, CHIP, and ErbB2 remain elusive, and the utilization of Tid1 and CHIP as breast cancer biomarkers has never been proposed. Herein, we analysed the expression and correlations among Tid1, CHIP, and ErbB2 in a total of 183 breast cancer histology sections, including 30 fresh tissue specimens, using immunohistochemistry (IHC) and immunoblotting assay. A computerized image analysis system was used for IHC scoring and determining relative immunoblot intensity. The immunohistochemical expression of Tid1 and CHIP were positively correlated with each other but were both inversely correlated to that of ErbB2. Odds ratio analyses showed that lower expression of Tid1 has a relatively higher risk of unfavourable tumour grade, later pathological stage, larger tumour size, and microscopic features of a more malignant histology including lymphovascular invasion, stromal inflammatory response, and tumour necrosis. Expression of CHIP displayed similar characteristics. Furthermore, expression of Tid1 and/or CHIP increases patients' 10-year overall and disease-free survival rate. Empirically, we also demonstrated that Tid1, CHIP, and ErbB2 interacted with each other through immunofluorescence or co-immunoprecipitation analyses. Functionally, Tid1 and CHIP acted synergistically to degrade ErbB2 in vitro. Conversely, Tid1 cannot compensate for the loss of proteolytic function noted in CHIP mutations for degradation of ErbB2. Overall, our data suggest that Tid1 and CHIP play pivotal roles in affecting the levels of ErbB2 protein, and that both are significant prognostic indicators of breast cancer patient survival.

Flue gas emissions and particle size distribution were investigated during combustion experiments of wood, forest residue and mixtures of these two. The combustion experiments were carried out in a grate fired multi-fuel reactor with and without air staging at stable operation conditions and constant temperature of 850 °C. The overall excess air ratio was held at 1.6, and the primary excess air ratio was 0.8 during air staged experiments. NOx emissions are reduced by air staging. Fly ash particle concentration of forest residues in the flue gas is lower than wood. Aerosols number increased in the staged experiments for fuel blends.

We present a laterally emitting, coupled cavity micro fluidic dye ring laser, suitable for integration into lab-on-a-chip micro systems. The micro-fluidic laser has been successfully designed, fabricated, characterized and modelled. The resonator is formed by a micro-fluidic channel bounded by two isosceles triangle mirrors. The micro-fluidic laser structure is defined using photo lithography in 10 microns thick SU-8 polymer on a glass substrate. The micro fluidic channel is sealed by a glass lid, using PMMA adhesive bonding. The laser is characterized using the laser dye Rhodamine 6G dissolved in ethanol or ethylene glycol as the active gain medium, which is pumped through the micro-fluidic channel and laser resonator. The dye laser is optically pumped normal to the chip plane at 532 nm by a pulsed, frequency doubled Nd:YAG laser and lasing is observed with a threshold pump pulse energy flux of around 55 micro-Joule/square-milimeter. The lasing is multi-mode, and the laser has switchable output coupling into an integrated polymer planar waveguide. Tuning of the lasing wavelength is feasible by changing the dye/solvent properties.

A single-ISA heterogeneous multi-core architecture is a chip multiprocessor composed of cores of varying size, performance, and complexity. This paper demonstrates that this architecture can provide significantly higher performance in the same area than a conventional chip multiprocessor. It does so by matching the various jobs of a diverse workload to the various cores. This type of architecture covers a spectrum of workloads particularly well, providing high single-thread performance when thread parallelism is low, and high throughput when thread parallelism is high.

Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. However, NoCs can be plagued by higher power consumption and degraded throughput if the network and router are not designed properly. Towards this end, this paper proposes a novel router architecture, where we tune the frequency of a router in response to network load to manage both performance and power. We propose three dynamic frequency tuning techniques, FreqBoost, FreqThrtl and FreqTune, targeted at congestion and power management in NoCs. As enablers for these techniques, we exploit Dynamic Voltage and Frequency Scaling (DVFS) and the imbalance in a generic router pipeline through time stealing. Experiments using synthetic workloads on a 8x8 wormhole-switched mesh interconnect show that FreqBoost is a better choice for reducing average latency (maximum 40%) while, FreqThrtl provides the maximum benefits in terms of power saving and energy delay product (EDP). The FreqTune scheme is a better candidate for optimizing both performance and power, achieving on an average 36% reduction in latency, 13% savings in power (up to 24% at high load), and 40% savings (up to 70% at high load) in EDP. With application benchmarks, we observe IPC improvement up to 23% using our design. The performance and power benefits also scale for larger NoCs.

The m i n i " system tempentture design of MCMs containing a number of chips of equal power for design in natwal convection is pursued through the optimal thermal placement of chips. For dealing with the thermal optimization problems, a simple but effective thermal design methodology that integrates a modified forcedirected (FD) algorithm and a finite element (FE) modeling technique is proposed. In the FD algorithm, novel force functions that include attractive and repulsive forces are proposed, which are built up, as a function of location and power of chips, based on the modeled actual temperature information through FE analysis, a response surface method WM) and an intmpolation scheme. The sum of these forces within the system, approximating the total system chip junction temperature, is considered as the objective of the optimization problem, and nonoverlapping conditions between chips are imposed as geometry constraints. The optimum locations of these chips are sought through an iteratwe search of the entire design space based on two proposed searching strategies. To demonstrate the effectiveness of the current design optimization methodology, severid design case studies involving direct chip attached (DCA) typed MCMs containing a number of chips of equal power are performed. The obtained results am: extensively compared against the published data.

This paper describes the development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques. This device isolates hard errors in system memory by writing a true and complement pattern to each system memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the memory word level, this method is more efficient than page swapping. Access to the on-chip cache occurs in parallel with access to system memory, so memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant memory system by as much as 35 times. and digital design for radar signal processing systems. He is currently an Associate Department Head in MITRE'S VLSI/VHSIC

This work examines the cellular localization of holocarboxylase synthetase (HCS) and its association to chromatin during different stages of development of Drosophila melanogaster. While HCS is well known for its role in the attachment of biotin to biotin-dependent carboxylase, it also regulates the transcription of HCS and carboxylases genes by triggering a cGMP-dependent signal transduction cascade. Further, its presence in the nucleus of cells suggests additional regulatory roles, but the mechanism involved has remained elusive. In this study, we show in D. melanogaster that HCS migrates to the nucleus at the gastrulation stage. In polytene chromosomes, it is associated to heterochromatin bands where it co-localizes with histone 3 trimethylated at lysine 9 (H3K9met3) but not with the euchromatin mark histone 3 acetylated at lysine 9 (H3K9ac). Further, we demonstrate the association of HCS with the hsp70 promoter by immunofluorescence and chromatin immuno-precipitation (ChIP) of associated DNA sequences. We demonstrate the occupancy of HCS to the core promoter region of the transcriptionally inactive hsp70 gene. On heat-shock activation of the hsp70 promoter, HCS is displaced and the promoter region becomes enriched with the TFIIH subunits XPD and XPB and elongating RNA pol II, the latter also demonstrated using ChIP assays. We suggest that HCS may have a role in the repression of gene expression through a mechanism involving its trafficking to the nucleus and interaction with heterochromatic sites coincident with H3K9met3.

Fabrication of microfluidic systems capable of extracting and isolating nucleic acids from biological samples and preparing them for downstream applications within the same device is of interest as on-chip sample preparation reduces the time and effort expended on multi-step benchtop procedures. A microfluidic chip capable of cell lysis, nucleic acid extraction and immobilization has been developed in our laboratory. This report focuses on substrate development and chip integration of the nucleic acid immobilization platform. The immobilization region was initially developed using poly-adenylated mRNA released from normal human lymphoblastoid cells. After immobilization, the mRNA remains functional for amplification by the reverse transcription polymerase chain reaction (RT-PCR) and quantitative real-time PCR (qPCR) gene expression analyses. Detailed surface functionalization, chemical modification, and covalent oligonucleotide immobilization methods are described. Vapor and liquid ...

Caenorhabditis elegans is a well-established model organism and has been gaining interest particularly related to worm locomotion and the investigation of the relationship between muscle arms and the motion pattern of the nematode. In this paper, we report on a micropillar-based on-chip system which is capable of quantifying multi-point locomotive forces of a moving C. elegans. A Polydimethylsiloxane (PDMS) device was microfabricated to allow C. elegans to move in a matrix of micropillars in a channel, and an image processing method was developed to resolve the worm force from the bending pillars. The current micropillar-based system is able to measure force with a resolution of 2.07 μN for body width of 80 μm. Initial experiments have been conducted to collect a maximum force level for thirteen wild type worm samples. A maximum force level of 61.94 μN was observed from 1571 data points, based on which an average maximum force level was 32.61 μN for multi-point measurements. The demonstrated capabilities of the system can be an enabling technology that allows biologist to gain a better understanding of subtle force patterns of C. elegans and worm muscle development.

Massive parallel computing performed on manycore Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which maps all tasks of the application into each region. In the application mapping step, several strategies based on the maximal empty rectangle (MER) technique are introduced for finding an optimal region for each application. In the task mapping step, a treemodel based algorithm is used with the purpose of reducing the communication latency and energy consumption. The experiment results show that the proposed method can achieve considerable reduction of network latency and energy consumption (up to 18%) for a given set of applications.

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six-transistor (6 T) SRAM and proposes an alternative bitcell that functions to much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.

One of the most challenging problems in Application-Specific Networks-on-Chip (ASNoC) design is to customize the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. The enhancement in area cost is achieved by reducing both routers area and the number of global links. Given the application core graph, Fiduccia-Mattheyses (FM) algorithm is adopted with modification to formulate the partitioning problem as an optimization one. As a proof of concept, our technique is applied to three different applications with different number of cores. Results show that the proposed technique is a promising way to reduce the ASNoC area compared to other topology generation techniques.

and the Electrical Engineering Department of the Arizona State University, in Tempe, and he serves as its Director. His research interests include design automation, verification, and testing of digital systems. His teaching experience includes undergraduate and graduate courses in digital systems design and testing, CMOS VLSI design, VLSI physical design, synthesis and formal verification, and discrete mathematics.

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13µm CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz.

A key application for microsystems in life-science are active microimplants for restoring and substituting lost or impaired biological functions in humans. The development of functional microdevices that ®t in the human eye and that take over lost biological functions to restore vision is a challenge that several international research are engaged in. This paper describes the joint multi-team efforts of German scientists to develop a microelectromechnical implant to stimulate retinal structures for regaining lost visional functions. Different types of active eye implants have been developed for stimulation in the epiretinal and subretinal space. Microelectrode arrays for electrical stimulation have been integrated into¯exible and rigid substrates. Innovative microtechniques have been developed for obtaining biocompatible¯exible microstructures, interconnects, and hybrid assemblies to ®t in the eye ball. Biocompatibility of material and devices was investigated in all design phases utilizing in vitro cell and tissue culture test. Devices at various stages of development have been evaluated in acute and chronic animal models. Passive stimulator electrode arrays (without electronic components) remained in animals for more than 6 months after implantation. Furthermore, animal experiments have shown that active devices equipped with silicon chips could be inserted and housed into the eye. Fully functional chronic devices are presently tested in animals. Experiments on humans are planned in the near future.

We describe a new fabrication process utilizing polydimethylesiloxane (PDMS) as a sacrificial substrate layer for fabricating free-standing SU-8-based biomedical and microfluidic devices. The PDMS-on-glass substrate permits SU-8 photo patterning and layer-to-layer bonding. We have developed a novel PDMS-based process which allows the SU-8 structures to be easily peeled off from the substrate after complete fabrication. As an example, a fully enclosed microfluidic chip has been successfully fabricated utilizing the presented new process. The enclosed microfluidic chip uses adhesive bonding technology and the SU-8 layers from 10 µm to 450 µm thick for fully enclosed microchannels. SU-8 layers as large as the glass substrate are successfully fabricated and peeled off from the PDMS layer as single continuous sheets. The fabrication results are supported by optical microscopy and profilometry. The peel-off force for the 120 µm thick SU-8-based chips is measured using a voice coil actuator (VCA). As an additional benefit the release step leaves the input and the output of the microchannels accessible to the outside world facilitating interconnecting to the external devices.

This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chiplevel simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

We have developed a super compact optical fluorescence spectrometer. Our innovative design combines advantages of guided wave planar optics and free-space microoptics. This innovation allows for miniaturization that is not achievable with pure planar or pure free-space optics. A prototype device has volume of its optical part below 1cm3. The spectrometer covers 450nm-650nm spectral range, and provides spectral resolution of

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

Pyramidal neurons in hippocampal subregions are selectively vulnerable in certain disease states. To investigate, we tested the hypothesis that selective vulnerability in human hippocampus is related to regional differences in neuronal cell death and cell receptor gene expression in CA1 vs. CA3 subregions. We used laser capture microdissection to remove approximately 600 CA1 and 600 CA3 pyramidal neurons each from five fresh-frozen normal post-mortem brains, extracted total RNA and double-amplified mRNA. This was reverse transcribed and labeled for hybridization onto human cDNA array chips containing probes to 10,174 genes and unknown ESTs. RNA from additional microdissections was pooled for replicate hybridizations and quantitative RT-PCR validation. Gene expression differences were few ( < 1%). We found 43 enriched genes in CA1 neuronal samples that included peripheral benzodiazipine receptor-associated protein, nicotinic cholinergic receptor, two chemokine receptors (CCR1 and CCR5) and several transcriptional factors. We found 17 enriched genes in the CA3 neuronal samples that included fibroblast growth factor receptor and prostaglandin-endoperoxide synthase 1. We found no differential gene expression for 23 calcium channel proteins; nine transporter proteins; 55 cell death and apoptotic regulator proteins; and an additional 497 cell receptors, including 24 glutamate receptors. Quantitative RT-PCR of four differentially expressed genes confirmed the microarray data. The results confirm the ability to examine gene expression profiles in microdissected neurons from human autopsy brain. They show only minor gene expression differences between two distinct neuronal populations in the hippocampus and suggest that selective hippocampal vulnerability is due to factors other than intrinsic differential expression in glutamate receptors and cell death genes. D

Hernia surgery has been associated with severe pain within the first 24 h postoperatively. The application of cold or cryotherapy has been in use since at least the time of Hippocrates. The physiological and biological effects from the reduction of temperature in various tissues include local analgesia, inhibited oedema formation and reduced blood circulation. Our hypothesis was that cold therapy, applied by means of ice packs, following inguinal hernia surgery, controlled pain postoperatively. Forty patients scheduled for inguinal hernia repair were enrolled in a double-blind, randomized study. Postoperatively, chipped ice in a plastic bag (cold group), and a plastic bag containing only room temperature water (control) were placed over the incision for 20 min. Postoperative pain data were collected at 2, 6 and 24 h after operation according to the well validated visual analogue scale (VAS). The highest pain levels were recorded 2 h postoperatively for both groups. Pain levels then gradually decreased for both the trial groups during the first 24 h postoperatively. There were significant differences in the VAS scores between the groups at 2, 6 and 24 h. We conclude that local cooling is a safe and effective technique for providing analgesia following inguinal hernia repair.

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8X over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5X. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7X using a 200 mV swing.

Quality control analysis is a crucial task in manufacturing activities. Nevertheless, in mechanical and steel industry, the automation of the visual inspection phase of ferromagnetic parts of mechanical structures (e.g. engines) is still a research field and no satisfactory approaches have been adopted. To visualize structural surface defects better, the mechanical parts are usually treated by the Fluorescent Magnetic Particle Inspection (FMPI) method . The result of this phase is an image of the mechanical part where edges or structural surface defects (like crack marks or scratches) are evidenced as thin, bright lines. Once the mechanical parts have been treated by the FMPI method, the quality analysis is commonly performed by an expert human operator who must distinguish, by looking at the n this paper, we present a VLSI architecture for real-time image processing in quality control industrial applications: automation of the visual inspection phase of mechanical parts treated by the IFl uorescent Magnetic Particle Inspection method for structural-defect detection. The VLSI architecture implements a highly constrained neural network tailored for this specific application: the multi-layer perceptron with strictly local connections. The learning of the weights is performed off line by using the adaptive simulated-annealing algorithm. The neural network has been trained on real plant data: recognition results of the training and classification tasks compare favorably with those obtained by expert human operators.

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Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. The vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. The whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw bandwidth. Tarantula extends the Alpha ISA with new vector instructions that operate on new architectural state. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather than acting as a co-processor, (5) can achieve a peak of 104 operations per cycle, and (6) achieves excellent "real-computation" per transistor and per watt ratios. Our detailed simulations show that Tarantula achieves an average speedup of 5X over EV8, out of a peak speedup in terms of flops of 8X. Furthermore, performance on gather/scatter intensive benchmarks such as Radix Sort is also remarkable: a speedup of almost 3X over EV8 and 15 sustained operations per cycle. Several benchmarks exceed 20 operations per cycle.

An experimental study was performed to evaluate the bond strength between two concrete layers, using different techniques for increasing the roughness of the substrate surface and a commercial epoxy-based bonding agent. A total of 40 slant shear half specimens and 40 pull-off half specimens first had the substrate surface prepared by wire-brushing, sand-blasting, chipping with a light jackhammer, or were left as-cast against steel formwork. Three months later, the bonding agent was applied and the new concrete was added. Pull-off tests and slant shear tests were performed to evaluate the bond strength in tension and in shear. Analysis of the results indicates that the application of an epoxy-based bonding agent does not improve the bond strength since the adopted method for surface preparation adequately increases its roughness.

To date, there has been relatively little research on Internet gambling. Furthermore, there have been few studies comparing the behaviour of Internet gamblers versus non-Internet gamblers. Using the game of roulette, this study experimentally examined (a) the differences in gambling behaviour between online and offline gamblers, and (b) the role social facilitation in gambling behaviour between online and offline gamblers. A total of 38 participants played online and offline roulette either alone or alongside another gambling ...

We present a parametric experimental study of convective electrokinetic instability (EKI) in an isotropically etched, cross-shaped microchannel using quantitative epifluorescence imaging. The base state is a three-inlet, one-outlet electrokinetic focusing flow configuration where the centre sample stream and sheath flows have mismatched ionic conductivities. Electrokinetic flows with conductivity gradients become unstable when the electroviscous stretching and folding of conductivity interfaces grows faster than the dissipative effect of molecular diffusion. Scalar images, critical applied fields required for instability, and temporal and spatial scalar energy are presented for flows with a wide range of applied d.c. electric field and centre-tosheath conductivity ratios. These parameters impose variations of the electric Rayleigh number across four orders of magnitude. We introduce a scaling for charge density in the bulk fluid as a function of local maximum conductivity gradients in the flow. This scaling shows that the flow becomes unstable at a critical electric Rayleigh number (Ra e, = 205) and applies to a wide range of applied field and centre-tosheath conductivity ratios. This work is relevant to on-chip electrokinetic flows with conductivity gradients such as field amplified sample stacking, flow at the intersections of multi-dimensional assays, electrokinetic control and separation of sample streams with poorly specified chemistry, and low-Reynolds number micromixing.

This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one-to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequencydependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.

A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimental results were presented at ITC'95. This paper presents results for different clock speeds and clocking modes (at-speed and delay), and uses this data to characterize the behavior of the defective parts. It was found that timing-related defects are common, and the escape rate for different test techniques on these parts is discussed.

In this paper we show the possibility of using FAUST (a program-ming language for function based block oriented programming) to create a fast audio processor in a single chip FPGA environment. The produced VHDL code is embedded in the on-chip processor system and utilizes the FPGA fabric for parallel processing. For the purpose of implementing and testing the code a com-plete System-On-Chip framework has been created. We use a Dig-ilent board with a XILINX Virtex 2 Pro FPGA. The chip has a PowerPC 405 core and the framework uses the on chip peripheral bus to interface the core. The content of this paper presents a proof-of-concept imple-mentation using a simple two pole IIR filter. The produced code is working, although more work has to be done for implementing complex arithmetic operations support.

The content of reducing sugars and asparagine, responsible for the formation of acrylamide, was determined in eight Indian potato varieties. Among these, Kufri chipsona-2 and Kufri lavkar showed the lowest level of reducing sugar (680.68 ± 56.50 mg/kg) and asparagine (2074.36 ± 122.27 mg/kg), respectively. The acrylamide content in potato chips prepared from Kufri chipsona-2, the variety that is used commercially in India for making potato chips was also the lowest. Irradiation of this variety of potatoes at the sprout inhibition dose of 60 Gy and subsequent storage for six months showed a 10.7% lower content of reducing sugars at both 14 and 4 °C. The acrylamide content was 8.41% and 6.95% lower in chips from irradiated potatoes stored at 14 and 4 °C than the corresponding non-irradiated controls. The colour of the chips was also better in irradiated potatoes as judged from the L∗ and a∗ values.► Indian varieties of potatoes were screened for their ability to form acrylamide. ► Irradiation reduces sprouting, and hence the reducing sugars. ► Irradiated potatoes showed lower content of acrylamide in potato chips.

This paper presents a burst-mode 1.25Gb/s transmitter suitable for use in Ethernet PON (E-PON) applications. With burst enable signal the transmitter proposed in this paper allows fast responses from the beginning of high-speed burst data while a conventional APC circuits based on feedback from a monitor photodiode was used. The chip was implemented in 0.18µm CMOS technology and occupies an area of 0.9 0.75 mm 2 with about 260mW power dissipation under 3.3V supply. Measurement shows a stable transmitted optical power over a wide temperature range (-40 C to 80 C) with above 10dB extinction ratio.

The effects of cryogenic cooling on cutting forces in the milling process of AISI 304 stainless steel were investigated experimentally. Cryogenic cooling was achieved by spraying liquid nitrogen to tool, chips and material interfaces using a pipe with an internal diameter of 1 mm; the flow rate of liquid nitrogen was 5.2 L/min; two cutting directions (climbing and conventional milling), two machining conditions (dry and cryogenic cooling) and four cutting speeds (80, 120, 160 and 200 m/min) were used in the milling process. Cryogenic cooling and cutting speed are found to be effective on cutting forces. Cutting forces and torque in cryogenic milling are higher than those in dry milling. Cutting force is increased as the cutting speed is increased. Tool fritter around insert nose radius is the main problem of climb milling method in cryogenic cooling at low cutting speeds.

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered. In the first scenario, the total area occupied by the grid lines is maintained constant and the grid inductance versus grid resistance tradeoff is evaluated as the width of the grid lines varies. In the second scenario, the metal area of the grid is maintained constant and the grid inductance versus grid area tradeoff is investigated. In both cases, the grid inductance increases virtually linearly with line width, rising more then eightfold for a tenfold increase in line width. The grid resistance and grid area, however, decrease relatively slowly with line width. This decrease in grid resistance and area is limited to a factor of two under assumed interconnect characteristics.

This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specific application-refueling of vehicles. The system is based on monochromatic, monocular vision, and it utilizes very specialized image processing schemes. Image processing consists of very fast filtering and segmenting algorithms, as well as moment's computation. A robotic arm with 6 joints (FANUC M-6i), and a controller unit (R-J3), does the physical work. A serial interface, with very high-level commands, connects a supercomputing machine and the robot's controller. A practical setup would probably be scaled down to a special design robot, and a single processor controller with special VLSI chips for image processing. Results are very promising; the robot can identify the cap position, orientation, and height in real time with acceptable accuracy and reliability.

This paper describes the use of digitally set delay lines in conjunction with MUTEX time comparison circuits, to measure on-chip signal path timing differences to accuracies of better than 10ps. Three methods of time measurement are described. The first, which uses parallel MUTEXs with a tapped delay line, is analogous to a flash A/D converter. The second one is similar to a successive approximation method. Both are fast, and efficient, but the second requires less hardware for a large number of bits. The third technique uses a MUTEX to amplify small time differences to a measurable size. Applications for these techniques include adaptive synchronization and input tests, such as data setup time conditions that currently require the use of very expensive test hardware. We describe an on-chip method of testing these conditions, using uncorrelated signals whose statistics are known, and accurately selecting the conditions to be tested on-chip.

Network on Chip is an efficient on-chip communication architecture for SoC architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC with multiple, connecting to other router and to a local IP core. This router architecture can be used later for building a NoC with standard or arbitrary topology with low latency and high speed and High maximal peak performance. The low latency and high speed is achieved by allowing for each input port a routing function which runs in parallel with Link controler and with distributed arbiters. To evaluate our approach, A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA thechnology, with different flit size.