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    VHDL Monday Test

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    Dimple Bansal
    The document contains a quiz on VHDL concepts with multiple choice questions. It tests understanding of VHDL entity declaration, architecture body, sum of products, and differences between VHDL and other hardware description languages. Key aspects covered include the sections that make up VHDL code and how statements are evaluated concurrently in the architecture body.

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    VHDL Monday Test

    Uploaded by

    Dimple Bansal
    124 views2 pages
    The document contains a quiz on VHDL concepts with multiple choice questions. It tests understanding of VHDL entity declaration, architecture body, sum of products, and differences between VHDL and other hardware description languages. Key aspects covered include the sections that make up VHDL code and how statements are evaluated concurrently in the architecture body.

    Original Description:

    For Semester VIII Students of E & C Department, Gyan Vihar University, Jaipur, Rajasthan

    Original Title

    Vhdl Monday Test

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    The document contains a quiz on VHDL concepts with multiple choice questions. It tests understanding of VHDL entity declaration, architecture body, sum of products, and differences between VHDL and other hardware description languages. Key aspects covered include the sections that make up VHDL code and how statements are evaluated concurrently in the architecture body.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    124 views2 pages

    VHDL Monday Test

    Uploaded by

    Dimple Bansal
    The document contains a quiz on VHDL concepts with multiple choice questions. It tests understanding of VHDL entity declaration, architecture body, sum of products, and differences between VHDL and other hardware description languages. Key aspects covered include the sections that make up VHDL code and how statements are evaluated concurrently in the architecture body.

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    © All Rights Reserved
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    SURESH GYAN VIHAR UNIVERSITY

    DEPT. OF E&C
    MONDAY TEST VHDL SECTION A
    1. The following VHDL ENTITY declaration
    code is incorrect because:
    ENTITY boolean2 IS
    PORT(
    A,B,C,D,E: IN std_logic;
    X
    : OUT std_logic);
    END boolean1;
    (a) It has too many inputs
    (b) Missing ENTITY name
    (c) Missing PORT END
    (d) Mismatch in the ENTITY name
    2. The following code can represent the
    VHDL ENTITY declaration for a ________
    -input OR gate.
    ENTITY booly IS
    PORT(
    A,B,C,D,E: IN bit;
    X
    : OUT bit);
    END booly;
    (a) 3
    (b) 4
    (c) 5
    (d) 6
    3. The following ARCHITECTURE body
    declaration is incorrect because:

    (a)

    B ) B C
    X =( A +

    (b)

    + C
    X = AB +B

    (c)

    )B
    C
    X =( AB

    (d)

    + B+
    C
    X = AB

    5. The Boolean sum of four product terms is


    called the sum-of-products.
    (a) True
    (b) False
    6. VHDL code is divided into three sections:
    library declaration, entity declaration, and
    architecture body.
    (a) True
    (b) False

    (a) missing semicolon after "END arc"


    (b) no end to match the BEGIN command
    (c) missing semicolon after the IS command
    (d) "END arc" should read "arc END"

    7. Sum-of-products is two or more product


    terms that are NANDed together.
    (a) True
    (b) False

    4. The Boolean equation for x is:

    8. The ARCHITECTURE body of the above


    program is for a 4-input AND gate.

    SURESH GYAN VIHAR UNIVERSITY


    DEPT. OF E&C
    MONDAY TEST VHDL SECTION A
    12.Any VHDL description must contain atleast
    one entity
    (a) True
    (b) False
    13.How much architecture can be associated
    with an entity?
    (a) One or more
    (b) More than one
    (c) Only one
    (d) None
    14. In VHDL, the mode of a port does not define:
    (a) True
    (b) False
    9. The full form of VHDL is
    (a) Very High Speed Integrated Circuits
    Hardware description Language
    (b) Very High Scale Integrated Circuits
    Hardware description Language
    (c) Very High Speed Integrated Circuits
    Hardware division Language
    (d) VLSI Hardware description Language

    10. What is the basic difference between AHDL and


    VHDL?
    (a)

    ADHL is used in all PLD's.

    (b)

    VHDL is used in all PLD's.

    ADHL is proprietary.

    (d)

    VHDL is proprietary.

    11. How are the statements between BEGIN


    and END not evaluated in VHDL?
    (a) Constantly
    (b) Simultaneously
    (c) Concurrently
    (d) Sequentially

    (a)
    (b)
    (c)
    (d)

    an input.
    an output.
    both an input and an output.
    the TYPE of the bit.

    15.In VHDL a digital system is modeled as


    (a) Module
    (b) Entity
    (c) Process
    (d) All of the above
    16.If the declarative part in the architecture
    of a half adder is as below:
    component XOR2
    port (X,Y:in BIT;z: out BIT);
    end component
    component AND2
    port (L,M:in BIT;z:out BIT);
    end component;
    Then what kind of architecture is it ?
    (a) Structural
    (b) Behavioral
    (c) Dataflow
    (d) None of these
    17.Define Entity in one line.
    18.What do you mean by hardware
    description languages? Why are they
    needed?
    19.Difference between VHDL and Verilog?
    20.Write 2 features of VHDL.

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