ANNUAL JOURNAL OF ELECTRONICS, 2012, ISSN 1314-0078

Simulation of 1T DRAM Memory Cell with

Verilog-A Model of CNTFET in Cadence
Mariya Lyubomirova Spasova, George Vasilev Angelov and Marin Hristov Hristov
Abstract - Carbon nanotubes are promising materials for transistors [5], Gallium Antimonide (GaSb) nanowire
the nanoscale memory devices. A Verilog-A formulation of the transistors [6], Gallium Nitride (GN) nano-field effect
Stanford compact model for CNTFET is used for simulation transistors [7], Zinc oxide (ZnO) nanowire transistor [8],
of 1T DRAM cell in Cadence Spectre circuit simulator. Read FinFET [9].
and write operations of the 1T DRAM circuit with CNTFET
are compared to the memory circuit with standard nmos4
As one of the most important nanomaterials with
transistor from 0.35 µm CMOS design kit of AMS. The excellent mechanical and electronic properties, carbon
analysis showed that CNTFET is applicable to 1T DRAM nanotube has been explored for various memory
memory cell and CNTFET memory cell has better applications. The first Carbon NanoTube Field-Effect
performance compared to the standard MOSFET. Transistor (CNTFET) was reported in 1998 [4], [10]. Since
Keywords – Carbon nanotubes, CNTFET, 1T DRAM, then the progress of CNTFET technology and the under-
compact model, circuit simulation. standing of its device physics has been very quick [11].
Carbon nanotubes are form of carbon that can be
I. INTRODUCTION considered as the result of folding graphite layers into
carbon cylinders and may be composed of single shell–
The state-of-the-art high density integrated circuits are single wall nanotubes (SWNTs), or of several shells –
based on the bulk CMOS (complimentary metal-oxide- multi-wall nanotubes (MWNTs). Depending on the folding
semiconductor) technology and the classic MOSFET. angle and the diameter, nanotubes can be metallic or
Technology progress and device scaling have driven semiconducting. Simple theory predicts that the band gap
semiconductor devices into nanometer scale of dimensions. of semiconducting nanotubes decreases with increasing
This implies unwanted physical effects such as leakage diameter. These predictions have been verified in recent
currents, tunneling, etc. i.e. arises the need for introducing scanning tunneling spectroscopy experiments [4], [12].
new devices that could follow the Moore’s law overcoming Recent experimental and theoretical studies have shown
the physical limits of the conventional MOS transistor [1]. that the CNTFET device can outperform state-of-the-art
Dynamic RAMs are important class of semiconductor silicon MOSFET in many ways [3], [10], [13], [14]. It has
devices based on the MOSFET with huge range of been listed in the International Technology Roadmap of
applications to all computational devices. DRAM Semiconductors as an emerging candidate succeeding
integrated circuits also obey the Moore’s law and thus, silicon CMOS device [11]. The tremendous developments
there is an urgent need of new materials to address the in CNTFETs promise that there will soon be implemented
problems related to higher data storage, smaller sizes, an alternative material to replace silicon in conventional
higher density of integration, lower power consumption, microelectronics.
higher reliability, faster performance, etc. And all these Concerning memory applications, a simple CNTFET can
requirements have to be met at a low cost. work as a memory device through storing charges in SiO2.
One very important aspect of device scaling is the The detailed charge injection process, however, is still not
extremely reduced oxide thickness of MOSFETs. A well studied [15]. This causes uncertainty on the reliability
prospective solution to this issue is the use of electronic and the retention capability of the device because the SiO2
devices with channels made of a single carbon nanotube or itself works as both tunneling barrier and storage media in
a semiconductor nanowire. Carbon nanotubes are sheets of such device and the trap density determines both the charge
graphite layers (grapheme, a semi-metal) rolled into a tube density and the leakage current.
[2]. Depending on the way the sheet is rolled up (its In the non-volatile memory application, however, it is
chirality) the CNT may be metallic or semiconducting. not a straight forward solution to simply replacing silicon
Interest in carbon nanotubes is driven by their electronic, MOSFET with CNTFET in a Flash cell without a
optical, thermal, and mechanical properties [2], [3]. significant change of the cell structure [15]. Unlike the
There are several types of alternatives to the FinFET [16], whose channel is still considered bulky
conventional SiO2 used to overcome this problem: carbon comparing with a CNT channel, the bulk floating gate in
nanotube (CNT) transistors [4], Silicon (Si) nanowire the present flash cell structure seems unlikely to be able to
pull out the full advantage of the CNTFET considering the
M. Spasova is PhD student at ECAD Laboratory, Technical electrostatic coupling and the charge injection efficiency.
University of Sofia, 8 Kliment Ohridski blvd., 1000 Sofia, In the present paper we focus on application of CNTFET
Bulgaria, e-mail: mls@ecad.tu-sofia.bg
G. Angelov, PhD, is asst. professor with the Dept of
model to volatile memories. We simulate a CNTFET in one
Microelectronics FETT, TU–Sofia, 8 Kliment Ohridski blvd., transistor (1T) DRAM memory circuit using a Verilog-A
1000 Sofia, Bulgaria, e-mail: gva@ecad.tu-sofia.bg formulation of the Stanford CNTFET model [17]. The
M. Hristov is professor with the Dept. of Microelectronics, Verilog-A code is implemented in Cadence Spectre circuit
FETT, Technical University of Sofia, 8 Kliment Ohridski blvd., simulator as an external model. Simulation results
1000 Sofia, Bulgaria, e-mail: mhristov@ecad.tu-sofia.bg concerning CNTFET are compared to the results simulated
 ANNUAL JOURNAL OF ELECTRONICS, 2012

for the standard NMOS transistor in the 0.35 mm AMS Transconductance is a fundamental parameter
CMOS technology design kit. characterizing MOSFET amplifier properties. It is defined
by the following expression:
II. CIRCUIT DESCRIPTION AND SIMULATIONS
S = ΔID / ΔVGS at VDS = const (1)
The compact model of the CNTFET developed by the
Nanotechnology/Nanoelectronics Group at Stanford
University describes enhancement mode MOSFET with
semiconducting single wall carbon nanotube as channel.
The model is based on a quasi-ballistic transport
assumption and accounts for the capacitor network in a
CNFET. Each device may have one or more carbon
nanotubes and the effects of channel length scaling can be
accurately modeled down to 20nm [18], [19].

FIGURE 3. IDS(VDS) AT VGS = 0, 0.625, 1.25, 1.87 AND 2.500 V ;

VBS = 0 V; L = 14 NM W = 0.1 µM FOR CNTFET.

FIGURE 1. CNTFET OUTPUT I-V CHARACTERISTIC.

Figures 2 and 3 present the I–V characteristics of the

standard nmos4 transistor within AMS 0.35 μm design kit
and the CNTFET transistor, respectively.

FIGURE 4. IDS (VGS) AT VDS = 2.5 V; VBS = 0 V; L = 14 NM W = 0.1

µm FOR CNTFET COMPACT MODEL AND L = 0.35 µm W = 10 µm
FOR NMOS4 MODEL FROM CADEBCE LIBRARY.

Figure 5 shows the transconductance characteristics of

the two transistors. For the Stanford CNTFET the
transconductance has greater value in the range between 0
V – 0.7 V and 1.3 V do 3 V. In the range between 1.2 V –
1.3 V the characteristics of both MOS transistors match to
each other. Тransconductance of Stanford CNTFET
FIGURE 2. IDS(VDS) AT VGS = 0, 0.625, 1.25, 1.87 AND 2.500 V;
VBS = 0 V; L = 0.35 µM W = 10 µM NMOS4 MODEL TO CADENCE
compact model is less in the range from 0.7 V – 1.2 V.
LIBRARY.

Since our design kit is for 0.35 mm CMOS technology,

when we set submicron dimensions to both standard design
kit nms4 transistor and the CNTFET transistor, we obtain
unrealistic results. This is due to model limitations: in the
Stanford CNTEFT compact model the channel length
should be between (10-100 nm); there are no limitations to
channel width.
Figures 4 present the transfer I-V characteristics of the
standard nmos4 transistor and the CNTFET, respectively.
Both characteristics match almost perfectly to each other
between 1 V and 2 V. The Stanford CNTFET compact
FIGURE 5. TRANSCONDUCTANCE OF BOTH MODELS AT IDS (VGS) AT
model has higher transfer characteristics in the range VDS = 2.5 V; VBS = 0 V; L = 14 nm W = 0.1 µm FOR CNTFET
between 0 V to 1 V and 2 V to 3 V. COMPACT MODEL AND L = 0.35 µm W = 10 µm FOR NMOS4 MODEL
FROM CADENCE LIBRARY.
 ANNUAL JOURNAL OF ELECTRONICS, 2012

Figure 6 shows 1T DRAM cell memory circuit with using high-k capacitor. Now we replace the standard
Stanford CNTFET compact model. In our previous paper transistor in the memory cell with CNTFET transistor to
[20] we made simulations with the same memory cell, compare the results.

FIGURE 6. DRAM ARRAY AND DATA LINE CONFIGURATION WITH CNTFET.

A) OPERATION READ OF 0 WITH CNTFET TRANSISTOR. B) OPERATION READ OF 1 WITH CNTFET TRANSISTOR

C) OPERATION WRITE OF 0 WITH CNTFET TRANSISTOR. D) OPERATION WRITE OF 1 WITH CNTFET TRANSISTOR
FIGURE 7. THE READ/WRITE OPERATIONS OF THE WITH CNTFET TRANSISTOR

On Figure 7 voltage sources V22 and V23 (Fig. 6) are Figure 7а), operation “read of 0”. The voltage defined on
turned ON; Sense Amplifier (SA) has applied voltage of 0 data lines (WL and WL1) by voltage sources V18 and V20
V and 1 V. Voltage source V24 with a voltage 0 V и 1 V is is between 0.5 V ÷ 1 V. Capacitances of the two cell
applied to PE. Voltage sources V14, V24, V3 are applied to capacitors are as follows C0 = 30 fF, C10 = 90 fF. The
the I/O block with a voltage 0 V и 1 V. voltage defined on data lines (BL and BL-) are C6 = 100 fF
 ANNUAL JOURNAL OF ELECTRONICS, 2012

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