Infineon_IMLT65R026M2H_DataSheet_v02_00_EN-3518011

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IMLT65R026M2H
Final datasheet

SiC MOSFET TOLT


CoolSiC™ MOSFET 650 V G2
16 9

9 16

Built on Infineon’s robust 2nd generation Silicon Carbide trench


technology, the 650 V CoolSiC™ MOSFET delivers unparalleled
performance, superior reliability, and great ease of use. It enables cost
effective, highly efficient, and simplified designs to fulfill the ever‑growing 8
system and market needs.
1

8 1

Features
• Ultra‑low switching losses Drain
• Benchmark gate threshold voltage, VGS(th) = 4.5 V Pin 9-16, Tab
• Robust against parasitic turn‑on even with 0 V turn‑off gate voltage
• Flexible driving voltage and compatible with bipolar driving scheme
• Robust body diode operation under hard commutation events
*1
Gate
Pin 8
• .XT interconnection technology for best‑in‑class thermal performance Driver
Source
Benefits
Power
Pin 7
Source
• Enables high efficiency and high power density designs *1: Internal body diode Pin 1-6

• Facilitates great ease of use and integration


• Provides the best price performance ratio compared to Industry’s most
ambitious roadmaps
• Reduces the size, weight and bill of materials of the systems
• Enhances system robustness and reliability

Potential applications
• SMPS
• Solar PV inverters
• Energy storage and battery formation
• UPS
• EV charging infrastructure
• Motor drives
Product validation
Fully qualified according to JEDEC for Industrial Applications
Please note: The source and driver source pins are not exchangeable. Their
exchange might lead to malfunction.
Table 1 Key Performance Parameters
Parameter Value Unit
VDSS over full Tj,range 650 V
RDS(on),typ 26 mΩ
RDS(on),max 33 mΩ
QG,typ 42 nC
ID,pulse 216 A
Qoss @ 400 V 80 nC
Eoss @ 400 V 10.8 μJ

Type/Ordering Code Package Marking Related Links


IMLT65R026M2H PG‑HDSOP‑16 65R026M2 see Appendix A

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Table of Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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1 Maximum ratings
at Tj = 25°C, unless otherwise specified.

Note: for optimum lifetime and reliability, Infineon recommends operating conditions that do not exceed
80% of the maximum ratings stated in this datasheet.

Table 2 Maximum ratings


Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
82 Tc = 25°C
Continuous DC drain current 1) IDDC ‑ ‑ A
57 Tc = 100°C
Peak drain current 2) IDM ‑ ‑ 216 A Tc = 25°C, VGS = 18 V
Avalanche energy, single pulse EAS ‑ ‑ 200 mJ ID = 7.5 A, VDD = 50 V; see table 11
Avalanche energy, repetitive EAR ‑ ‑ 1.00 mJ ID = 7.5 A, VDD = 50 V; see table 11
Avalanche current, single pulse IAS ‑ ‑ 7.5 A ‑
MOSFET dv/dt ruggedness dv/dt ‑ ‑ 200 V/ns VDS= 0...400 V
Gate source voltage (static) 3) VGS ‑7 ‑ 23 V ‑
Gate source voltage (transient) VGS ‑10 ‑ 25 V tp ≤ 500 ns, duty cycle ≤ 1%
Power dissipation Ptot ‑ ‑ 365 W Tc = 25°C
Storage temperature Tstg ‑55 ‑ 150 °C ‑
Operating junction temperature Tj ‑55 ‑ 175 °C ‑
Mounting torque ‑ ‑ ‑ ‑ Ncm ‑
82 VGS = 18 V, Tc = 25°C
Continuous reverse drain current 1) ISDC ‑ ‑ A
54 VGS = 0 V, Tc = 25°C
216 Tc = 25°C, tp ≤ 250 ns
Peak reverse drain current 2) ISM ‑ ‑ A
65 Tc = 25°C
Insulation withstand voltage VISO ‑ ‑ n.a. V Vrms, Tc = 25°C, t = 1 min
1) Limited by Tj,max.
2) Pulse width tpulse limited by Tj,max.
3) The maximum gate‑source voltage in the application design should be in accordance to IPC‑9592B.

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2 Thermal characteristics
Table 3 Thermal characteristics
Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
Not subject to production test.
Parameter verified by
Thermal resistance, junction ‑ case Rth(j‑c) ‑ ‑ 0.41 °C/W
design/characterization according
to JESD51‑14.
Soldering temperature,
Tsold ‑ ‑ 260 °C reflow MSL1
reflow soldering allowed

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3 Operating range
Table 4 Operating range
Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
Recommended turn‑on voltage VGS(on) ‑ 18 ‑ V ‑
Recommended turn‑off voltage VGS(off) ‑ 0 ‑ V ‑

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4 Electrical characteristics
at Tj = 25°C, unless otherwise specified

Table 5 Static characteristics


Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
Drain‑source voltage VDSS 650 ‑ ‑ V VGS = 0 V, ID = 0.7 mA
Gate threshold voltage 4) VGS(th) 3.5 4.5 5.6 V VDS = VGS, ID = 7 mA
1 75 VDS = 650 V, VGS = 0 V, Tj = 25°C
Zero gate voltage drain current IDSS ‑ μA
3 ‑ VDS = 650 V, VGS = 0 V, Tj = 175°C
Gate‑source leakage current IGSS ‑ ‑ 100 nA VGS = 20 V, VDS = 0 V
34 ‑ VGS = 15 V, ID = 34.5 A, Tj = 25°C
26 33 VGS = 18 V, ID = 34.5 A, Tj = 25°C
Drain‑source on‑state resistance RDS(on) ‑ mΩ
24 ‑ VGS = 20 V, ID = 34.5 A, Tj = 25°C
43 ‑ VGS = 18 V, ID = 34.5 A, Tj =175°C
Internal gate resistance RG,int ‑ 2.9 ‑ Ω f = 1 MHz
4)Tested after 1 ms pulse at VGS = +20 V. “Linear mode” operation is not recommended. For assessment of potential “linear
mode” operation, please contact Infineon sales office.

Table 6 Dynamic characteristics

External parasitic elements (PCB layout) influence switching behavior significantly.


Stray inductances and coupling capacitances must be minimized.
For layout recommendations please use provided application notes or contact Infineon sales office.

Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
Input capacitance Ciss ‑ 1499 ‑ pF VGS = 0 V, VDS = 400 V, f = 250 kHz
Reverse transfer capacitance Crss ‑ 8.6 ‑ pF VGS = 0 V, VDS = 400 V, f = 250 kHz
Output capacitance 5) Coss ‑ 111 145 pF VGS = 0 V, VDS = 400 V, f = 250 kHz

Output charge 5) Qoss ‑ 80 103 nC calculation based on Coss


Effective output capacitance, VGS = 0 V,
Co(er) ‑ 135 ‑ pF
energy related 6) VDS = 0...400 V
Effective output capacitance, ID = constant, VGS = 0 V,
Co(tr) ‑ 199 ‑ pF
time related 7) VDS = 0...400 V
VDD = 400 V, VGS = 0/18 V,
Turn‑on delay time td(on) ‑ 9.3 ‑ ns ID = 34.5 A, RG,ext = 1.8 Ω;
see table 10
VDD = 400 V, VGS = 0/18 V,
Rise time tr ‑ 10.1 ‑ ns ID = 34.5 A, RG,ext = 1.8 Ω;
see table 10

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Table 6 Dynamic characteristics

External parasitic elements (PCB layout) influence switching behavior significantly.


Stray inductances and coupling capacitances must be minimized.
For layout recommendations please use provided application notes or contact Infineon sales office.

Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
VDD = 400 V, VGS = 0/18 V,
Turn‑off delay time td(off) ‑ 16 ‑ ns ID = 34.5 A, RG,ext = 1.8 Ω;
see table 10
VDD = 400 V, VGS = 0/18 V,
Fall time tf ‑ 5.1 ‑ ns ID = 34.5 A, RG,ext = 1.8 Ω;
see table 10
VDD = 400 V, VGS = 0/18 V,
Turn‑ON switching losses 8) Eon ‑ 43 ‑ μJ
ID = 34.5 A, RG,ext = 1.8 Ω
VDD = 400 V, VGS = 0/18 V,
Turn‑OFF switching losses 8) Eoff ‑ 33 ‑ μJ
ID = 34.5 A, RG,ext = 1.8 Ω
VDD = 400 V, VGS = 0/18 V,
Total switching losses 8) Etot ‑ 76 ‑ μJ
ID = 34.5 A, RG,ext = 1.8 Ω
5) Maximum specification is defined by calculated six sigma upper confidence bound
6) Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 400 V.
7) Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 400 V.
8) Values for 4‑pin configuration based on TO‑263‑7 measurements; MOSFET used in half‑bridge configuration without external
diode

Table 7 Gate charge characteristics


Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
VDD = 400 V, ID = 34.5 A,
Plateau gate to source charge QGS(pl) ‑ 11.0 ‑ nC
VGS = 0 to 18 V
VDD = 400 V, ID = 34.5 A,
Gate to drain charge QGD ‑ 7.9 ‑ nC
VGS = 0 to 18 V
VDD = 400 V, ID = 34.5 A,
Total gate charge QG ‑ 42 ‑ nC
VGS = 0 to 18 V

Table 8 Reverse diode characteristics


Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
Drain‑source reverse voltage VSD ‑ 4.3 ‑ V VGS = 0 V, IS = 34.5 A, Tj = 25°C
VDD = 400 V, IS = 34.5 A,
16 diS/dt = 1000 A/μs; see table 9
MOSFET forward recovery time tfr ‑ ‑ ns
10.7 VDD = 400 V, IS = 34.5 A,
diS/dt = 4000 A/μs; see table 9

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Table 8 Reverse diode characteristics


Values
Parameter Symbol Unit Note/ Test Condition
Min. Typ. Max.
VDD = 400 V, IS = 34.5 A,
83 diS/dt = 1000 A/μs; see table 9
MOSFET forward recovery charge 9) Qfr ‑ ‑ nC
131 VDD = 400 V, IS = 34.5 A,
diS/dt = 4000 A/μs; see table 9
VDD = 400 V, IS = 34.5 A,
MOSFET peak forward recovery 10.6 diS/dt = 1000 A/μs; see table 9
Ifrm ‑ ‑ A
current 25 VDD = 400 V, IS = 34.5 A,
diS/dt = 4000 A/μs; see table 9
9) Qfr includes Qoss

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5 Electrical characteristics diagrams

Diagram 1: Power dissipation Diagram 2: Safe operating area


400 103

320 102 1 µs

10 µs
240 101
Ptot [W]

ID [A]
100 µs

160 100
1 ms

10 ms
80 10 1
DC

0 10 2
0 25 50 75 100 125 150 175 100 101 102 103
TC [°C] VDS [V]
Ptot=f(TC) ID=f(VDS); TC=25 °C; D=0; parameter: tp

Diagram 3: Safe operating area Diagram 4: Max. transient thermal impedance


103 100

102 1 µs 0.5

10 µs 10 1
0.2
101
ZthJC [K/W]

0.1
ID [A]

100 µs 0.05
0.02
100
1 ms 0.01
10 2

10 ms single pulse
10 1
DC

10 2 10 3
100 101 102 103 10 6 10 5 10 4 10 3 10 2 10 1
VDS [V] tp [s]
ID=f(VDS); TC=80 °C; D=0; parameter: tp ZthJC=f(tP); parameter: D=tp/T

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Diagram 5: Typ. output characteristics Diagram 6: Typ. output characteristics


400 400

20 V

300 18 V 300
20 V
18 V
ID [A]

ID [A]
200 200
15 V
15 V

100 12 V 100 12 V
10 V
10 V
8V
8V
0 0
0 5 10 15 20 0 5 10 15 20
VDS [V] VDS [V]
ID=f(VDS); Tj=25 °C; parameter: VGS ID=f(VDS); Tj=175 °C; parameter: VGS

Diagram 7: Typ. drain‑source on‑state resistance Diagram 8: Drain‑source on‑state resistance


0.090 2.0
0.085
0.080
0.075
0.070 10 V 12 V 15 V
RDS(on) [normalized]

18 V 1.5
0.065
RDS(on) [ ]

0.060 20 V
0.055
0.050 1.0
0.045
0.040
0.035
0.030 0.5
0 50 100 150 200 250 300 350 50 25 0 25 50 75 100 125 150 175
IDS [A] Tj [°C]
RDS(on)=f(IDS); Tj=125 °C; parameter: VGS RDS(on)=f(Tj); ID=34.5 A; VGS=18 V

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Diagram 9: Typ. transfer characteristics Diagram 10: Typ. gate charge


400 20
18
16
300
25 °C 14

175 °C 12

VGS [V]
ID [A]

200 10 400 V
8
6
100
4
2
0 0
0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 45 50
VGS [V] QG [nC]
ID=f(VGS); VDS=20V; parameter: Tj VGS=f(Qgate); ID=35 A pulsed; parameter: VDD

Diagram 11: Typ. reverse characteristics Diagram 12: Typ. reverse characteristics
103 103

102 102
25 °C
ISD [A]

ISD [A]

101 175 °C 25 °C 101 175 °C

100 100

10 1 10 1
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VSD [V] VSD [V]
ISD=f(VSD); VGS=0 V; parameter: Tj ISD=f(VSD); VGS=18 V; parameter: Tj

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Diagram 13: Avalanche energy Diagram 14: Drain‑source breakdown voltage


250 700

200 690

150 680

V(BR)DSS [V]
EAS [mJ]

100 670

50 660

0 650
25 50 75 100 125 150 175 50 25 0 25 50 75 100 125 150 175
Tj [°C] Tj [°C]
EAS=f(Tj); ID=7.5 A; VDD=50 V V(BR)DSS=f(Tj); ID=0.7 mA

Diagram 15: Typ. capacitances Diagram 16: Typ. Coss stored energy
104 30

25
Ciss
103
20
Eoss [µJ]
C [pF]

102 Coss 15

10
101 Crss
5

100 0
0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700
VDS [V] VDS [V]
C=f(VDS); VGS=0 V; f=250 kHz Eoss=f(VDS)

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Diagram 17: Typ. Qoss output charge Diagram 18: Typ. Switching Losses vs RG,ext
120 500

100
400 Etot

80
300
Qoss [nC]

E [µJ]
60
Eon
200
Eoff
40

100
20

0 0
0 100 200 300 400 500 600 700 0 5 10 15 20 25
VDS [V] RG, ext [ ]
Qoss=f(VDS) E=f(RG,ext); VDD=400 V; VGS=0‑18 V; ID=34.5 A

Diagram 19: Typ. Switching Losses vs switching current


220
200
180
160
140
120 Etot
E [µJ]

100
80
Eoff
60
Eon
40
20
0
0 10 20 30 40 50 60 70 80
ID [A]
E=f(ID); V DD=400 V; VGS=0‑18 V; RG,ext=1.8 Ω

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6 Test Circuits
Table 9 Body diode characteristics (CoolSiC)
Test circuit for body diode characteristics Body diode recovery waveform

VDS
+
VDD

RG2 VDS
IS
- Is
ISO tfr
IS
VDD
dIs / dt

RG1 Ifrm
Qfr

Ifrm

Table 10 Switching times (CoolSiC)

Switching times test circuit for inductive load Switching times waveform

VDS
90%

VDS VDD 10%


VGS
VGS
td(on) tr td(off) tf
RG
ton toff

Table 11 Unclamped inductive load

Unclamped inductive load test circuit Unclamped inductive waveform

VDSS

VDD
ID
VDS

VDS VDS
ID

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7 Package Outlines

PACKAGE - GROUP
NUMBER: PG-HDSOP-16-U02
MILLIMETERS MILLIMETERS
DIMENSIONS DIMENSIONS
MIN. MAX. MIN. MAX.
A 2.25 2.35 e 1.20
A1 0.00 0.15 e1 8.40
b 0.60 0.80 L 1.50
c 0.40 0.60 P 3.00
D 9.70 10.10 O 10°
D1 9.46 O1 0.00° 8°
D2 8.20 8.40
D3 0.15
E 14.80 15.20
E1 10.00 10.30
E2 5.27
E3 4.05
E4 2.00
E5 2.24

Figure 1 Outline PG‑HDSOP‑16, dimensions in mm

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4.2

1.2 0.8 4.2


14× 16×
1.2 0.76
14× 16×

2.66
16×

16×
2.7
6.85

6.85
13.7

13.7

Pin1

copper solder mask stencil apertures

All dimensions are in units mm


All pads are non-solder mask defined

Figure 2 Footprint Drawing PG‑HDSOP‑16, dimensions in mm

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Pin1 marking 12

4 0.3

11.5

24
15.65

2.85
10.3

All dimensions are in units mm


The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]

Figure 3 Packaging Variant PG‑HDSOP‑16, dimensions in mm

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8 Appendix A
Table 12 Related Links

IFX CoolSiC CoolSiC™ MOSFET 650V G2 Webpage

IFX CoolSiC CoolSiC™ MOSFET 650V G2 Application Note

IFX CoolSiC CoolSiC™ MOSFET 650V G2 Simulation Model

IFX Design tools

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Revision History
IMLT65R026M2H

Revision 2024‑09‑06, Rev. 2.0


Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2024‑09‑06 Release of final

Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to
continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com

Published by
Infineon Technologies AG
81726 München, Germany
© 2024 Infineon Technologies AG
All Rights Reserved.

Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon
Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non‑infringement of
intellectual property rights of any third party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any
applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in
customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical
departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this
document with respect to such application.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.
infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the
nearest Infineon Technologies Office.
The Infineon Technologies component described in this Data Sheet may be used in life‑support devices or systems and/or automotive, aviation
and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life‑support, automotive, aviation and aerospace device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or
maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be
endangered.

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