MRF1550 Motorola
MRF1550 Motorola
MRF1550 Motorola
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction to Case RθJC 0.75 °C/W
TJ – TC
(1) Calculated based on the formula PD =
RθJC
NOTE – CAUTION – MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 6
MOTOROLA
Motorola, RF DEVICE DATA MRF1550T1 MRF1550FT1
Inc. 2003 For More Information On This Product,
1
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS — continued (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current IDSS — — 1 µAdc
(VDS = 60 Vdc, VGS = 0 Vdc)
Gate–Source Leakage Current IGSS — — 0.5 µAdc
(VGS = 10 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS
Gate Threshold Voltage VGS(th) 1 — 3 Vdc
(VDS = 12.5 Vdc, ID = 800 µA)
Drain–Source On–Voltage RDS(on) — — 0.5 Ω
(VGS = 5 Vdc, ID = 1.2 A)
Drain–Source On–Voltage VDS(on) — — 1 Vdc
(VGS = 10 Vdc, ID = 4.0 Adc)
DYNAMIC CHARACTERISTICS
Freescale Semiconductor, Inc...
C5 160 pF, 100 mil Chip Capacitor R3 1 kΩ, 1/8 W Chip Resistor
C6 240 pF, 100 mil Chip Capacitor R4 33 kΩ, 1/4 W Chip Resistor
C7, C17 300 pF, 100 mil Chip Capacitors Z1 1.000″ x 0.080″ Microstrip
C8, C18 10 µF, 50 V Electrolytic Capacitors Z2 0.400″ x 0.080″ Microstrip
C9, C19 0.1 µF, 100 mil Chip Capacitors Z3 0.200″ x 0.080″ Microstrip
C10 470 pF, 100 mil Chip Capacitor Z4 0.200″ x 0.080″ Microstrip
C11, C12 200 pF, 100 mil Chip Capacitors Z5, Z6 0.100″ x 0.223″ Microstrip
C13 22 pF, 100 mil Chip Capacitor Z7 0.160″ x 0.080″ Microstrip
C14 30 pF, 100 mil Chip Capacitor Z8 0.260″ x 0.080″ Microstrip
C15 6.8 pF, 100 mil Chip Capacitor Z9 0.280″ x 0.080″ Microstrip
C20 1,000 pF, 100 mil Chip Capacitor Z10 0.270″ x 0.080″ Microstrip
L1 18.5 nH, Coilcraft #A05T Z11 0.730″ x 0.080″ Microstrip
L2 5 nH, Coilcraft #A02T Board Glass Teflon, 31 mils
L3 1 Turn, #24 AWG, 0.250″ ID
TYPICAL CHARACTERISTICS
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Figure 2. Output Power versus Input Power Figure 3. Input Return Loss
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Figure 4. Gain versus Output Power Figure 5. Drain Efficiency versus Output Power
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Figure 6. Output Power versus Biasing Current Figure 7. Drain Efficiency versus
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Figure 8. Output Power versus Supply Voltage Figure 9. Drain Efficiency versus Supply Voltage
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Freescale Semiconductor, Inc...
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IDQ = 500 mA
S11 S21 S12 S22
f
MHz |S11| ∠φ |S21| ∠φ |S12| ∠φ |S22| ∠φ
50 0.93 –178 4.817 80 0.009 –39 0.86 –176
100 0.94 –178 2.212 69 0.009 –3 0.88 –175
150 0.95 –178 1.349 61 0.008 –8 0.90 –174
200 0.95 –178 0.892 54 0.006 –13 0.92 –174
250 0.96 –178 0.648 51 0.005 –7 0.93 –174
300 0.97 –178 0.481 47 0.004 –8 0.95 –174
350 0.97 –178 0.370 46 0.005 4 0.95 –174
400 0.98 –178 0.304 43 0.001 15 0.97 –174
450 0.98 –178 0.245 43 0.005 81 0.97 –174
Freescale Semiconductor, Inc...
IDQ = 2.0 mA
S11 S21 S12 S22
f
MHz |S11| ∠φ |S21| ∠φ |S12| ∠φ |S22| ∠φ
50 0.93 –177 4.81 80 0.003 –119 0.93 –178
100 0.94 –178 2.20 69 0.006 4 0.93 –178
150 0.95 –178 1.35 61 0.003 –1 0.93 –177
200 0.95 –178 0.89 54 0.004 18 0.93 –176
250 0.96 –178 0.65 51 0.001 28 0.94 –176
300 0.97 –178 0.48 47 0.004 77 0.94 –175
350 0.97 –178 0.37 46 0.006 85 0.95 –175
400 0.98 –178 0.30 43 0.007 53 0.96 –174
450 0.98 –178 0.25 43 0.006 74 0.97 –174
500 0.98 –177 0.21 44 0.006 84 0.97 –174
550 0.99 –177 0.18 41 0.002 106 0.97 –175
600 0.98 –178 0.15 41 0.004 116 0.96 –174
IDQ = 4.0 mA
S11 S21 S12 S22
f
MHz |S11| ∠φ |S21| ∠φ |S12| ∠φ |S22| ∠φ
50 0.97 –179 5.04 87 0.002 –116 0.94 –179
100 0.96 –179 2.43 82 0.006 42 0.94 –178
150 0.96 –179 1.60 77 0.004 13 0.94 –177
200 0.96 –179 1.14 74 0.003 43 0.95 –176
250 0.97 –179 0.89 71 0.004 65 0.95 –175
300 0.97 –179 0.71 68 0.006 68 0.95 –175
350 0.97 –179 0.57 67 0.006 74 0.97 –174
DESIGN CONSIDERATIONS
This device is a common–source, RF power, N–Channel drain–source voltage under these conditions is termed
enhancement mode, Lateral Metal–Oxide Semiconductor VDS(on). For MOSFETs, VDS(on) has a positive temperature
Field–Effect Transistor (MOSFET). Motorola Application coefficient at high temperatures because it contributes to the
Note AN211A, “FETs in Theory and Practice”, is suggested power dissipation within the device.
reading for those not familiar with the construction and char- BVDSS values for this device are higher than normally re-
acteristics of FETs. quired for typical applications. Measurement of BVDSS is not
This surface mount packaged device was designed pri- recommended and may result in possible damage to the de-
marily for VHF and UHF mobile power amplifier applications. vice.
Manufacturability is improved by utilizing the tape and reel GATE CHARACTERISTICS
capability for fully automated pick and placement of parts. The gate of the RF MOSFET is a polysilicon material, and
However, care should be taken in the design process to in- is electrically isolated from the source by a layer of oxide.
sure proper heat sinking of the device. The DC input resistance is very high – on the order of 109 Ω
The major advantages of Lateral RF power MOSFETs in- — resulting in a leakage current of a few nanoamperes.
clude high gain, simple bias systems, relative immunity from Gate control is achieved by applying a positive voltage to
thermal runaway, and the ability to withstand severely mis- the gate greater than the gate–to–source threshold voltage,
matched loads without suffering damage. VGS(th).
Freescale Semiconductor, Inc...
MOSFET CAPACITANCES Gate Voltage Rating — Never exceed the gate voltage
The physical structure of a MOSFET results in capacitors rating. Exceeding the rated VGS can result in permanent
between all three terminals. The metal oxide gate structure damage to the oxide layer in the gate region.
determines the capacitors from gate–to–drain (Cgd), and Gate Termination — The gates of these devices are es-
gate–to–source (Cgs). The PN junction formed during fab- sentially capacitors. Circuits that leave the gate open–cir-
rication of the RF MOSFET results in a junction capacitance cuited or floating should be avoided. These conditions can
from drain–to–source (Cds). These capacitances are charac- result in turn–on of the devices due to voltage build–up on
terized as input (Ciss), output (Coss) and reverse transfer the input capacitor due to leakage currents or pickup.
(Crss) capacitances on data sheets. The relationships be- Gate Protection — These devices do not have an internal
tween the inter–terminal capacitances and those given on monolithic zener diode from gate–to–source. If gate protec-
data sheets are shown below. The Ciss can be specified in tion is required, an external zener diode is recommended.
two ways: Using a resistor to keep the gate–to–source impedance low
also helps dampen transients and serves another important
1. Drain shorted to source and positive voltage at the gate.
function. Voltage transients on the drain can be coupled to
2. Positive voltage of the drain in respect to source and zero the gate through the parasitic gate–drain capacitance. If the
volts at the gate. gate–to–source impedance and the rate of voltage change
In the latter case, the numbers are lower. However, neither on the drain are both high, then the signal coupled to the gate
method represents the actual operating conditions in RF ap- may be large enough to exceed the gate–threshold voltage
plications. and turn the device on.
DC BIAS
Since this device is an enhancement mode FET, drain cur-
=8)*
rent flows only when the gate is at a higher potential than the
:&
source. RF power FETs operate optimally with a quiescent
drain current (IDQ), whose value is application dependent.
)@@ / :& :@ This device was characterized at IDQ = 150 mA, which is the
8;
&@ @@ / :& &@ suggested value of bias current for typical applications. For
=@@ / :& special applications such as linear amplification, IDQ may
have to be selected to optimize the critical parameters.
:@ The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may generally be just a simple re-
#=0; sistive divider network. Some special applications may
require a more elaborate bias system.
GAIN CONTROL
DRAIN CHARACTERISTICS Power output of this device may be controlled to some de-
One critical figure of merit for a FET is its static resistance gree with a low power dc control signal applied to the gate,
in the full–on condition. This on–resistance, RDS(on), occurs thus facilitating applications such as manual gain control,
in the linear region of the output characteristic and is speci- ALC/AGC and modulation systems. This characteristic is
fied at a specific gate–source voltage and drain current. The very dependent on frequency and load line.
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TO–272
PLASTIC
MRF1550T1
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CASE 1264A–02
ISSUE A
TO–272 STRAIGHT LEAD
PLASTIC
MRF1550FT1
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