RF SYstem Design Main Topics

RF Transistor Amplifier
Designs
A mplifier designs at RF differ significantly from

the conventional low-frequency circuit approaches and consequently require special
considerations. In particular, the fact that voltage and current waves impinge upon the
active device necessitates appropriate matching to reduce the VSWR and avoid undesir-
able oscillations. For this reason a stability analysis is usually the first step in the design
process and, in conjunction with gain and noise figure circles, is a basic ingredient
needed to develop amplifier circuits that meet the often competing requirements of
gain, gain flatness, output power, bandwidth, and bias conditions.
This chapter expands upon the material covered in Chapters 2 and 3, where power
relations of terminated transmission lines are investigated. However, unlike the passive
circuit presentations, Chapter 9 deals with active devices where gain and feedback con-
siderations assume central importance. Issues such as power gain, unilateral and bilat-
eral circuit designs and their graphical display in the Smith Chart constitute the starting
point of an extensive analysis into quantifying high-frequency transistor amplifier per-
formance. The reader will note the flexibility of the Smith Chart, which allows constant
gain, VSWR, and stability circle displays to be superimposed over the reflection coeffi-
cient and impedance representation discussed in Chapter 3. Moreover, even a noise ana-
lysis can be conducted by converting the noise figure of an amplifier into circles that are
displayed in the Smith Chart.
After covering the basic design tools, Chapter 9 also investigates various types of
power amplifiers and their characteristics such as gain flatness, bandwidth, and inter-
modular distortion as well as the differences between single- and multistage amplifiers.
464 Chapter 9 RF Translstor Amplifier Deslgns
9.1 Characteristics of Amplifiers

Perhaps the most important and complex task in analog circuit theory is the ampli-
fication of an input signal through either a single or multistage transistor circuit. A
generic single-stage amplifier configuration embedded between input and output
matching networks is shown in Figure 9-1.
- ,
RF
source
-
<+
,
-
Input
,
Matching
Network
fi
V
.
T
i
output
Matching
T
Network P+ .
(OMN) i
-
Load
T'
1: DC bias
I
Lut
Figure 9-1 Generic amplifier system.
Input and output matching networks, discussed in Chapter 8, are needed to reduce
undesired reflections and thus improve the power flow capabilities. In Figure 9-1 the
amplifier is characterized through its S-matrix at a particular DC bias point. In terms of
performance specifications, the following list constitutes a set of key amplifier
parameters:
Gain and gain flatness (in dB)
Operating frequency and bandwidth (in Hz)
Output power (in dBm)
Power supply requirements (in V and A)
Input and output reflection coefficients (VSWR)
Noise figure (in dB)
In addition, one often must consider such parameters as intermodular distortion (IMD)
products, harmonics, feedback, and heating effects, all of which can seriously affect the
amplifier performance.
To approach the amplifier design process systematically, we need first to establish
a number of definitions regarding various power relations. This is followed by several
important analysis tools required to define stability, gain, noise, and VSWR perfor-
mance. The common denominator of all four topics is that they can be expressed as cir-
cle equations and displayed in the Smith Chart.
Amplltier Power Relations 465
9.2 Amplifier Power Relations
9.2.1 RF Source
There are various power gain definitions that are critical to the understanding of
how an RF amplifier functions. For this reason, let us examine Figure 9-1 in terms of its
power flow relations under the assumption that the two matching networks are included
in the source and load impedances. This simplifies our system to the configuration
shown in Figure 9-2(a). The starting point of our power analysis is the RF source con-
nected to the amplifier network. For the convention depicted in Figure 9-2 we recall our
signal flow discussion in Section 4.4.5 [see (4.82) and (4.83)]and write for the source
voltage
(a) Simplified schematics of a single-stage amplifier
bs
~ : J [ - ~ ;O
b,' 1 a,
a,' b, Sl, a* b;
3 bqrnQI'
(b) Signal flow graph

Figure 9-2 Source and load connected to a single-stage amplifier network.
The incident power wave associated with bl ' is given as

466 Chapter 9 RF Transistor Arnplitler Deslgns
which is the power launched toward the amplifier. The actual input power Pin observed
at the input terminal of the amplifier is composed of the incident and reflected power
waves. With the aid of the input reflection coefficient Tin we can therefore write:
The maximum power transfer from the source to the amplifier is achieved if the
input impedance is complex conjugate matched (Zin = Z , ) or, in terms of the reflec-
*
tion coefficients, if T i , = T , . Under maximum power transfer condition, we define the
available power PA as
This expression makes clear the dependence on T s . If Tin = 0 and T s + 0 it is seen

from (9.2) and (9.4) that Pin, = lbsl 2 / 2 .
9.2.2 Transducer Power Gain

We can next investigate the transducer power gain G T , which quantifies the
gain of the amplifier placed between source and load.
power delivered to the load - - PL
-
G, =
available power from the source PA
1 2
orwith P , = -Ib21 . ( 1 -lrL12)
weobtain
2
In this expression, the ratio b 2 / b s has to be determined. With the help of our signal
flow discussion in Section 4.4.5 and based on Figure 9-2, we establish
Ampllfkr Power Relations 467
The required ratio is therefore given by
Inserting (9.7) into (9.5) results in
which can be rearranged by defining the input and output reflection coefficients (see
Problem 9.2)
s12s21l-s
rout = S22 +
1 -s11rs
With these two definitions, two more transducer power gain expressions can be derived.
First, by incorporating (9.9a) into (9.8), it is seen that
Second, using (9.9b) in (9.8) results in the expression
An often employed approximation for the transducer power gain is the so-called unilat-
eral power gain, G,, which neglects the feedback effect of the amplifier (S12 = 0).
This simplifies the form (9.11) to
As discussed in Section 9.4.1, equation (9.12) is often used as a basis to develop approx-
imate designs for an amplifier and its input and output matching networks.
468 Chapter 9 RF Transistor Amplifier Designs
9.2.3 Additional Power Relations

The transducer power gain is a fundamental expression from which additional impor-
tant power relations can be derived. For instance, the available power gain for load
side matching (TL = I'&) is defined as
- power available from the amplifier

GA = GT
power available from the source
or, with the aid of (9.1 I),
Further, the power gain (operating power gain) is defined as the ratio of the power
delivered to the load to the power supplied to the amplifier.
power delivered to the load - PL -

_ - _ P- .L- P A -
G = - G -P A
power supplied to the amplifier Pin P A Pin TPin
Combining (9.3), (9.4), and (9.10), we find
*
It is interesting to note that (9.14) can be obtained from (9.10) by setting Ts = Fin
since in this case Pi, = P A . The following example goes through the computation of
some of these expressions for an amplifier with given S-parameters.
S & M W
Example 9-1: Power relations for an RF amplifier
-
-.-8 IX
An RF amplifier has the following S-parameters: S l l = 0.31-70°,

S,, = 3.5185", S,, = 0.21-lo0, and S2, = 0.41-45'. Fur-
thermore, the input side of the amplifier is connected to a voltage
source with Vs = 5 VLO " and source impedance Zs = 40 R . The
output is utilized to drive an antenna which has an impedance of
ZL = 73 R . Assuming that the S-parameters of the amplifier are
Amplltler Power Relations 469
measured with reference to a Zo = 50 R characteristic impedance,

find the following quantities:
(a) transducer gain GT, unilateral transducer gain GTU, available

gain G, , operating power gain G , and
(b) power delivered to the load P L , available power P A , and inci-
dent power to the amplifier Pinc.
Solution: First we find the source and load reflection coefficients

assuming a Zo = 50 R characteristic impedance:
Next, the input and output impedances, as given in (9.9a) and (9.9b),
are determined:
sl2s21 r
rout = S22 + = 0.265 - j0.358
1 - S11Ts
Substituting the obtained values along with the S-parameters into
(9.1l), (9.12), (9.13), and (9.14), the transducer gain GT, unilateral
transducer gain GTU,available gain GA, and operating power gain
G are computed as follows:
470 Chapter 9 RF Transistor Amplifier Deslgns
Using (9.2) in conjunction with (9.1) allows us to find the incident

power flow into the amplifier:
Often Pi, is expressed in dBm as

Pinc(dBm) = 10log[Pin,/(l mW)] = 18.73 dBm
Similarly, from (9.2) we find the available power to be
PA = 78.1 mW or PA = 18.93 dBm. Finally, the power delivered to
the load is the available power multiplied by the transducer gain.
This results in PL = PAGT = 98 1.4 mW , or, expressed in dBm,
It is interesting to point out that the unilateral power gain

often matches the actual transducer power gain very closely. As dis-
cussed further; the use of the unilateral amplifier gain signijicantly
simpli$es the amplijier design task.
9.3 Stability Considerations
9.3.1 Stability Circles

One of the first requirements that an amplifier circuit must meet is a stable perfor-
mance in the frequency range of interest. This is a particular concern when dealing with
RF circuits, which tend to oscillate depending on operating frequency and termination.
The phenomenon of oscillations can be understood in the context of a voltage wave
along a transmission line. If Ira( > 1 , then the return voltage increases in magnitude
(positive feedback) causing instability. Conversely, Ir0l< 1 causes a diminished return
voltage wave (negative feedback).
Let us regard the amplifier as a two-port network characterized through its S-
parameters and external terminations described by TL and Ts. Stability then implies
that the magnitudes of the reflection coefficients are less than unity. Namely,
FLI< I7 lrsl< I (9.15a)
Stability Considerations 471
where A = SllS22- S12S21has been used to re-express (9.9a) and (9.9b). Since the S-
parameters are fixed for a particular frequency, the only factors that have a parametric
effect on the stability are TL and Ts .
In terms of the amplifier's output port, we need to establish the condition for
which (9.15b) is satisfied. To this end the complex quantities
R I R I R I R I
Sll = S , l + j S l l , S 2 2 = S2,+jS2,,A = A + j A , T L = r L + j T L (9.16)
are substituted into (9.15b), resulting after some algebra in the output stability circle
equation
where the circle radius is given by
- lS12S2ll
rout -
lls2212 - 14
and the center of this circle is located at
* *
as depicted in Figure 9-3(a). In terms of the input port, substituting (9.16) into (9.1%)
yields the input stability circle equation
where
and
(a) Output stability circle (b) Input stability circle

Figure 9-3 Stability circle ITin[= 1 in the complex T, plane and stability circle
ITout[= 1 in the complex T, plane.
When plotted in the T, -plane we obtain a response as schematically shown in Figure

9-3(b).
To interpret the meaning of Figure 9-3 correctly, a critical issue arises that is
investigated for the output circle [Figure 9-3(a)], although the same argument holds for
the input circle. If TL = 0 , then Irinl= ISll[ and two cases have to be differentiated
depending on ISll[< 1 or lSlll > 1 . For lSlll < 1 , the origin (the point TL = 0 ) is part
of the stable region, see Figure 9-4(a). However, for ISl1[> 1 the matching condition
TL = 0 results in (Tin(= ISl1(> 1 , i.e. the origin is part of the unstable region. In this
case the only stable region is the shaded domain between the output stability circle
I&/ = 1 and the ITL/ = 1 circle, see Figure 9-4(b).
For completeness, Figure 9-5 shows the two stability domains for the input stabil-
ity circle. The rule-of-thumb is the inspection if IS2,( < 1 , which leads to the conclu-
sion that the center (Ts = 0 ) must be stable; otherwise the center becomes unstable for
Is221 > 1 .
Care has to be exercised in correctly interpreting the stability circles if the circle
radius is larger than (Gin( or (Co,( . Figure 9-6 depicts the input stability circles for
c 1 and the two possible stability domains depending on rin< (Cinlor rin> lCinl.
\ Unstable 1 /
(a) Shaded region is stable, (a) Stable region excludes the origin,
since ISllI< 1 r, = 0,since IS,,J> 1
Figure 9-4 Output stability circles denoting stable and unstable regions.
(a) IS22 1 < 1 (b) IS22 1 '1

Figure 9-5 Input stability circles denoting stable and unstable regions
9.3.2 Unconditional Stability

As the name implies, unconditional stability refers to the situation where the
amplifier remains stable throughout the entire domain of the Smith Chart at the selected
frequency and bias conditions. This applies to both the input and output ports. For
lS,,I < 1 and < 1 it is stated as
- --- -
Chapter 9 RF Translstor Ampilfier Designs
Figure 9-6 Different input stability regions for S221< 1 depending on

ratio between r , and ICin .
In other words, the stability circles have to reside completely outside the lrsl = 1 and
lrLl= 1 circles. In the following discussion we concentrate on the Ir,/ = 1 circle
shown in Figure 9-7(a). It is shown in Example 9-2 that condition (9.23a) can be reex-
pressed in terms of the stability or Rollett factor k:
Alternatively, unconditional stability can also be viewed in terms of the Ts behavior in

I
the complex T,, = rfUt+ jrout plane. Here, the /rs1S 1 domain must reside com-
pletely within the IrOutl= 1 circle, as depicted in Figure 9-7(b). Plotting Ir,( = 1 in
the rout plane produces a circle whose center is located at
and which possesses a radius of

Stablllty Conslderatlons
(a) [r,,,l = 1 circle must reside outside (b) FSl= 1 circle must reside inside
Figure 9-7 Unconditional stability in the T, and To,, planes for IS,,I < 1.
where the condition lCsl + rs < 1 must hold. We note that (9.25) can be rewritten as
C , = (S22- AS;^)/(^ - ISl1I2). Employing /Csl + r, < 1 and (9.26) it is seen that
IS12S2~I < I- 1 ~ 1 1 1 ~ (9.27b)

A similar analysis can be established for T L in the complex rinplane. From the
corresponding circle center C, and radius rL, we set ICLI = 0 and rs < 1 . Thus,
<I
/sl2s21/ -1 ~ 2 2 1 ~ (9.28)
However, as long as 1A1 < 1 ,(9.24) remains the sufficient requirement to ensure uncon-
ditional stability. This follows from the fact that when (9.27b) and (9.28) are added, it is
seen that
2ISl2S2,I < 2 - 1 ~ 1 1-1 1~~ 2 2 1 ~

Introducing the inequality [A1 = ISllS22-S12S211I ISllS221+ IS12S211results in
1 1 2
I4 < 1 - 3(lsll12 + 1p22l2- 21~1111~221)
= 1 - Z(IS1ll - IS221)
Since ( 1/2)(ISllI - 1Sz2ll2< 1 , it is seen that (9.27b) and (9.28) are equivalent to
14 < 1 (9.29)
. w
Example 9-2: Stability factor derivation
Derive the stability factor k (Rollett factor) from (9.23a).
Solution: Substituting (9.21) and (9.22) into (9.23a) gives
Is11 - $ 2 ~ 1 - ls12s121
>1 (9.30a)
1p11l2- b12
Squaring and rearranging (9.30a) results in
2
The term ISll - S22A1 in (9.30b) can be re-expressed as
Isll- @I 2 = IS ~+ (1 S ~ ~ ~- 1 ~~ 1 ~ ) ( 9 . 3 ~
~ - p2212)(~~1112
Squaring (9.30b) again and rearranging terms finally gives
The terms inside the curly brackets are recognized as the desired sta-
bility factor:
A stability analysis starting from (9.23b) would have resulted

in exactly the same inequality. Thus, the stability factor k applies for
both input and output ports.
Stability Conslderatlons 477
It is always prudent to determine that both the [A1 < 1 and k > 1 conditions are
fulfilled to ensure an unconditionally stable design. The next example investigates a
transistor in common-emitter configuration in terms of its input and output stability
behavior.
c & M w
Example 9-3: Stability circles for a BJT at different operating
frequencies
Determine the stability regions of the bipolar junction transistor

BFG505W (Philips Semiconductors) biased at V C E = 6 V and
Ic = 4 rnA . The corresponding S-parameters as a function of fre-
quency are given in Table 9- 1.
Table 9-1 BFG505W Sparameters as a function of frequency

I Frequency
1250 MHz
Solution: Based on the definitions for k, [A1 , Cin , Tin, Cout ,and
rout, we compute the values via a MATLAB routine (see m-file
ex9-3.m). A summary of the results is given in Table 9-2 for the four
frequencies listed in Table 9- 1.
Table 9-2 Stability parameters for BFG505W for frequencies listed in
Table 9-1
k IAI 'in 'in Cout '-out
0.41 0.69 39.04L108" 38.62 3.56170" 3.03

0.60 0.56 62.21L119" 61.60 4.12L70° 3.44
0.81 0.45 206.231131" 205.42 4.39L69' 3.54
1.02 0.37 42.421143' 41.40 4.24168' 3.22
478 Chapter 9 RF Translstor AmplHier Deslgns
The example input and output stability circles for the frequen-
cies of f = 750 MHz and f = 1.25 GHz are shown in Figure 9-8.
We notice that lSlll < 1 and ISz2[< 1 in all cases. This implies that
the rL = 0 and Ts = 0 points are stable, indicating that the inte-
rior domain of the Smith Chart up to the stability circles denotes the
stable region.
f = 1250 MHz
f = 1250 MHz /
stagility
circles
r i i a 5 , 0
4.2
Figure 9-8 Input a n d output stability circles for BFG505W computed

750 MHz a n d f = 1.25 GHz.
Also, as can be seen from Figure 9-8 and Table 9-2, the transis-
tor is unconditionally stable at f = 1.25 GHz and both input and
output stability circles are located completely outside of the IT1 = 1
circle. At all other frequencies transistor is potentially unstable.
The stability circles are not only affected byfrequency, but also
by the bias conditions. We recall that the S-parameters are given for
particular bias conditions. The entire stability analysis must be
repeated if biasing, or even temperature, changes.
Even though k can vary widely, most unstable practical designs fall into the range
0 l k l 1 . Oscillators, discussed in Chapter 10, target the entire Smith Chart as the
unstable domain, resulting in negative values of k. It is also interesting to observe that
in the absence of any output to input feedback ( S , , = 0 ) the transistor is inherently
stable, since the stability factor yields k + = . In practice, one often examines k alone
without paying attention to the )A)< 1 condition. This can cause potential problems, as
the following example highlights.
Y V & MW
Example 9-4: Stable versus unstable region of a transistor
Investigate the stability regions of a transistor whose S-parameters

are recorded as follows: S l l = 0.71-70°, S I 2 = 0.21-lo0,
S,, = 5 . 5 L U 0 ,and S22 = 0.71-45'
Solution: We again compute the values k, [A/, Cin, T i n , Gout,

and rout.The results are k = 1.15, /A1 = 1.58, C , = 0.21152",
rin = 0.54, Cou, = 0.21 L27", and rout = 0.54 (see Figure 9-9).
It is seen that even though k > 1 , the transistor is still potentially
unstable because IAI > 1 . This results in input and output stability
circle
Figure 9-9 Stability circles for k > 1 and IAI > 1 .
circles being located inside of the Smith Chart. Since both IS, and ,I
IS2,[ are less than unity, the center of the Smith Chart is a stable
point. Therefore, since ICinl < rin and ICoutI< rout,the area inside
of the stability circles represents the stable region, as shown in Fig-
ure 9-9.
Usually manufacturers avoid producing transistors with both

k > 1 and IAI > 1 by incorporating matching networks housed
inside the transistor casing.
9.3.3 Stabilization Methods

If the operation of a FET or BJT is found to be unstable in the desired frequency
range, an attempt can be made to stabilize the transistor. We recall that Irinl> 1 and
IrOutl> 1 can be written in terms of the input and output impedances:
> 1 and lrou,l=

which imply Re{Zin} < 0 and Re{Zout}< 0 . One way to stabilize the active device is
to add a series resistance or a shunt conductance to the port. Figure 9- 10 shows the con-
figuration for the input port. This loading in conjunction with Re{Z,} must compen-
sate the negative contribution of Re{Zin} . Thus, we require
Re{Zin + Rin' + Zs} > 0 or Re{ Yin + Gin' + Y,} > 0 (9.3la)
C
Source
Zin
(a) Series resistance
T n
(b) Shunt conductance
Figure 9-10 Stabilization of input port through series resistance or shunt
conductance.
Following an identical argument, Figure 9-1 1 shows the stabilization of the output port.
The corresponding condition is
zoul+~out'
You, +Gout'
--.
Active device
-
"
Active device
(BJT or FET) + Load (BIT or FET)
--.
ZOUI YO",
(a) Series resistance (b) Shunt conductance

Figure 9-11 Stabilization of output port through series resistance or shunt
conductance.
The next example explains the stabilization procedure for transistor.
5 & M w
Example 9-5: Stabilization of a BJT
Using the transistor BFG505W from Example 9-3 operated at

f = 750 MHz (and with the S-parameters given as follows:
S1, = 0.561-78", S2, = 0.05L33", SI2 = 8.64L122", and
S22 = 0.661-42"), attempt to stabilize the transistor by finding a
series resistor or shunt conductance for the input and output ports.
Solution: With given S-parameters we can identify the input and

output stability circles by computing their radii and center positions:
C i n = 62.21L119", r i n = 61.60, and C0,,=4.12L7O0,
rout = 3.44. The corresponding stability circles are shown in Figure
9-12. A constant resistance circle r' = 0.33 in the 2-chart indicates
the minimal series resistance that has to be connected to the input of
the transistor to make this port stable. If a passive network is con-
nected in series to the resistor with the value of
Rinr = r'Zo = 16.5 Q , then the combined impedance will be
located inside of the r' = 0.33 circle and therefore in the stable
region. Similarly, by tracing a constant conductance circle g' = 2.8

we find the shunt admittance Gin' = g'/Zo = 56 mS that stabilizes
the input of the transistor. This time any passive network connected to
Ginr will have the combined admittance residing inside of the
g' = 2.8 circle in the Y-chart,which is inside the stable region for the
input port of the transistor.
circle
Figure 9-12 Input and output stability circles and circles for finding stabilizing
series resistance and shunt conductances.
Following an identical procedure we can find a series resistance of

R,,,' = 40 s2 and a shunt conductance Goutr= 6.2 mS, which
stabilize the output port of the transistor.
Due to the coupling between input and output ports of the

transistor it is usually sufJicient to stabilize one port. The choice of
which port is generally up to the circuit designel: However; one
Constant Gain
attempts to avoid resistive elements at the input port since they

cause additional noise to be amplijied.
Stabilization through the addition of resistors comes at a prize: the impedance

matching can suffer, there may be a loss in power flow, and the noise figure typically
worsens due to the additional thermal noise sources that the resistors present.
9.4 Constant Gain
9.4.1 Unilateral Design

Besides ensuring stability, the need to obtain a desired gain performance is
another important consideration in the amplifier design task, If, as sometimes done in
practice, the influence of the transistor's feedback is neglected (S12= 0), we can
employ the unilateral power gain GTUdescribed by (9.12). This equation is rewritten
such that the individual contributions of the matching networks become identifiable.
With reference to Figure 9-13, we write
where the individual blocks are
r," ",, rout s22
Figure 9-13 Unilateral power gain system arrangement.
Because most gain calculations are done in dB, (9.32) is frequently expressed as
where Gs and GLare gains associated with input and output matching networks and Go
is the insertion gain of the transistor. As seen from (9.33), the network gains can be
greater than unity which at first glance might appear stronger since they do not contain
any active devices. The reason for this seemingly contradictory behavior is that without
any matching a significant power loss can occur at the input and output sides of the
amplifier. The use of Gs and GL attempts to reduce these inherent losses, which is con-
sidered a gain.
If ISl,I and IS221 are less than unity, the maximal unilateral power gain FTUmax
results when both input and output are matched (i.e., Ts = S l l and TL = S22). For
this case it is seen that
The contributions from Gs and GL can be normalized with respect to their maximum
values such that
where the normalized gain is given in both cases as 0 I gi I 1 , with i = S, L .

Even though we have explicit gain equations for the input and output matching net-
works, they are not directly usable in terms of providing parametric curves of constant
gain. The key question that must be answered is formulated as follows: For a given S1
(or S22) and a desired normalized gain gs (or g,), what is the range of values for Ts
(or rL) that achieves a particulargain? The solution requires the inversion of (9.37)
for the reflection coefficient Ti. Here ii = 11, 22 depending on i = S, L . The result is
a set of circles with center locations at
Constant Gain 485
and radii of size
Example 9-6 details the necessary steps to derive the unilateral constant gain circle
equations (9.39) and (9.40).
W&MW
Example 9-6: Derivation of the constant gain circles
Find the expressions for dg, and rg, as given in (9.39) and (9.40).
Solution: The derivation begins with (9.38), which is rewritten

as
2 * * 2 2
1 +S -S -S ) = 1- S - lTil + 1~~~1~1r~1~
(9.41a)
The reflection coefficient Ti can be factored out such that
This equation is the complex form of a circle expression

2
( q - d g i ) ( T ; - d *gi ) = r gi (9.41~)
with
Multiplying out (9.41~)results in the more familiar from

R R 2 I 1 2 2
(Ti -dgi) + ( r i - dgi) = rgi (9.41d)
where superscripts R and I denote real and imaginary parts of Ti

and dgi.
Because of the unilateral assumption we are able to derive

separate gain circle equations for input and output ports.
The following observations can be made from the constant gain circle equations
(9.39) and (9.40):
2 .
The maximum gain Gi, = 1/( 1 - ISii[ ) is obtained for Ti = s:, , which coin-
cides with the gain circle whose center is at dgi = Sii and of radius rgi = 0 .
The constant gain circles all have their centers on a line connecting the origin to
*
Sii. The smaller the gain values, the closer the center dgi moves to the origin and
the larger the radius rgi.
2
*For the special case Ti = 0 , the normalized gain becomes gi = 1 - lSiil and
2
both dgi and rgi have the same value dgi = rg, = lSii/(l + lsiil) . This implies
that the Gi = 1 (or 0 dB) circle always passes through the origin of the Ti -plane.
Example 9-7 demonstrates the source gain circles for an amplifier design under
unilateral approximation.
-- -
&
-M
w
Example 9-7: Computation of the source gain circles for a uni-
- -
A-*
lateral design
A FET is operated at f = 4 GHz and is biased such that

S,, = O.7Ll25" . It is assumed that the transistor is uncondition-
ally stable so that the unilateral approximation can be applied. Find
the maximum source gain G,,, and plot the constant source gain
circles for several values of Gs .
Solution: First we find the maximum source gain Gs,,, using

(9.35). The result is
Constant Gain 487
We can now plot the constant gain circles by using (9.39) and (9.40)
for the computation of circle centers dgs and radii rgs. A summary
of several arbitrary source gains Gs is presented in Table 9-3.
Table 9-3 Parameters for constant source gain circles
in Example 9-7.
As seen from Table 9-3, the radius rgSof the Gs = 0 dB circle

is equal to the magnitude of its center position dgs and the circle
indeed passes through the center of the Smith Chart. We also
observe that the centers for all Gs circles are located on the
O = LS,,* = -125" line, and as Gs approaches G,,, , the
radius of the corresponding circle reduces to zero and its center
position becomes Sll* = 0.71-125" .
Figure 9-14 illustrates the source gain circles based on the
computed numerical values given in Table 9-3. The figure points out
clearly that, despite the input matching network being passive, the
gain can be greater than 0 dB, indicating amplification. The physical
meaning for such a behavior lies in the fact that the matching net-
work reduces the input reflection coefficient of the overall system,
thus effectively creating an "additional" gain.
Chapter 9 RF Transistor AmpllRer Designs
-1.0
Figure 9-14 Constant source gain circles in the Smith Chart.
The underlying assumption of this example is that the gain

associated with the matched input port is not affected by the output
since the unilateral approximation neglects the reverse gain.
We next discuss a typical application that requires the use of the constant gain circle
approach. Specifically, let us develop a unilateral amplifier for a predetermined fixed
gain value.
& , . w
Example 9-8: Design of a 18 dB single-stage MESFET ampli-
fier operated at 5.7 GHz
A MESFET operated at 5.7 GHz has the following S-parameters:

Sll = 0.5L-60°, S12 = 0.02L0°, ,692, = 6.5Ll15', and
S2, = 0.6L-35".
(a) Determine if the circuit is unconditionally stable.

Constant Gain
(b) Find the maximum power gain under optimal choice of the
reflection coefficients, assuming the unilateral design (S12= 0).
(c) Adjust the load reflection coefficient such that the desired gain is
realized using the concept of constant gain circles.
Solution: (a) The stability of the device is tested via (9.24) and
(9.29), with the results
and
(A] = (SllS22- S12S21(= 0.42
Because k > 1 and )A)< 1 , the transistor is unconditionally stable.
(b) We next compute the maximum gain for the optimal choice of
the reflection coefficients (i.e., rL
2
Go = )S211 = 42.25 or 16.26 dB
Therefore, the maximum unilateral transducer gain is given by
GTUmax-
- GsmaxGoGLm,,= 88.02 or 19.45 dB
(c) Since the source matching network (Ts = Sll* ) and the transis-
tor combined already provide a gain of 17.51 dB, we have to chose
r, in such a way that GL = 0.49 dB. This means that T, has to
reside on the rgL= 0.38, dgL= 0.48135' circle, as shown in Fig-
ure 9-15. If we choose TL = 0.03 + j0.17, the output matching net-
work reduces to a single element (i.e., a series inductor with a value
of L = 0.49 nH) provided the load is equal to the characteristic
impedance (2, = Zo).
490 Chapter 9 RF Tmnsistor Amplffler Designs
-1.0
Figure 9-15 Constant load gain circle in the Smith Chart.
I f the amplijier is operated over a range of frequencies, the

gain has to be determined for a corresponding number of discrete
frequency points due to the changing S-parameters.
For the case where (Siil> 1 ( i i = 1 1 for the input port and i i = 22 for the out-
put port) it is possible for a passive network to produce an infinite value of G i ( i = S
or L , respectively). This situation occurs when T i = S i l , meaning that the real com-
ponent of the impedance associated with T i is equal in magnitude to the negative resis-
tance related to S i i . Thus, the two resistances cancel each other and oscillations will
result: the amplifier is unstable. To avoid this problem, we plot the constant gain circles
for ISii(> 1 and the corresponding stability circle and choose Tiin such a way that it is
located on the desired gain circle but also resides inside the stable region.
9.4.2 Unilateral Figure of Merit

The unilateral design approach discussed in Example 9-8 involves the approxima-
tion that the feedback effect, or the reverse gain, of the amplifier is negligible
(S12 = 0). TO estimate the error due to this assumption, the ratio between the trans-
ducer gain GT , which takes into account S 1 2 ,and the unilateral transducer gain GTu
can be formed. Using definitions (9.8)and (9.12),we find
Constant Gain
where GT I GTU.
The maximum value of G T U ,and therefore the maximum error, is obtained for
*
the input and output matching conditions (Ts = S , , and TL = S22).Therefore, (9.42)
becomes
This can be used to set bounds on the error fluctuation
where U is known as the frequency-dependent unilateral figure of merit:
To justify a unilateral amplifier design approach, this figure of merit should be as small
as possible. In the limit, as GT approaches GTu for the ideal case of SI2 = 0 , we see
that the error does indeed vanish (i.e., U = 0 ).
Y , & M W4
Example 9-9: Unilateral design applicability test
For the amplifier discussed in Example 9-8 estimate the error that is
introduced by making the unilateral design approximation.
Solution: Substituting the S-parameter values into (9.43, the

unilateral figure of merit is found to be
The maximum error can then be estimated from (9.44):
This implies that the theoretical value for the transducer gain can
deviate from its unilateral approximation by as much as 18%. Prac-
tically, however, the actual difference often is much smaller. This
becomes apparent if we substitute the values obtained in Example
9-8 into the transducer power gain definition (9.8). It is found that
GT = 62.86 or 17.98 dB, which compares favorably with
GTU = 63.10 or 18 dB. In other words, we introduced an error of
less than 1%.
The unilateral jigure of merit computation constitutes a very

conservative, worst case error estimation.
9.4.3 Bilateral Design

For many practical situations the unilateral approach may not be appropriate
because the error committed by setting S12 = 0 could result in an intolerably impre-
cise design. The bilateral design takes into account this feedback. Instead of the unilat-
* *
era1 matching T s = S l l and T L = S22, it deals with the complete equations [see
(9.15b) and (9.15c)l for the input and output reflection coefficients
which require a simultaneous conjugate match. The meaning of simultaneous implies

that matched source and load reflection coefficients rMS and rML have to be found
that satisfy both coupled equations. If the device is potentially unstable, then a simulta-
neous complex conjugate does not exist. The solution approach to obtain these optimal
coefficients is outlined in Example 9-10. The final results, for the matched source
reflection coefficient rMs is
Constant Gain
where
2
C1 = Sll -&A and B1 = 1 - S -A
2
+ IS,,I 2
Similarly, the matched load reflection coefficient rML
is
where
C2 = S2, - S;,A and B2 = 1 - IS,,^^ - 1A12 + IS^^^^ (9.50)

The solutions (9.47) and (9.49) are derived under the assumption of unconditional
stability.
With rML and rMS given by (9.47) and (9.49), the optimal matching can be
rewritten as
(9.5 la)
and
It is noted that the unilateral approach, which decouples input and output ports, is a
subset of the bilateral design approach.
c m w
Example 9-10: Derivation of simultaneous conjugate matched
reflection coefficients
Derive the reflection coefficient expression (9.47).
Solution: Starting from (9.46a) and (9.46b), we see that

*
( 1 - S & ) ( ~ S - S11) = r~S12S21 (9.52a)
Chapter 9 RF Translator Amplifier Demlgna
(9.52b)
Solving (9.52a) for r, yields
Substituting (9.52~)into (9.52b) results, after some algebra, in
(9.52d)
2 2
Identifying C = ( S - S 2 A ) , B, = (1 + ISllI -IS2,[ - 1 ~ 1 ~ )
leads to the standard quadratic equation
whose solution is
The negative sign in front of the square root is picked to ensure sta-
bility ( k > 1).
An identical analysis approach for the load side leads to a

quadratic equationfor rL whose solution yields rML.
Example 9-11 demonstrates the use of simultaneously complex conjugate reflec-

tion coefficients for the design of an amplifier with maximum gain.
w&Mw
Example 9-11: Amplifier design for maximum gain
A BJT with I c = 10 mA and V c E = 6 V is operated at a fre-

quency of f = 2.4 GHz. The corresponding S-parameters are:
S l l = 0.3L30°, S12 = 0.21-60°, S2, = 2.51-80°, and
S22 = 0.21-15'. Determine whether the transistor is uncondition-
Constant Galn 495
ally stable and find the values for source and load reflection coeffi-
cients that provide maximum gain.
Solution: The stability of the transistor is determined by com-

puting k and ]A1 based on (9.24) and (9.29) with the explicit result
of k = 1.18, IAI = 0.56. Since k > 1 and lAl < 1 , the transistor is
unconditionally stable.
As we see from the S-parameters of the transistor, S12 has a
relatively large magnitude and the use of the unilateral design
method for the amplifier does not appear appropriate, suggesting the
bilateral approach instead.
Using (9.48) and (9.50), we find the coefficients
C , =0.19+j0.06, B, =0.74, and C2 = 0.03+j0.07,
B2 = 0.64, which allow us to compute the simultaneously complex
conjugate source and load reflection coefficients
rMS = 0.301- 18 and rML = O.12L69 , respectively. It should
be noted that these values differ significantly from s;, and s i 2 ,
which are the basis for the unilateral design.
Applying (9.8), with TL and Ts replaced by TML and TMs,
we find the transducer gain to be GT = 8.42 dB. This also happens
to be the maximum transducer gain GTmax.
The discrepancy between unilateral and bilateral

* gain is best
seen *in the large diferences in phase between Sll and rMS as well
as SZ2and rML .
9.4.4 Operating and Available Power Gain Circles

For the situation where the reverse gain of S12 cannot be neglected, the input
impedance is dependent on the load reflection coefficient. Conversely, the output
impedance becomes a function of the source reflection coefficient. Because of this
mutual coupling, the unilateral approach described in Section 9.4.1 is not appropriate to
design an amplifier for a predetermined gain.
In the bilateral case, which takes into account the mutual coupling between input
and output ports, there are two alternative design methods to develop amplifiers with a
specified gain.
496 Chapter 9 RF Transistor Arnpllfler Dedgns
The first method is based on the use of the operating power gain G given by
(9.14). Here we attempt to find the load reflection coefficient r L , assuming that the
source is complex conjugate matched to the input reflection coefficient [i.e., Ts = T:~,
where Tin is computed based on (9.9a)l. This method yields an input voltage standing
wave ratio of VSWR, = 1 .
*
The second method uses the available power gain GA definition of (9.13). In this
case we assume perfect match on the output side of the amplifier (TL = Tout),and the
load is chosen in such a way as to satisfy the gain requirement. This method is prefera-
ble if the output standing wave ratio should be unity (i.e., VSWR,,, = 1 ).
Operating Power Gain
To develop the design procedure based on using the operating power gain (and
thus ensuring VSWR, = I), we rewrite (9.14) in the form
where we use (9.9a) for Tin.The factor go defines a proportionality factor given by
As shown in Example 9-12, (9.54) can be rewritten in terms of a circle equation

for the load reflection coefficient TL; that is,
I ~ -41
L = rgo (9.55)
where the center position dgois
and the radius rgois defined as
with k denoting the Roulette stability factor as defined in (9.24).

Constant Gain 497
& , . w-
Example 9-12: Operating power gain circle derivation
Starting from (9.54), derive the circle equation (9.55) in the complex
rL-plane.
Solution: First we rewrite (9.54) in the form
After multiplying both sides of (9.58) by the denominator and rear-

ranging terms, we see that
lrL12[1 + g0(p2212- I ~ 1 ~-) 21 g o ~ e { r L ( ~-2AS;^)}
2 = (9.59)
2
= I -go(l - p 1 1 1 )
Dividing (9.59) by [ I + g0(IS2212- 1AI2)], we find
This equation can already be recognized as a circle equation of the

form irL-dgo12 - 2 , where the circle center dgo is given by
(9.56) and the radisr;io is computed from
--1 - 2gop12S2,1k - g,2M

11 + g0(p2212- lAI2)l2
where k is the stability factor defined in (9.24) and M is a constant
given by
--
Chapter 9 RF Transistor Amplifier Designs
M = (1 - I s ~ ~ ~ ) ( b12) I S ~- Is22
~ ~- A
~ S-; I ~ = -1S12S211'
Thus, for the square of the circle radius we obtain
which agrees with (9.57).
The following example demonstrates the design of an amplifier based on the bilat-
eral method. It targets a specified gain using the constant operating gain circle
approach.
S & M W
Example 9-13: Amplifier design using the constant operating
gain circles
Use the same BJT as described in Example 9-11, but instead of

GTmax= 8.42 dB, design an amplifier with 8 dB power gain. In
addition, ensure a perfect match on the input port of the amplifier.
Solution: As shown in Example 9-1 1, the transistor is uncondi-

tionally stable. Because a perfect match on the input port must be
maintained, we employ the operating power gain circles in our
design.
First we compute the value of factor go ; that is,
where G = 6.31 is the required 8 dB operating gain. Substituting

go into (9.56) and (9.57), we find center and radius of the constant
operating gain circle in the T L-plane. The corresponding values are
dgo = 0.11169" and rgo = 0.35. The constant gain circle is
shown in Figure 9- 16.
Constant Galn 499
Figure 9-16 Constant operating power circle in the TL-plane.

There is a great variety of possible choices for the load reflec-
tion coefficient that ensures a G = 8 dB operating gain. To simplify
the output matching network, we pick TL at the intersection of the
constant gain circle with the constant resistance circle r = 1 (see
Figure 9-16). The value obtained at that point is TL = 0.261-75'.
With rL known, we can next find the source reflection coefficient
that must be the conjugate to the input refection coefficient as given
in (9.9a):
Based on the previously computed values, we check the correctness

of our approach. Substituting Tinand TL into (9.10), we find that
the transducer power gain is indeed 8 dB.
500 Chapter 9 RF Trfanslstor Amplltier Deslgns
The complexity of the input matching network is directly

affected by the appropriate choice of TL because of the requirement
Ts = T;n where Tin is afunction of rL.
In Example 9-13 we pick the value of T , arbitrarily (residing on the desired gain
circle) and compute a corresponding input impedance such that T , = Ti*,, assuming
that there are no restrictions imposed on the value of T , . Unfortunately, in many prac-
tical applications, T , has to satisfy certain constraints (for example, to stay within a
desired noise performance). Such additional conditions may therefore restrict our free-
dom in using r, and, as a consequence, limit the possible choices for T L. One way to
satisfy both requirements ( T L residing within an appropriate gain circle, and Ts sat-
isfy a particular noise requirement) is via trial-and-error, whereby we arbitrarily pick
T L and see whether the corresponding Ts meets design specifications. This method is
simple but very tedious and time-consuming.
A more scientific approach relies upon mapping the constant gain circle (9.55) in
the T L-plane into a circle in the T , -plane, i.e.,
where the equations for the circle radius rgs and its center dgs are obtained from the
requirement that T s = Tyn. This can be written as
Substituting (9.62) into (9.55) gives us
which can be rewritten in the form of (9.60), where the circle radius is
--
Constant Galn
and the center is given by
The derivation of (9.64) and (9.65) is left as a problem at the end of this chapter. The
example of constant gain circle mapping is discussed further in Section 9.5, Example
9-14.
Available Power Gain
In those cases where perfect matching on the output side of the amplifier is
required (VSWR,, = 1 ), the available power gain approach should be used instead of
the previously presented operating gain method. For this situation, a constant available
gain circle equation can be derived in the same fashion as (9.55) is obtained. The result
of such a derivation is a circle equation which relates the source reflection coefficient to
the desired gain:
lr~-dgal = rga (9.66)

where the center position dgais
and the radius rgais defined as
The proportionality factor g, is computed as
where GA is the desired power level.

Similar to the constant operating power circles, a constant available power circle
can be mapped into the T L-plane using
I ~ -L = 5 1 (9.70)
with the circle radius given by

502 Chapter 9 RF Transistor Arnpiffler Designs
and the center location defined by
We see that rgl and d g , for VS WR,, = 1 have their correspondence to rgs and
dgs for VSWRin = 1 with S I 1in (9.71) and (9.72) replaced by S22.
9.5 Noise Figure Circles

In many RF amplifiers, the need for signal amplification at low noise level
becomes an essential system requirement. Unfortunately, designing a low-noise ampli-
fier competes with such factors as stability and gain. For instance, a minimum noise
performance at maximum gain cannot be obtained. It is therefore important to develop
a method that allows us to display the influence of noise as part of the Smith Chart to
conduct comparisons and observe trade-offs between gain and stability.
From a practical perspective, the key ingredient of a noise analysis is the noise
figure of a two-port amplifier in the admittance form
or in the equivalent impedance representation
where Zs = l/Ys is the source impedance.

Both expressions are derived in Appendix H. When using transistors, typically
four noise parameters are known either through datasheets from the FET or BJT manu-
facturers or through direct measurements. They are:
The minimum (also called optimum) noise figure F f i n whose behavior depends
on biasing condition and operating frequency. If the device were noise free, we
would obtain F,, = 1 .
The equivalent noise resistance Rn = 1 /Gn of the device.
Noim Figurt, Circles 503
The optimum source admittance Yopt = Gopt+ jBopt = 1/Zopt . Instead of the
impedance or admittance, the optimum reflection coefficient Topt is often listed.
The relationship between Yopt and Top, is given by
Since the S-parameter representation is a more suitable choice for high-frequency

designs, we convert (9.73) into a form that replaces the admittances by reflection coeffi-
cients. Besides (9.75) we use
2
in (9.73). Recognizing that Gs can be written as GS = Yo(l - ITS\ )/I1 + rsl2 , the
final result becomes
In (9.77) the quantities F, , R , , and Topt are known. In general, the design engineer
has the freedom to adjust Ts to affect the noise figure. For Ts = Top, we see that the
lowest possible noise figure is achieved, F = F, . To answer the question of how a
particular noise figure, let us say Fk,relates to Ts , (9.77) is put into the form
which on the right-hand side already suggests the form of a circle equation. Introducing
a constant Qk such that
and rearranging terms gives

2
k lroPtl
(1 + ~ ~ ) l- 2r ~~e l{ r~ ~ r + ~ } = Qt (9.80)
Division by ( 1 + Q,) and forming a complete square yields, after some algebra,
This is the required circle equation in standard form that can be displayed as part of the
Smith Chart:
with the circle center location dFkdenoted by the complex number

R
= dFk
d ~ k
+ JdFk
I = -1 opt
1 + Qk
and the associated radius
There are two noteworthy conclusions that can be drawn from (9.83) and (9.84):
The minimum noise figure is obtained for Fk = Frnin,which coincides with the
location dFk= rapt and radius rFk= 0 .
All constant noise circles have their centers located along a line drawn from the
origin to point T, . The larger the noise figure, the closer the center dFkmoves to
the origin and the larger the radius rFk.
The following example points out the trade-offs between gain and noise figure for
a small-signal amplifier.
& , . w
Example 9-14: Design of a small-signal amplifier for minimum
noise figure and specified gain
Using the same transistor as in Example 9-13, design a low-noise

power amplifier with 8 dB gain and a noise figure that is less than
1.6 dB. Assume that the transistor has the following noise parame-
ters: Frni, = 1.5 dB , R, = 4 R , and rapt = 0.5145 .
Solution: The noise figure is independent of the load reflection

coefficient. However, it is a function of the source impedance. It is
therefore convenient to map the constant gain circle obtained in
Example 9-13 into the rs-plane. Applying equations (9.64) and
Noise Figure Circles 505
(9.65) and values from Example 9-13, we find the center and radius
of the mapped constant gain circle: dgs = 0.29L-18' and
r = 0.18 . A Ts residing anywhere on this circle will satisfy our
s
gam requirement. However, for the noise figure specifications to be
met we have to ensure that Ts resides inside the Fk = 2 dB con-
stant noise circle.
The noise circle center and its radius are computed using
(9.83) and (9.84), respectively. They are listed below together with
the coefficient Q k, see (9.79):
Q k = 0.2, dFk= 0.42L45O, rFk= 0.36
The obtained G = 8 dB and F k = 1.6 dB circles are shown in Fig-
ure 9-17.
Figure 9-17 Constant noise figure circle and constant operating gain circle
mapped into the Ts-plane.
Notice that the maximum power gain is obtained at the point

where rMS = 0.30L-18 (see Example 9- 11 for the detailed com-
putations). However, the minimum noise figure is obtained at
506 Chapter 9 RF Transistor Ampiltler Designs
rs = rapt = 0SL45', which shows for this example that it is

impossible to achieve maximum gain and minimum noise figure
simultaneously. Clearly, some compromises have to be made.
To minimize the noise figure for a given gain, we should pick
the source reflection coefficient as close as possible to the location
of Top while still residing on the constant gain circle. Arbitrarily
choosing T s = 0.29L19" ,the corresponding load reflection coeffi-
cient is found to be rL= 0.45L50° by applying (9.62). The
obtained amplifier noise figure is then computed using (9.77):
The requirements of maximum gain and minimum noise jigure

will always be design trade-offs and cannot be met simultaneously.
9.6 Constant VSWR Circles

In many cases the amplifier has to stay below a specified VSWR as measured at
the input or output port of the amplifier. Typical values range between
1.5 I VSWR 52.5. As we know from our discussion in Chapter 8, the purpose of
matching networks is primarily motivated by the desire to reduce the VSWR at the tran-
sistor. The complication arises from the fact that the input VSWR (or VSWRm) is
determined at the input matching network (IMN), which in turn is affected by the active
device, and, through feedback, by the output matching network (OMN). Conversely, the
output VSWR (or VSWRoMN)is determined by the OMN and, again through feedback,
by the IMN. This calls for a bilateral design approach, as discussed in Section 9.4.3.
To set the stage, let us consider the arrangement depicted in Figure 9-18. The two
VSWRs that are part of an RF amplifier specification are
The reflection coefficients r I M N ,roMN require further clarification. If we concentrate

on r I M N ,it is apparent from Section 9.2.1 that the input power Pi,(under the assump-
tion I?$ = 0 ) can be expressed as a function of the available power PA :
Constant VSWR Circles
Figure 9-18 System configuration for input and output VSWR.
Postulating that the matching network is lossless, the same power is also present at the
input terminal of the active device
in the absence of any matching. Setting both equations equal and solving for lrIMNl
yields
Equation (9.88) can be converted into a circle equation for T s that is centered at loca-
tion dVIMN with radius rVIMNsuch that
where
and
Here the subscript Vm in dvIMN

and rvIMN
is used to denote the VSWR at the
IMN location.
In an identical procedure, the circle equation for the output VSWR is found. The
voltage source is attached to the output side and impedance ZL is treated as source
impedance, whereas Zs is the load impedance. Therefore, in a perfectly analogous way
the output reflection coefficient becomes
We convert (9.92) into a circle equation for TL that is centered at location dvOMN
with
radius rVoMN such that
where
and
r.. -- (1- 2, l ~ o M N l
lroutl
The previous derivations allow us to draw the following conclusions regarding the con-
stant VSWR circles:
For minimum VSWR (on the input side: VSWRIMN= 1 , lrIMNl

= 0 ; on the
output side: VSWRoMN = 1 , IroMNI = 0 ) the circles are located at
*
= Ti, (for the input) and dVoMN = (for the output)
d~+,MNl =o =0 I I ~ ~ ~ ~ I
with both radii equal to zero.
All VSWR circles reside on the line extending from the origin to T,: (input) or
rEut(output).
It is important to be aware of the fact that under bilateral matching the input and
output reflection coefficients are functions of source and load reflection coefficients
(Ts, r L ) . Therefore, the input and output VSWR circles cannot be plotted simulta-
neously, but rather have to be considered one at a time in the iterative process of adjust-
ing Ts and rL.
Constant VSWR Circles 509
c m w -
Example 9-15: Constant VSWR design for given gain and noise
figure
Using the results of Example 9- 14, plot the VSWR,, = 1.5 circle in
the rs-plane as part of the Smith Chart. Plot the graph of
VSWRom as a function of the T s position for a VSWR,, = 1.5.
Find Ts that gives a minimum reflection on the output port of the
amplifier and compute its corresponding gain.
Solution: In Example 9-14 we have found rs = 0.29119" and

rL= 0.45L50° as source and load reflection coefficients that meet
specifications in terms of power gain and noise figure. Since we use
the design based on constant operating gain circles, we obtain a per-
fect match at the input port of the amplifier. However, the output
port is mismatched and the VSWRo,, can be computed from
lrOMNl , which is found from (9.92) in conjunction with (9.9b):
The result is
To improve the VSWRom, we can relax the requirements on

VSWR,, and introduce some mismatch at the input. If we set
VSWRm, = 1.5, the corresponding input VSWR circle can be plot-
ted in the Smith Chart, as shown in Figure 9-19.
The center of the VSWR,, = 1.5 circle and its radius are
found from (9.90) and (9.91), respectively. The numerical values
yield dYIMN = 0.28L19' and rVIMN = 0.18 .
Every point on the VSWRMN = 1.5 circle can be expressed
in the polar form
rs = dvIMN+ rv,,,exp(ja)
where the angle a changes from 0 to 360'. As a changes, we
obtain a changing Ts , which in turn results in a corresponding rout
Figure 9-19 Constant operating power gain, noise figure, and input VSWR circle
in Ts-plane.
and a computed VSWRom. The graph of such a dependence is

shown in Figure 9-20.
As can be observed in Figure 9-20, the V S W , , reaches its
minimum value of 1.37 at approximately a = 85'. The corre-
sponding source and output reflection coefficients, transducer gain,
and noise figure are as follows:
Ts = 0.39L45', r,,, = 0.32L-52'
G , = 7.82 dB, F = 1.51 dB
An improvement in VSWRom has been achieved at the expense of
a reduced gain. If the gain reduction becomes unacceptable, then
both source and load reflection coefficients have to be adjusted
simultaneously.
Many specijkations explicitly prescribe a maximum tolerable

VSWR that the ampl$er design must meet. This becomes particu-
Broadband, High-Power, and Multistage AmplHlers 511
Angle a, deg.
Figure 9-20 Input and output VSWR as a function of angle a
lady important when dealing with system integration issues where

several units are cascaded.
9.7 Broadband, High-Power, and Multistage Amplifiers
9.7.1 Broadband Amplifiers

Many modulation and coding circuits require amplifier with a wide or broad fre-
quency band of operation. From the RF point of view, one of the major problems in
broadband amplifier design is the limitation imposed by the gain-bandwidth product of
the active device. As pointed out in Chapter 7, any active device has a gain roll-off at
higher frequencies due to the base-collector capacitance in the BJTs or the gate-source
and gate-drain capacitances in the FETs. Eventually, as the frequency reaches the transi-
tion frequency f T ,the transistor stops functioning as an amplifier and turns attenuative.
Unfortunately IS2,)seldom remains constant over the wide frequency band of
operation, necessitating compensation measures. Besides forward gain IS211degrada-
tion, other complications that arise in the design of broadband amplifiers include
Increase in the reverse gain ISl2), which degrades the overall gain even further
and increases the possibility for a device to fall into oscillation
Frequency variation of S1 and S22
Noise figure degradation at high frequencies
To account for these effects, two different amplifier design approaches are used:
frequency compensated matching networks and negative feedback. In the subsequent
sections we investigate both design techniques.
Frequency Compensated Matching Networks
Frequency compensated matching networks introduce a mismatch on either the
input or output port of the device to compensate for the frequency variation introduced
by the S-parameters. The difficulty with these types of matching networks is that they
are rather difficult to design and the procedures involved are more an art than a well-
defined engineering approach that guarantees success. Frequency compensated match-
ing networks have to be custom tailored for each particular case.
The following example demonstrates some of the key steps required to design a
frequency compensated matching network.
M& * W
Example 9-16: Design of a broadband amplifier using a fre-
quency compensated matching network
Design a broadband amplifier with 7.5 dB nominal gain and k0.2 dB

gain flatness in the frequency range from 2 GHz to 4 GHz. For the
design use Hewlett-Packard's AT41410 BJT, which is biased with
Zc = 10 mA collector current and Vo = 8 V collector-emitter
voltage. The corresponding S-parameters measured at frequencies of
2, 3, and 4 GHz under unilateral assumption are summarized in
Table 9-4.
Solution: According to the data provided in Table 9-4 the inser-

tion gain of the transistor is IS2,I2 = 11.41 dB at f = 2 GHz,
8.16 dB at 3 GHz, and 5.85 dB at 4 GHz. To realize an amplifier
with a nominal gain of 8.7 dB, source and load matching networks
must be designed that decrease the gain by 2.71 dB at 2 GHz and
increase the gain by 0.54 dB at 3 GHz and 2.85 dB at 4 GHz.
Broadband, Hlgh-Pow, and Multlstagn Ampllflers 513
Table 9-4 Sparameters of AT41410 BJT (I, = 10 mA ,

V, = 8V)
The maximum gain provided by the source and load are found
from (9.35) and (9.36) and are as follows:
f = 2 GHz: Gsm, = 2.02 dB, GLm, = 0.98 dB
f = 3 GHz: Gsm, = 2.11 dB, GLm, = 0.93 dB
f = 4 GHz: Gsm,, = 2.11 dB, GLm, = 1.14 dB
Although for the general case source and load matching networks
would have to be designed, in this example an additional gain Gs
that can be produced by the source matching is already sufficient to
meet the amplifier specifications. Therefore, we concentrate on the
development of the source matching network and leave the output
port of the transistor without any matching network.
Since the output of the transistor is directly connected to the
load, we have GL = 0 dB. The input matching network should pro-
duce an additional gain of (- 3.9 k0.2) dB at f = 2 GHz,
+
(- 0.7 0.2) dB at 3 GHz, and (1.7 k 0.2) dB at 4 GHz. The corre-
sponding constant gain circles are shown in Figure 9-21.
The required input matching network must be capable of trans-
forming points on the constant gain circles in Figure 9-21 to the cen-
ter of the Smith Chart. There are a number of networks that can
accomplish this task. One solution involves a combination of two
capacitors, one in shunt with the transistor and one in series with the
input port of the amplifier, as shown in Figure 9-22. From a known
rs we can compute the transducer gain by setting rL= 0 in (9.10).
We can next find the input and output VSWR. Since TL = 0, the
values for VSWRom is equal to VSWR,,, and is found as
Figure 9-21 Smith Chart design of a broadband amplifier in Example 9-16.
Figure 9-22 Broadband amplifier with 8.7 dB gain and k0.2 dB gain flatness over
a frequency range from 2 to 4 GHz.
For the computation of the VSWR at the input port we use
where IrIMNl
is computed based on (9.88):
Broadband, High-Powar, and Multistage Ampllflers 515
The obtained values are summarized in Table 9-5.

Table 9-5 Parameters of a broadband amplifier
f,GHz rs G,, dB VSWR,, VSWR,,,
2 0.741-83" 7.65 13.1 2.6

3 0.681-101 7.57 5.3 2.6
4 0.661-112" 7.43 2.0 2.8
As seenfrom the values provided in Table 9-5, gain linearity is

achieved at the expense of signfzcantly higher VSWR.
As demonstrated in Example 9-16, the addition of a frequency compensated

matching network to obtain an improved gain flatness may result in significant imped-
ance mismatch, degrading the amplifier performance. To circumvent this problem, a
balanced amplifier can be employed.
Balanced Amplifier Design
The typical balanced amplifier block-diagram using a 3 dB Lange or hybrid cou-
pler and a 3 dB Wilkinson power divider and combiner are shown in Figures 9-23(a)
and (b), respectively. The input signal power is split into two, amplified, and combined
at the output. A complete discussion of the theory behind the operation of couplers and
power dividers is given in Appendix G.
Let us first discuss the operation of the balanced amplifier in Figure 9-23(a). Here
the input power launched into port 1 of the input coupler is equally divided in magni-
tude, but with a 90" phase shift between ports 2 and 3. No power is present at port 4.
The output coupler combines the output signals of amplifiers A and B by introducing an
additional 90" phase shift, thus bringing them in phase again. We denote the S-parame-
A A A A
ters of amplifierA as Sll , SI2, S21, S22,and the corresponding S-parameters of ampli-
fier B with superscript B. The equations that relate the S-parameters of the entire
amplifier to the S-parameters of individual branches are as follows
nnrt 1 nnrt 7
(a) Balanced amplifier using 3 dB coupler
h/4 transformer
ut
(b) Balanced amplifier using 3 dB Wilkinson power divider and combiner

Figure 9-23 Block diagram of a balanced broadband amplifier.
where coefficients 112 take into account the 3 dB attenuation, and the minus sign is due
to the 90" phase shift at port 3 that is traversed twice, adding up to 180".
If the amplifiers in the two branches are identical, then lSlll = = 0 and the
forward and reverse gain of the balanced amplifier are equal to the corresponding gains
of each branch.
-
Broadbond, High-Power, and Multl8taga Ampllflers 517
The operation of the balanced amplifier with Wilkinson power dividers [see Fig-
ure 9-23(b)] is identical. The only difference compared to the power divider is that the
signals are in phase, and we need to add additional h/4 transformers to produce a 90"
phase shift between branches.
The main advantages of balanced amplifiers are that they possess very good
impedance match at the input and output ports (provided that the amplifiers in both
branches have similar characteristics), and one of the two amplifiers can continue oper-
ating even if the other branch should fail completely. The chief disadvantages of bal-
anced amplifiers include increased circuit size and a reduction in frequency response
introduced by the bandwidth of the couplers.
Negative Feedback Circuits
The alternative to frequency compensating networks is the use of negative feed-
back. This allows a flat gain response and reduces the input and output VSWR over a
wide frequency range. An additional advantage of the negative feedback is that it makes
the circuit less sensitive to transistor-to-transistor parameter variations. The disadvan-
tage of such circuits is that they tend to limit the maximum power gain of the transistor
and increase its noise figure.
The term negative feedback implies that part of the signal from the output of the
transistor is coupled back to the input with opposite phase so that it subtracts from the
input signal, thereby reducing it. If the signals are added in phase, the resulting
response will grow and a positive feedback is obtained. The most general resistive feed-
back circuits for BJT and FET are shown in Figure 9-24, where resistor R1 constitutes
a shunt feedback and resistor R2 a series feedback.
(a) Feedback in BJTs (b) Feedback in FETs

Figure 9-24 Negative resistive feedback circuits.
518 Chapter 9 RF Transistor Arnplmer Daslgns
As discussed in Chapter 7, both circuits in Figure 9-24 at low-frequencies can be

replaced by the equivalent .n -models, as shown in Figure 9-25, where the input resis-
tance r, is equal to infinity for FETs.
Figure 9-25 Low-frequency model of negative feedback circuit.
then r, in Figure 9-25 can be replaced by an open circuit and the h-parameter represen-
tation can be written as
Using the matrix conversion formula from Appendix D, we find the corresponding
S-parameter representation
1
[S] = -
A
where
Broodband, Hlgh-Power, and Multistage Ampllflers 519
Assuming ideal matching conditions S I 1 = S22 = 0 (i.e., the input and output
VSWRs equal unity) yields the following equation relating the value of the shunt feed-
back resistor to the series feedback resistor R1 :
where the characteristic impedance Zo and transconductance g, are used.

Substituting (9.101) into (9.100) and (9.99) gives
As seen from (9.99) and (9.102), both gain flattening and perfect match can be
achieved by choosing appropriate values for the feedback resistors R1 and R 2 . The
only limitation arises from the requirement that R2 in (9.101) must be nonnegative; that
is, there exists a minimum value grnfinthat limits the range of g, to
Any transistor with g, satisfying condition (9.103) can be used in the negative feed-
back configuration shown in Figure 9-24.
The analysis of the feedback circuit is applicable only for ideal devices operated
in the low-frequency range where all reactances are neglected. In practical applications
the presence of the parasitic resistances in the transistor must be taken into account,
resulting in modified values of the feedback resistors. In addition, at FW and MW fre-
quencies the influence of internal capacitances and inductances cannot be neglected,
and additional reactive components in the feedback loops enter the analysis. The most
common practice is to add an inductance in series with the feedback resistor R1 . This is
done to reduce the feedback from higher frequencies and thus compensate for S21-
related roll-off.
The following example demonstrates the use of negative feedback for a broad-
band amplifier design where the feedback resistors are first computed theoretically and
then adjusted using a CAD software package.
520 Chapter 9 RF Tmnslstor AmplHler Dealgna
W & Mw
Example 9-17: Design of a negative feedback loop broadband
amplifier
The BJT BFG403W is biased with VcE = 3 V and Ic = 3.3 mA

(p = 125 ). The corresponding S-parameters in common-emitter
configuration are listed in Table 9-6, where a 500 R resistor has
been added to ensure stability.
Design a broad-band amplifier with G, = 10 dB and a band-
width ranging from 10 MHz to 2 GHz by using a negative feedback
loop.
Table 9-6 S-parameters for the transistor in Example 9-17
Solution: As seen from Table 9-6, the minimum gain of 14.2dB

is attained at f = 2GH.2, which is well above the required trans-
ducer power gain of GT = 10dB.
Before continuing our approximate analysis, we have to ensure
that condition (9.103) is satisfied. The value of r, is found to be
r, = P/g, = 984 R , where the transconductance g, is com-
puted as g, = Ic/VT = 0.127 S. Thus, the negative feedback
Broadband, High-Power, and Multlstaga Amplltlers 521
analysis is applicable since condition (9.103) is satisfied even for

R2 = 0 .
The next step involves an estimation of the resistances R1 and
R2. Because the desired gain is G = 10 dB, the low-frequency Szl
coefficient should be equal to -3.16. Here the minus sign is due to
the 180" phase shift of the common-emitter configuration. Substitut-
ing this value into (9.103) yields
R1 = Zo(l -S2,) = 208 SZ
Applying (9.101), we compute the value for the series feedback
resistor R2 :
The resulting insertion gain of the feedback network is listed in the

second column of Table 9-7. It is observed that the negative feed-
back makes the gain response of the amplifier more uniform at the
lower frequencies, unfortunately at too low a level. The discrepancy
between the expected gain of 10 dB and the obtained value of
(S2,(2= 7.5 dB is largely due to the fact that we neglected all para-
sitic resistances in the transistor. Such parasitics include the base
resistance that is connected in series with r , and thus reduces the
effective transconductance g m . Furthermore, the emitter resistance,
which is in series with R2, has to be subtracted from the obtained
value of R2.
Optimization of the circuit for frequencies up to 500 MHz
using CAD tools results in the following modified values of the
feedback resistances: R1 = 276 R and R2 = 1.43 R . The corre-
sponding insertion gain is listed in the third column of Table 9-7.
As observed from Table 9-7, these new values for the feedback
resistances bring the transistor gain closer to the 10 dB specification
at lower frequency, but it degrades quickly as the frequency
increases. This indicates that a R1 = 276 R feedback resistor is too
small at those frequencies and has to be increased. This can be done
by connecting an additional L1 = 4.5 nH inductor in series with
the resistor R, (the value of L1 is predicted by a separate CAD
optimization procedure).
522 Chapter 9 RF Transistor Ampllfler Deslgns
Table 9-7 Insertion gain of the feedback amplifier
The resulting gain is listed in the last column in Table 9-7. As

seen from the values presented, the addition of an inductor flattens
the frequency response and improves the gain flatness to better than
0.1% over the entire bandwidth.
As the frequency increases, the negative feedback design

approach becomes increasingly prone to parasitic injuences. Above
approximately 5 GHz, this lumped element method begins to break
down.
9.7.2 High-Power Amplifiers

Thus far we have discussed the design of amplifiers based on linear, small-signal
S-parameters. When dealing with high-power amplifiers, however, a small-signal
approximation is usually not valid because the amplifier operates in a nonlinear region
and large-signal S-parameters or impedances have to be obtained to conduct the appro-
priate design. Small-signal S-parameters can still be used when designing a Class A
Broadband, High-Power, and Multistage Amplltiers 523
amplifier. Here the signal amplification is largely restricted to the linear region of the
transistor. However, the small-signal S-parameters become progressively unsuitable for
Class AB, B, or C amplifiers, which operate in the saturation region.
One of the important characteristics of a high-power amplifier is the so-called
gain compression. As the input signal to the amplifier approaches the saturation
region, the gain begins to fall off, or compress. The typical relationship between input
and output power can be plotted on a log-log scale, as shown in Figure 9-26.
Figure 9-26 Output power of the amplifier as a function of input power.
At low drive levels, the output is proportional to the input power. However, as the
power increases beyond a certain point, the gain of the transistor decreases, and eventu-
ally the output power reaches saturation. The point where the gain of the amplifier devi-
ates from the linear, or small-signal gain by l dB is called the l dB compression point
and is used to characterize the power handling capabilities of the amplifier. The gain
corresponding to the 1 dB compression point is referred to as GldB and is computed as
GldB = GO- 1 dB , where Go is the small-signal gain. If the output power Po,, laat
the 1 dB compression point is expressed in dBm, it can be related to the corresponding
input power Pin, as
Another important characteristic of an amplifier is its dynamic range labeled dR.

The dynamic range signifies the region where the amplifier has a linear power gain
524 Chapter 0 RF Tnnslstor Amplifier Designs
expressed as the difference between Pout, ldB and the output power of the minimum
detectable signal Pout,mds. The quantity Pout, ,d, is defined as a level X dB above the
output noise power P,, out.In most of the specifications, X is chosen to be 3 dB. The
output noise power of an amplifier is given as
P,, out = kTBGoF (9.105)
which, if expressed in dBm, can be cast in the form
P , ,,(dBm) = lOlog(kT) + lOlogB + Go(dB) + F(dB) (9.106)
where lOlog(kT) = -173.8 dBm at T = 300°K and B is the bandwidth.
As with any nonlinear circuit, high-power amplifiers create harmonic distortions
(multiples of the fundamental frequency). They appear as a power loss in the funda-
mental frequency. In general, Class A operation produces the lowest distortion figures.
For higher-power applications where Class A operation is not feasible, due to low effi-
ciency, Class AB push-pull amplifiers are employed to achieve nearly comparable dis-
tortion levels. Harmonic distortion is specified as the harmonic content of the overall
output expressed in dB below the output power at the fundamental frequency.
An undesirable property of power amplifiers is the occurrence of so-called inter-
modulation distortion (IMD). Although present in any amplifier (like harmonic distor-
tion) it is most prominent in the high-power region of an active device where the
nonlinear behavior has to be taken into account. Unlike harmonic distortions, IMD is
the result of applying two unmodulated harmonic signals of slightly different frequen-
cies to the input of an amplifier and observing the output, as shown in Figure 9-27.
2~'-"6 2f, -A
Figure 9-27 Observing the intermodular distortion of an amplifier.
Due to third-order nonlinearities of the amplifier, the input signals Pin(f and
Pin(f 2) create, besides the expected output signals Pout(f and Pout(f 2), additional
Broadband, High-Power, and MultlstagaAmplifiers 525
frequencies POut(2 f - f 2) and POut(2 f - f . The additional frequency components

can serve a desirable purpose when dealing with mixer circuits (see Chapter 10). How-
ever, for an amplifier one would like to see these contributions to be as small as possi-
ble. The difference between the desired and the undesired power level (in dBm) at the
output port is typically defined as IMD in dB; that is,
In Figure 9-28 the output powers Pout(f 2) and POut(2 ,

f - f are plotted versus
the input power Pin(f ,) on a log-log scale. In the region of linear amplification, the
output power Pout(f ,) increases proportionally to the input power Pin(f .J,let us say
Pout(f ,) = aPin(f 2) . However, the third order product POu,(2f - f increases pro-
,
portional to the third power [i.e., POJ2 f - f l ) = a3pi,,( f ,)] Thus, the IMD is
reduced in proportion to the inverse square of the input power. Projecting the linear
region of Pout(f 2) and POu,(2f - f results in a fictitious point called the intercept
point (IP). In practice, if higher than third order products can be neglected, the IP
becomes a fixed point, independent of the particular power gain of the amplifier. This
allows us to us the IP as a single number to quantify the IMD behavior.
Figure 9-28 Recording of IMD based on input-output power relation.
Also shown in Figure 9-28 is a quantity called spurious free dynamic range, df ,
which is defined as
Qpical values for a MESFET are Pin,,,, = -100 dBm, IP = 40 dBm, and
df = 85 dB.
9.7.3 Multistage Amplifiers

A multistage amplifier circuit should be considered if the power gain requirement
of the amplifier is so high that a single stage may not be able to achieve it. A typical
example of a dual-stage BJT amplifier is shown in Figure 9-29.
Figure 9-29 Dual-stage transistor amplifier.
Besides the typical input and output matching networks (MN1 and MN3), this
configuration features an additional so-called interstage matching network (MN,)
for matching the output of stage 1 with the input of stage 2. In addition to providing
appropriate matching, MN, can also be used to condition the gain flatness.
Under the assumption of optimally matched and lossless networks, let us sumrna-
rize the most important dual-stage performance parameters. The total power gain G,,,
of a dual-stage amplifier under linear operating conditions results in a multiplication of
the individual gains G1 and G2,or in dB
An increase in gain performance is unfortunately accompanied by an increase in the

noise figure, as discussed in Appendix H. Specifically, if F and F2 denote the noise
figures associated with stages 1 and 2, we obtain a total noise figure
In addition, if the minimal detectable signal Pin,mds at 3 dB above thermal noise at the
input is given by Pi,, mds = kTB + 3 dB + F, , the minimal detectable output power
Pout, mds
'out, mds (dBm) = kTB(dBm) + 3dB + F,,(dB) + Gtot(dB) (9.1 11)
Broadband, High-Power, and Multistage Amplitiers 527
The dynamic properties are also affected. For instance, Rhode and Bucher (see Further
Reading) have shown that the previously mentioned third-order intercept point changes to
where ZP1 and IP2 are the third order intercept points associated with stages 1 and 2.
Finally, the total spurious-free dynamic range dftot is approximately
dftot(dBm) = IPtot(dBm) - Pout,&(dBm) (9.1 13)
Equation (9.1 13) also reveals that the addition of a second stage reduces the total
dynamic range.
c & M w
Exampleg-18: Transistor choices for multistage amplifier
design
Design an amplifier with Pout,dB = 18 dBm and a power gain not

less than 20 dB. Using the transistor choices listed in Table 9-8,
which shows pertinent characteristics at the operating frequency of
f = 2 GHz, determine the number of stages for the amplifier and dis-
cuss the choice of an appropriate transistor for each stage. In addi-
tion, estimate the noise figure Fto,and the third-order intercept point
IPtotof the amplifier.
Table 9-8 Transistor characteristicsfor Example 9-18.
Transistor F[dBl G,,,[dBl l d ~ [ ~ IP[dBml

Pout, ~ ~ l
BFG505 1.9 10 4 10
BFG520 1.9 9 17 26
BFG540 2 7 21 34
Solution: Since the output power should be 18'dBm, the only

transistor choice for the output stage of the amplifier is BFG540.
528 Chapter 9 RF Tmnslstor Arnpl#er De8lgns
Because the output power of the amplifier Pout,ldB= 18 dBm is

much lower than Pout,ldBof the BFG540, it can operate at maximum
gain of G = 7 dB. This means that the remaining stages of the ampli-
fier must be able to provide at least 20 dB - 7 dB = 13 dB of gain.
Thus, our amplifier should have at least three stages.
For the last stage to have 18 dBm output power, the second-
stage transistor should be able to produce a power level of
POUt2,dB = 18 dBm - 7 dBm = 11 dBm, which eliminates BFG505
from the list of possible candidates. Since the BFG540 has a much
higher power handling capability than necessary for the second
stage, we choose BFG520.
Due to the fact that Pout,,dB = 11 dBm is much lower than the
1-dB compression power of the BFG520, the second-stage transistor
will also operate well below the compression point and the maxi-
mum gain will be equal to G, = 9 dB. Therefore, the transistor
in the first stage has to have a minimum gain of G = 13 dB - 9 dB =
4 dB and be able to provide Pout, = 11 dBm - 9 dB = 2 dBm. Thus,
the BFG505 is more than adequate for the task with Pout, = 2 dBm
and G1 = 4 dB. The input power to the amplifier is then
Pi, = -2 dBm .
As shown in Appendix H, the noise figure of the entire ampli-
fier is computed as
and is minimized if the gain of the first stage is high. The BFG505
cannot provide a gain higher than 6 dB because in this case (for a
given Pi,) it reaches the compression point. This difficulty is avoided
if the BFG520 is used as the first stage. We can design the first stage
for maximum gain and the second stage for necessary power to drive
the output transistor. We can also adjust the gains of the individual
stages so that none of the transistors reaches the compression point.
The block diagram of the resulting amplifier is shown in Figure
9-30, where the gain of each stage is chosen according to the preced-
ing discussion. The noise figure of this amplifier is predicted as
Summary
Figure 9-30 Block diagram of a three-stage amplifier.
The output power at the third-order intercept point is calculated

using (9.112) and modified for a three-stage amplifier
where the preceding formula was obtained from (9.112) by first

computing the IP of the first two stages and then resubstituting it
into (9.112).
The above analysis is actually one of thejrst steps required in

an amplijier design process. Here the crucial steps of picking suit-
able transistor types and deciding on the number of stages are
made. They then become the starting point of a detailed perfor-
mance analysis.
9.8 Summary
This chapter deals with a broad spectrum of amplifier design concepts. First, the
various power relations are defined. Specifically, the transducer power gain
as well as the available and operating power gains are of key importance. We next
establish the various input and output stability circle equations and examine the mean-
ing of unconditional stability. Specifically, the factor
530 Chapter 9 RF Tmndstor Ampllfler Designs
is employed to assess the unconditional stability of an active device. If the transistor

turns out to be unstable, additional series or shunt resistances can be used to stabilize
the device. Next the constant unilateral gain circles are established and displayed in the
Smith Chart. The location and radius equations
provide insight as to where certain constant gain values are located under unilateral
design conditions (inverse power gain is assumed negligible). The error committed by
using the unilateral design approach over the bilateral method is quantified through the
unilateral figure of merit. If the unilateral approach turns out to be too imprecise, a
bilateral design has to be pursued, leading to the simultaneous conjugate matched
reflection coefficients ( r M S ,rML
) at the input and output ports. The optimal matching
rLs = sll+ S 1 2 S 2 1 r ~ ~ and rL,= S2, + S 1 2 S 2 1 r ~ ~

- '2zrML -'1lrMs
results in amplifier designs with maximum gain. Starting from the operating power gain
expression, circles of constant gain under optimal source matching are derived. Alter-
natively, starting with the available power gain expression, circles of constant gain
under optimal load matching are derived.
We then investigate the influence of noise generated by an amplifier. Using the
noise figure of a generic two-port network
circle equations for the Smith Chart are computed. The noise figure circles can be used
by the circuit designer to make trade-offs with the previously conducted constant gain
analysis.
An investigation into reducing the VSWR as part of various input and output
matching network strategies results in an addition set of circle equations that quantify
the VSWR at the matching network ports:
Further Reading 531
Combining the various circle representations permit the small-signal amplifier design
based on constant operating gain, noise figure, and VSWR circles, jointly displayed in
the Smith Chart.
For broadband design, we discuss the need to develop frequency compensated
matching networks in an effort to widen the operational frequency range. The use of
negative feedback loops is introduced as a way to flatten the power gain over the broad-
band frequency range.
In high-power amplifier applications issues related to the output power compres-
sion are of major concern since they limit the dynamic range of amplification. An
important figure of merit is the 1-dB compression point:
Po", ,d,(dBm) = G,(dB) - 1 dB + Pin,l,B(dBm)
Furthermore, an additional undesirable property is the occurrence of intermodular dis-
tortion due to the presence of nonlinearities. Finally, the influences of power compres-
sion, noise figure, and gain are investigated in the context of a multistage amplifier
design.
Further Reading
I. Bahil and P. Bhartia, Microwave Solid State Circuit Design, John Wiley, New York,
1988.
G. Gonzalez, Microwave TransistorAmpl$ers, Analysis and Design, Prentice Hall,
Upper Saddle River, NJ, 1997.
K. C. Gupta, R. Garg, and R. Chada, Computer-Aided Design of Microwave Circuits,
Artech, Dedham, MA, 1981.
Hewlett-Packard, RF Design and Measurement Seminar, Seminar Notes, Burlington,
MA, 1999.
Hewlett-Packard, S-Parameter Techniques for Faster and more Accurate Network
Design, Application Notes 95- 1, 1968.
H. Krauss, C. Bostian, and F. Raab, Solid Radio Engineering, John Wiley, New York,
1980.
S. Y. Liao, Microwave CircuitAnalysis andAmpl$er Design, Prentice Hall, Englewood
Cliffs, NJ, 1987.
S. J. Mason, "Power Gain in Feedback Amplifiers, IRE Trans., Vol. 1, pp. 20-25, 1954.
532 Chapter 9 RF Transistor ArnpiMler Designs
D. Pozar, Microwave Engineering, John Wiley, New York, 1998.

B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River, NJ, 1998.
U. L. Rohde and T. T. N. Bucher, Communication Receivers, Principle and Design,
McGraw-Hill, New York, 1988.
J. M. Rollett, "Stability and Power-Gain Invariants of Linear Ro-Ports," IRE Trans.,
Vol. 9, pp. 29-32, 1962.
G. D. Vendelin, Design of Amplijiers and Oscillators by the S-Parameter Method, John
Wiley, New York, 1982.
Problems
9.1 The available power of an RF source driving an amplifier connected to load
Z, = 80 Q can be represented as
Based on the signal flow graph shown in Figure 9-2(b),

(a) Find the power to the load PL in terms of TL, Ts , and b, .
(b) For Zs = 40 R , Z , = 50 R , V, = 5 VLOO,find the available power
PA and the power at the load PL.
9.2 Use the signal flow graph in Figure 9-2(b) and establish the validity of equa-
tion (9.8) in Section 9.2.2.
9.3 An amplifier is characterized by the following S-parameters:

Sll = 0.781-65" ,S2, = 2.2L78" ,S12 = 0.111-21°, S2, = 0.91-29'.
The input side of the amplifier is connected to a voltage source with
V , = 4VL0°, and impedance Z, = 65 R . The output is utilized to drive
an antenna that has an impedance of ZL = 85 R . Assuming that the S-
parameters of the amplifier are measured with reference to a Zo = 75 i2
characteristic impedance, find the following quantities:
(a) transducer gain GT, unilateral transducer gain GTU,available gain GA,
operating power gain G
(b) power delivered to the load P, ,available power P A ,and incident power
to the amplifier Pint
Problems
9.4 A FET is operated at f = 5.5 GHz and under bias conditions

V,, = 3.2 V and ID = 24 mA. The S-parameters are Sll = 0.731176',
S2, = 3.32L75', S,, = 0.05L34', S2, = 0.26L-107'. In the absence
of matching networks a load of ZL = 75 i 2 and a source of Zs = 30 R are
attached. Assume Zo= 50 R.
(a) Find GTU, GT, GA, and plot the magnitude of GTU for
10 Q I Z , I 100 n .
(b) Match the input side for the unilateral case and find G,, .
(c) Match both input and output for the unilateral case and compute
G~~ = G ~ ~ m a x .
9.5 Unconditional stability in the complex rout-plane requires that the
ITs/ = 1 domain resides completely within the T o = 1 circle, or
IC,I - rsl < 1 , where
(a) Derive these two equations.

(b) Find the circle equations for CL and rL and show that
ISl2S2,I < 1 - IS22I2
2
9.6 Prove that Isll- s ; ~ A ~ = I S ~+ (1 ~ -SI S ~~ ~ ~~-~1~)~ 1( ~This
~) .S is~ a~ / ~
key identity in the stability factor derivation of Example 9.2.
9.7 A BJT has the following S-parameters (see the table below) as a function of
four frequencies. Determine the stability regions and sketch them in the
Smith Chart.
9.8 The S-parameters for a BJT at a particular bias point and operating fre-
quency are as follows: SI1 = 0.60L157", S21 = 2.18L61°,
Chapter 9 RF Transistor Amplifier Designs
S12 = 0.09L77O, S22 = 0.471-29". Check the transistor stability, stabi-

lize it if necessary, and design an amplifier for maximum gain.
In this chapter we have derived the circle equations for constant operating
power gain. It can be concluded that the maximum gain is obtained when the
radius of the constant gain circle is equal to zero. Using this condition, prove
that the maximum achievable power gain in the unconditionally stable case is
) j c & G- ~km a( x =! b
Is121
where k is the stability factor (k > 1 ).
A BJT is operated at f = 750 MHz (and with the S-parameters given as

follows: S1, = 0.561-78", S2, = 0.05L33', SI2 = 8.64L122', and
S,, = 0.661-42' ). Attempt to stabilize the transistor by finding a series
resistor or shunt conductance for the input and output ports.
In Example 9-2 the stability factor k is derived based on the input stability
circle equation. Start with the output stability circle equation and show that
the same result (9.24) is obtained.
A BJT is operated at f = 7.5 GHz and is biased such that the S-parameter
is given as S, = 0.85L105" . It is assumed that the transistor is uncondi-
tionally stable so that the unilateral approximation can be applied. Find the
maximum source gain and plot the constant source gain circles for several
appropriately chosen values of gs .
A MESFET is used as a single-stage amplifier at 2.25 GHz. The S-parame-

ters at that frequency and under given bias conditions are reported as
S1, = 0.831-132", S12 = 0.03L22", S2, = 4.917 1" ,
S22 = 0.361-82'. For a required 18-dB gain, use the unilateral assumption
by setting SI2 = 0 , and
(a) Determine if the circuit is unconditionally stable.
(b) Find the maximum power gain under the optimal choice of the reflection
coefficients.
(c) Adjust the load reflection coefficient such that the desired gain is real-
ized using the concept of constant gain circles.
A BJT is used in an amplifier at 7.5 GHz. The S-parameters at that frequency

and under given bias conditions are reported as S,, = 0.631-140°,
Problems
S12 = 0.08135", S2, = 5.7L9g0, SZ2= 0.471-57'. The design

requires a 19 dB gain. Use the unilateral assumption and
(a) Find the maximum power gain under the optimal choice of the reflection
coefficients.
(b) Adjust the load reflection coefficient such that the desired gain under
stable operating conditions is realized.
9.15 A small-signal amplifier for a BJT operated at 4 GHz is appropriately biased

and has the following S-parameters: Sll =0.57L-150°,
S12 = 0.12145", S2, = 2.0156', S2, = 0.351-85'. If a unilateral
design approach is pursued, estimate the error involved.
9.16 A BJT with Zc = 10 rnA and V c E = 6 V is operated at a frequency of

f = 2.4 GHz. The corresponding S-parameters are Sll = 0.54L-70°,
S12 = O.O17Ll76", S2, = l.53L91°, and S22 = O.93L-15O. Determine
whether the transistor is unconditionally stable and find the values for source
and load reflection coefficients that provide maximum gain.
9.17 Using the same BJT discussed in the Problem 9.16, design an amplifier
whose transducer power gain is 60% of G,, . In addition, ensure a perfect
match on the input port of the amplifier.
9.18 A MESFET operated at 9 GHz under appropriate bias conditions has the
following S-parameters: Sll = 1.21-60°, S12 = 0.02L0°,
S2, = 6.51115" , and Sz2 = 0.61-35" . Design an amplifier that stays
within 80% of GTUmax.Moreover, ensure that VSWR, = 1.
9.19 In Section 9.4.4 it is mentioned that the constant gain design for a matched
input results in the circle equation
Show that the center d," and radius r," are given by
and
536 Chapter 9 RF Transistor Ampllfler Designs
9.20 For the constant available gain circle 1rs- dgal = r ga [see (9.66)], show
that
- ga(S11- A%,)* dl - 2kgalSl2S2lI + g:1~12~211~

and r,, =
dga 1+ g a ( l s l l 1 2 - ~ ~ ~ 2 ) 11 + ga(lsll12- I A I ~ ) ~
9.21 A BFG197X transistor is biased at VcE = 8 V and Ic = 10 mA and has

the following S-parameters measured at f = 1 GHz: Sll = 0.731176',
S,, = 0.07135', S2, = 3.32L75', and S22 = 0.261107'. Determine
the unilateral figure of merit and compare the transducer gain of the ampli-
fier designed under the unilateral and bilateral assumptions.
9.22 The BFG33 BJT is biased under VcE = 5 V and Ic = 5 mA and has the
following noise and S-parameters:
Design a broadband low-noise amplifier with minimum gain of 10 dB and a

noise figure not exceeding 3.5 dB.
Design a microwave amplifier using a GaAs FET whose S-parameters at

f = 10 GHz are Sll = 0.79L100°, S12 = 0.201-21°,
SZ1 = 6.51-73' , S2, = 0.741152' .Analyze the trade-offs posed by sta-
bility, gain, and VSWRs.
A broadband amplifier with nominal characteristics of VSWR,, = 4,

VSWR,,, = 2.8, and GT = 10 dB is used as part of a balanced amplifier
design. Compute the worst input and output VSWR and the insertion gain of
the balanced amplifier if the values listed can vary by as much as 10%.
In Section 9.7.3 we have listed equation (9.1 12) for the IP definition of a
two-stage amplifier.
(a) Derive a generalized formula for the IP computation of an N-stage
amplifier.
Problems 537
(b) Compute the total IP and the noise figure of the N-stage amplifier
assuming that all stages are identical and have ZP,, = 35 dBm,
F=2dB,andG=8dB.
9.26 Design a 15-dB broadband amplifier using a BJT with feedback loop. Cal-
culate the value of the feedback resistor and find the minimum collector cur-
rent of the transistor. Assume that the amplifier is operated at T = 300" K.
9.27 A transistor has the following S-parameters: Sll = 0.61L152",

S,, = O.lL79", S,, = l.89L55", and S2, = 0.47L-30". Design an
amplifier for minimum noise figure if F ~ =, 3 dB, r, = 0.52L-153",
and R, = 9 a.
9.28 Prove equation (9.113), which states the total spurious-free dynamic range.
9.29 An amplifier has a transducer gain of GT = 25 dB, and a 200 MHz band-
width. The noise figure is given as F = 2.5 dB and the 1 dB gain compression
point is measured as Po,, ldB = 20 dBm. Calculate the dynamic range and
the spurious-free dynamic range of the amplifier if ZP,,, = 40 dBm.
Assume that the amplifier is operated at room temperature.
9.30 An amplifier has a gain of G = 8 dB at 1 GHz and lists a 1 dB compression

point of Po,, dB = 12 dBm and the third order intercept point at IP,, = 25
dBm. Find the third order intercept points for the cascaded amplifier stages 2
and 3. What value of IP,,, is obtained in the limit of an infinite number of
stages?
9.31 Derive a formula for the noise figure of a balanced amplifier. Make the
assumption that the power gains and noise figures of the amplifiers in the
individual branches are GA, GB, and F A , FB ,respectively.Assume that the
balanced amplifier uses 3 dB hybrid couplers at the input and output ports.

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RF Transistor Amplifier

A mplifier designs at RF differ significantly from

9.1 Characteristics of Amplifiers

Figure 9-1 Generic amplifier system.

9.2 Amplifier Power Relations

(a) Simplified schematics of a single-stage amplifier

(b) Signal flow graph

The incident power wave associated with bl ' is given as

This expression makes clear the dependence on T s . If Tin = 0 and T s + 0 it is seen

9.2.2 Transducer Power Gain

The required ratio is therefore given by

Inserting (9.7) into (9.5) results in

Second, using (9.9b) in (9.8) results in the expression

9.2.3 Additional Power Relations

- power available from the amplifier

or, with the aid of (9.1 I),

power delivered to the load - PL -

Combining (9.3), (9.4), and (9.10), we find

An RF amplifier has the following S-parameters: S l l = 0.31-70°,

measured with reference to a Zo = 50 R characteristic impedance,

(a) transducer gain GT, unilateral transducer gain GTU, available

Solution: First we find the source and load reflection coefficients

Using (9.2) in conjunction with (9.1) allows us to find the incident

Often Pi, is expressed in dBm as

It is interesting to point out that the unilateral power gain

9.3 Stability Considerations

9.3.1 Stability Circles

where the circle radius is given by

(a) Output stability circle (b) Input stability circle

When plotted in the T, -plane we obtain a response as schematically shown in Figure

(a) IS22 1 < 1 (b) IS22 1 '1

9.3.2 Unconditional Stability

Chapter 9 RF Translstor Ampilfier Designs

Figure 9-6 Different input stability regions for S221< 1 depending on

Alternatively, unconditional stability can also be viewed in terms of the Ts behavior in

and which possesses a radius of

IS12S2~I < I- 1 ~ 1 1 1 ~ (9.27b)

2ISl2S2,I < 2 - 1 ~ 1 1-1 1~~ 2 2 1 ~

Derive the stability factor k (Rollett factor) from (9.23a).

Solution: Substituting (9.21) and (9.22) into (9.23a) gives

A stability analysis starting from (9.23b) would have resulted

Determine the stability regions of the bipolar junction transistor

Table 9-1 BFG505W Sparameters as a function of frequency

k IAI 'in 'in Cout '-out

0.41 0.69 39.04L108" 38.62 3.56170" 3.03

Figure 9-8 Input a n d output stability circles for BFG505W computed

Investigate the stability regions of a transistor whose S-parameters

Solution: We again compute the values k, [A/, Cin, T i n , Gout,

Usually manufacturers avoid producing transistors with both

9.3.3 Stabilization Methods

> 1 and lrou,l=

(a) Series resistance (b) Shunt conductance

Using the transistor BFG505W from Example 9-3 operated at

Solution: With given S-parameters we can identify the input and

region. Similarly, by tracing a constant conductance circle g' = 2.8

Following an identical procedure we can find a series resistance of

Due to the coupling between input and output ports of the

attempts to avoid resistive elements at the input port since they

Stabilization through the addition of resistors comes at a prize: the impedance