2036 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.

7, JULY 2009

A 36 V Programmable Instrumentation Amplifier

With Sub-20 V Offset and a CMRR in
Excess of 120 dB at All Gain Settings
Viola Schaffer, Martijn F. Snoeij, Member, IEEE, Mikhail V. Ivanov, Member, IEEE, and Dimitar T. Trifonov

Abstract—A 36 V capable programmable gain instrumen- TABLE I

tation amplifier (PGA) is presented with sub-20 V offset, KEY DESIGN GOALS AND SYSTEM REQUIREMENTS
sub-0.2 V C offset drift and a common-mode rejection
(CMRR) that exceeds 120 dB at all gain settings without any
trimming. It is the first 36 V capable precision PGA implemented
in a high-voltage CMOS process, which, in addition, incorporates
several additional functions, such as the detection of input and
output fault conditions, provisions for improving system-level
settling time and an input switch network. All op-amps used in the
PGA employ chopper stabilization with a notch filter that removes
chopping glitches, leading to low offset and drift and no 1
noise. The PGA has a total of 22 gain steps (binary steps between
1/8 to 128, each with an optional multiplying factor of 1 or 1.375)
with better than 0.1% gain accuracy, 0.001% nonlinearity and
sub-2 ppm/C gain drift. The input switch network, in addition to
acting as a 2-channel multiplexer, also enables various system-level
diagnostic features. The PGA is implemented in a 0.35 m CMOS
process with a 36 V extension, has a 3.6 2.4 mm chip area and
consumes a total quiescent current of 3 mA. signals can have up to 10 V of common-mode voltage due
Index Terms—Chopper, CMRR, high-voltage CMOS design,
to long connection lines and different ground potentials, thus
industrial instrumentation, instrumentation amplifier, pro- requiring a common-mode rejection-ratio (CMRR) in excess
grammable gain. of 100 dB up to 100 Hz. Due to the variety of signal sources,
high input impedance is essential, making systems
based on resistive input dividers or on capacitive input sampling
I. INTRODUCTION impractical, due to their low dynamic impedance and input
current draw. To limit the need for system calibration and to
W HILE several application-specific sensor-interface
ICs [1] and integrated smart sensors [2] have been
published and made available commercially in recent years, in
maintain the accuracy over time and temperature, offset drift,
gain drift and nonlinearity need to be minimized, while
industrial signal-acquisition applications there is still a strong noise needs to be eliminated. Table I summarizes the key design
need for a more universal interface solution for various signal goals and system requirements.
sources, supporting an effective resolution of 16 bit and above. The PGAs and IAs currently available for use in industrial
The system implementation of such interface solutions usually signal-acquisition applications can generally be divided into
includes a programmable or fixed gain instrumentation ampli- two categories. A first category is implemented in high-voltage
fier (IA) followed by a high-resolution A/D converter (ADC). (HV) bipolar technology, and use laser-trimming to achieve
This paper focuses on the programmable-gain instrumentation good noise and DC precision [3], [4]. These are capable of
amplifier (PGA) implementation. handling input common-mode and differential voltages of up to
In industrial signal-acquisition applications, apart from 15 V, which are still commonplace in industrial applications.
sensor outputs of a few millivolts, larger signals of up to 10 V The drawbacks of such ICs include limited programmability,
exist, such as those coming from remote transmitter outputs. lack of diagnostics and auxiliary functions, and relatively high
Signals in this wide range need to be extracted and translated cost due to the use of bipolar technology and trimming. At low
without corruption to the low-voltage domain in which most gain settings, most of these ICs also have a limited CMRR of
A/D converters and microcontrollers operate. Moreover, these about 80 dB.
A second category of PGAs is implemented in analog CMOS
technology [5], [6]. This enables the use of dynamic offset can-
Manuscript received November 04, 2008; revised February 26, 2009. Current cellation techniques to improve DC precision, thus eliminating
version published June 24, 2009. the need for trimming. Moreover, the use of CMOS technology
V. Schaffer, M. F. Snoeij, and M. V. Ivanov are with Texas Instruments allows for the integration of a digital interface, additional func-
GmbH, 91058 Erlangen, Germany (e-mail: schaffer_viola@ti.com).
D. T. Trifonov is with Texas Instruments Inc., Tucson, AZ 85706 USA. tionality such as sensor excitation/linearization and the ability
Digital Object Identifier 10.1109/JSSC.2009.2021921 to detect and indicate internal or system level fault conditions.
0018-9200/$25.00 © 2009 IEEE
SCHAFFER et al.: A 36 V PROGRAMMABLE INSTRUMENTATION AMPLIFIER WITH SUB-20 V OFFSET 2037

Since this can make the overall readout system much more ro- in the order of 10 at a reasonable sampling frequency, would
bust against errors, there has been a considerable interest in require an impractically small capacitance, whose high kT/C
PGAs with such additional functionality. However, until now, noise would limit SNR. Similarly, the low input impedance of
the relatively low supply voltages of such CMOS PGAs has amplifiers with input resistor structures (such as a divider) is un-
made them unsuitable for many industrial applications, where acceptable in our application.
an input range of 15 V is required. Recently published Current-Feedback IA architectures [9],
In this paper, we present a precision PGA implemented in a [15], [16] rely on transconductors to convert both the input and
HV-CMOS technology that covers this wide input range and feedback voltages into currents, which are then balanced at a
integrates additional digital control and diagnostics functions virtual ground node. Although such amplifier’s can achieve
while meeting or exceeding the DC specifications of similar high CMRR and low offset, their input range is restricted to tens
bipolar HV IAs and PGAs. of millivolts. Due to transconductor mismatch, they also suffer
This paper is organized as follows. Section II presents the from limited gain accuracy. Although this can be increased
system-level design of the PGA and discusses the architecture, by using transconductance-setting resistors and local feedback
the gain network and the design approach. Section III outlines loops [9], [15], this is at the expense of increased input-referred
the opamps and other key circuit blocks that are critical to the noise.
overall performance of the PGA. In Section IV, the additional One of the most commonly used IA topologies in the in-
functionality that the use of CMOS technology allows, such as dustry is the 3-opamp topology [3], [4], [10]. Having dedicated
error detection circuitry, is described. In Section V, measure- opamps at each input provides a high input impedance for any
ment results are shown. Finally, conclusions are presented in input signal within the opamp’s common-mode input range,
Section VI. along with a continuous signal path to the output. The gain is
usually set at the front-end for best noise, DC and AC perfor-
II. SYSTEM-LEVEL DESIGN mance. Using precision chopper stabilized opamps in such an
IA (Section III-A) makes it possible to meet the offset, offset
A. Overview drift and low frequency noise requirements. This topology was,
This section gives a quick overview of the chosen architecture therefore, chosen as the starting point of the PGA’s architec-
while further details are provided in subsequent sections. The ture. However, the standard 3-opamp structure has two impor-
key design goals that mandated the architectural choices are tant drawbacks. Firstly, the use of voltage gain in the input am-
listed in Table I. The choice of a high-voltage-capable CMOS plifiers reduces the input common-mode voltage range for high
process enabled implementation of the on chip MUX, digital gains, since the outputs of the input amplifiers can clip. Sec-
control and diagnostics features. A current-mode IA structure ondly, the CMRR is determined by the matching between the
was selected for its high input impedance, wide common-mode resistors around the output amplifier, which is typically limited
input range and high CMRR capability. The gain range based to about 80 dB at low gains.
on the full scale (FS) input- and output-range requirements was Another current-mode instrumentation amplifier approach,
chosen to be 1/8 to 128 in binary steps. In order to minimize described in [11]–[14] can provide wide common-mode input
the unused output range between gain steps an intermediate range and high CMRR while maintaining the high input
multiplying factor of 1 or 1.375 was added. The overall PGA impedance, noise and offset/drift advantages of the 3-opamp
contains two input opamps, two output opamps, and two pre- topology. This type of current-mode IA structure is imple-
cision current mirrors each employing two OTAs. To meet the mented in this design as shown in Fig. 1. The input amplifiers
offset, offset drift and low frequency noise requirements, all and induce the input voltage across the programmable
of these amplifiers employ chopper stabilization. Chopping resistor network. The current through this resistor network,
glitches could potentially cause settling and aliasing problems which also flows through the output stage of the input ampli-
in successive parts of the signal chain, especially at high gain fiers, is mirrored by precision bi-directional current mirrors
settings. To avoid this, chopping glitches were filtered out by and fed into the summing nodes of the output opamps and
using the notch-filter approach introduced in [7]. The chopping , where it is converted into a differential output voltage
frequency of 250 KHz was chosen to be high enough to keep via the feedback resistors and . The total PGA gain
the capacitors in the notch-filter small but low enough to avoid where is the fixed gain
large input bias currents and unnecessary amplifier bandwidth implemented in the current mirror and is the transconduc-
requirements. tance set by the resistor network. Through the use of this V-I
and I-V conversion, the input common-mode range becomes
B. IA Architecture independent of the gain, and the CMRR does not depend
This sub-section gives an overview of the instrumentation mainly on resistor matching, but on the mismatch of output
amplifier architectures considered and provides details about resistance, open loop gain and CMRR of the individual input
the architecture used in this PGA. Capacitive sampling tech- amplifiers [13]. Equally important is that this architecture is
niques such as [8] can achieve very good noise and DC per- compatible with the high-voltage/low-voltage (HV/LV) parti-
formance characteristics. However, they provide no continuous tioning method described in Section II-D, leading to a more
signal path to the output and thus may suffer from sub-sampling efficient and compact design. The only disadvantage of the
and aliasing effects. Furthermore, achieving an input impedance approach is that in current-mode systems certain internal nodes
2038 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

(a) (b)

Fig. 1. Block diagram of the presented PGA: (a) the key system-level components and supply domains and (b) a detailed block diagram of the signal path.

need to have a high impedance to assure low distortion, which

is difficult to achieve over frequency because of the necessary
HV cascoding transistors.
Depending on the selected gain, the precision of the input and
output amplifiers and the current mirror affects the overall per-
formance of the PGA to a different degree. While the output
error contribution of the input amplifiers is multiplied by the
PGA gain, the contribution from current mirror and output am-
plifiers is only modified slightly by the chosen output scaling
factor of 1 and 1.375. Therefore, to meet the offset, offset drift,
CMRR, PSRR and low frequency noise requirements at high
as well as low gain settings, each of the opamps was chopper
stabilized.
The DC precision of the current mirrors is critical for the
overall offset, gain accuracy, drift performance and linearity,
especially in lower gain and attenuation modes. The static
matching of a regular or an impedance-boosted current mirror
yields insufficient DC precision. A potential solution would
be to use dynamic element matching, where the input and
output transistors are exchanged to average out their mismatch. Fig. 2. The implementation of the bi-directional current mirrors from Fig. 1.
However, the transistor mismatches would lead to large current
glitches at the mirror output, which would subsequently be
converted into large voltage glitches by the output amplifiers. important to note that while the signal gain of the current mirror
Instead, a resistive current mirror solution was implemented is set by the RP1/RP2 (and RN1/RN2) ratio, the OTA’s noise
as shown in Fig. 2. Referring to the P-side current mirror, the and offset contribution is scaled by the ratio of the output re-
input current flows through RP1 and the feedback loop con- sistor ( or in Fig. 1) to the mirror resistor RP2 (RN2).
sisting of OTA and cascode transistor MPH2 ensures that Therefore, the value of the mirror resistors must be chosen, on
the voltage across RP2 matches that across RP1, resulting in the the one hand, to minimize the voltage drop across them to avoid
mirror output current . The precision input range restrictions and, on the other hand, to minimize the
of this circuit depends on the accuracy of the OTA and the mis- contribution of errors from the current mirror amplifiers, such
match of the resistors. The resistors are implemented using a as offset and noise, to the output. This so-called noise gain is
thin-film layer available on the process, and have sufficient static equal to 5 in this design. The OTA’s offset, offset drift and 1/f
matching when proper precision layout techniques are used. It is noise are minimized by the same chopper stabilization scheme
SCHAFFER et al.: A 36 V PROGRAMMABLE INSTRUMENTATION AMPLIFIER WITH SUB-20 V OFFSET 2039

used for the input and output opamps, and which is described in
Section III-A.

C. Gain Network
To cover full-scale input ranges from 10 mV to 12 V, the
gain range was selected to be 0.125 V/V–128 V/V in binary
steps. These binary steps are implemented by changing the
transconductance of the front-end comprising amplifiers ,
and the resistor network. In addition, to maximize the
signal-to-noise ratio at the output of the PGA, and therefore
relax the requirements of the ADC that typically follows (a)
the PGA in measurement systems, an additional 1 V/V or
1.375 V/V gain factor was realized by scaling the feedback
resistors , .
Programmable transconductance stages typically rely on ei-
ther an R-2R type resistor network (Fig. 3(a)) or on a tapped
resistor string (Fig. 3(b)) to set the transconductance .
When a large number of transconductance steps are required,
the R-2R ladder is compact but, since the input signal voltage
is amplified and the amplifier will have an output swing lim-
itation, places severe limitations on the common-mode input
range (CMIR). This approach also limits the signal bandwidth
(b)
according to the gain-bandwidth relationship typically associ-
ated with voltage feedback. The tapped resistor string approach Fig. 3. Commonly used transconductance resistor networks based on (a) an
can have a much improved CMIR performance if the unused re- R-2R ladder and (b) the addition of series resistors.
sistors to the left of the selected tap point switches in use are
shorted out as shown in Fig. 3(b). In this case the voltage gain
to the output of the amplifier is always 1 and the transconduc- D. High-Voltage Design
tance is changed by the total impedance to the right of the se- To be able to handle the various industrial signal levels, the
lected switches. The signal bandwidth is then independent of the primary design goal for the PGA is to be able to operate from
transconductance setting, but the number of resistor segments a 18 V supply, with an input common-mode range of 16 V.
goes up exponentially with the number of transconductance set- The output amplifiers operate at a separate supply voltage of
tings. This costs chip area and complicates layout and metal 3 to 5 V, which is essential to be able to drive a low-voltage
matching without adding significantly to system accuracy. ADC. This output supply voltage can be freely chosen to be
This PGA uses a combination of the two approaches to op- anywhere within the high-voltage supply range. Similarly, the
timize the input range, dynamic performance, resistor area and digital support circuitry also operates at a supply voltage of 3 to
gain error characteristics. This is illustrated in Fig. 4, with the 5 V that can be freely chosen within the high voltage supply
dotted lines indicating the configuration. For higher range. As a result, several analog and digital signal transfers
gains the R-2R type resistor network is used while the lower between these various supply domains on the chip are required.
gains are implemented with a tapped resistor network. By doing In order to meet the input range requirements along with the
this, the CMIR limitations are reduced as the voltage gain to the required digital gate density, a CMOS process is used that has
output of the amplifier is reduced (provided that the series resis- 5 V thin-oxide transistors, thin-oxide transistors with extended
tors to the left of the tap point are shorted as shown). In drains for 36 V operation between drain and source, and thick-
addition, the arrangement lends itself to easier layout and better oxide gate transistors capable of handling 36 V across both
matching performance at the more critical high gain settings. gate-source and drain-source. Unfortunately HV-capable tran-
For lower gain settings the series resistance approach is used, sistors have degraded performance and matching, which makes
therefore the CMIR is not limited and the bandwidth stays con- them unsuitable for use in gain stages of amplifiers and other
stant with changing gains in this region. The total number of parts of the PGA where good analog performance is required.
resistor segments for the network shown (11 steps) is 94 com- However, the process allows the better performing low-voltage
pared to the 1024 that would be required if the whole network CMOS transistors to be isolated from the substrate. Therefore,
was implemented as a series resistor string. This means signif- throughout the design, the approach was to use isolated circuit
icantly less area, along with less layout complexity and the op- blocks, with low-voltage transistors in the signal path, which are
portunity of better optimization, better matching and less series driven by on-chip voltage regulators. This is illustrated in Fig. 5.
(parasitic) metal resistance. Most importantly, an additional de- In addition to the three external (user) supply domains labeled
gree of freedom is obtained, that can be used to optimize the with prefixes HV (high voltage), LV (analog low voltage) and
gain network for system common-mode input range, bandwidth D (digital), there are four internally generated supply domains.
and chip area requirements. The clock conditioning and chopping switches at the input of
2040 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

Fig. 4. The composite transconductance network used in this PGA.

Fig. 5. Supply domain diagram.

the amplifiers , are supplied by floating voltage regula- III. CIRCUIT DETAILS
tors, which are referenced to the input voltage of each ampli-
fier. Furthermore, two additional voltage regulators produce a A. Opamp Topology
voltage 5 V below HV VDD and 5 V above HV VSS, which As discussed in Section II-B, the selected IA topology re-
allows for low-voltage circuit blocks to be supplied between quires a total of 4 opamps and 4 OTAs that all need dynamic
these voltage regulators and one of the high voltage supply rails. offset correction. All of these used the architecture shown in
Signal transfer between these various supply domains is accom- Fig. 6, with the exception of the OTAs, which only drive MOS
plished by current-mode signal processing. The HV transistors gates and so do not require an output stage. The chopped high-
are needed for cascoding only; therefore they do not limit DC gain path with and ensures low offset, while a parallel
precision. feed-forward stage ensures wide bandwidth. A notch-filter
As a result, each input amplifier operates in three different in the high gain path of the amplifier filters out the chopping
supply domains. A floating sub-regulator is used for the first glitches [7]. The resulting opamps have very low offset, no 1/f
stage of the input amplifier. The output current of this stage is noise, low white noise, and no measurable chopping glitches at
cascoded, and passed to a folded-cascode stage, followed by the the output. This chip has proved that this concept can also be
output chopper, notch filter and second gain stage, which all op- applied to a system consisting of multiple amplifiers with ex-
erate at a supply voltage of 5 V above HV VSS. Only the output cellent performance.
stage of the input amplifier operates at the full 36 V supply; the All amplifiers have a bandwidth of 2 MHz. Due to their
current mirrors again operate at 5 V from either the positive or high gain, the input amplifiers have the lowest noise and offset
negative rail. Finally, the output amplifiers are supplied from a voltage requirement of 14 nV/sqrt(Hz) and 14 V. They each
separate low-voltage output supply allowing for easy interfacing consume 250 A. The current mirror and output amplifiers
with low-voltage ADCs. have a relaxed noise and offset requirements of 20 nV/sqrt(Hz)
SCHAFFER et al.: A 36 V PROGRAMMABLE INSTRUMENTATION AMPLIFIER WITH SUB-20 V OFFSET 2041

Fig. 6. Chopper stabilized amplifier structure used in the input and output amplifiers and current mirror OTAs.

Fig. 7. The floating sub-regulator structure.

and 50 V. They consume 50 A and 300 A respectively, is cut off and thus most of the 15 A current from the source I1
with the output amplifier using the extra current for a robust flows through MNH6, increasing the current in MPH3 threefold.
output drive, current limit and diagnostic functions. This guarantees operation to the positive rail. The voltage of the
negative sub-regulator rail is set to about below VREG+
B. Floating Sub-Regulator by MOS diodes MN5, MN6, MN7 and the buffer MN4,MN5,
As was shown in Fig. 5, a floating sub-regulator referenced MPH4,MPH5. Operation to the negative rail is achieved by the
to the input voltage is used for each of the input amplifiers. This addition of the current source I4.
sub-regulator acts as the supply for the chopping switches and
for the clock translator and conditioner. The chosen clock trans- C. Input Stage Configuration
lator requires that the negative supply rail is able to both sink As mentioned previously, high-voltage gate-oxide transistors
and source current and that its positive rail is able to source cur- exhibit significantly higher offset, higher noise and lower gm
rent to a switching circuit. Since the chopping switches are also for comparable area and current levels. Consequently, for
driven from this supply, quick settling of the supply rails is es- best performance, low-voltage transistors must be used in the
sential to avoid coupling into the signal path. signal path, especially for the input devices. Fig. 8 shows the
Fig. 7 shows a simplified schematic of the floating sub-regu- arrangement of the input stage of the input amplifiers ,
lator that generates a floating supply of approximately 3 V be- . Input transistors MIN1 and MIN2 are cascoded by drain
tween rails VREG+ and VREG-, using the input voltage VIN as extended devices MC1 and MC2 to protect them. The reference
a reference point. MPH1 and MN3 set the level of the positive voltage of the cascoding devices follows the common mode
rail VREG+ to above the input voltage, VIN. Throughout voltage, set by the source follower MN and MOS diode MC.
most of the input range, VREG+ is regulated by a fast feed- This also improves common-mode and power-supply rejection
back loop formed by MNH1-MN2. Once the common-mode performance, since the drain-source voltage of the input tran-
sub-regulator approaches the positive rail, a parallel slower loop sistors remains nearly constant over the input common-mode
formed by MPH1, folded cascode MNH6, and the current mirror and supply range. To further increase the CMRR the tail cur-
MPH2 and MPH3 takes over the control. In this condition MN2 rent source employs impedance boosting. The small OTA
2042 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

Fig. 8. The input stage used in the input amplifiers A ,A .

maintains the drain voltage of current mirror transistor MS Fig. 8 shows an example of indicating a positive opamp input
constant at voltage throughout the input common-mode common-mode range violation. Here, the input differential
range. The well connection of the input transistors is buffered pair is biased from the cascoded current source MS-MSC,
by MD to a above the input pair source voltage. This is containing an impedance boost amplifier . The presence of
necessary to prevent the extra capacitance of the isolated well is critical to stabilize the tail current throughout the large
causing unsymmetrical and unpredictable slew behavior. The common mode range of the input amplifiers by maintaining
floating sub-regulator described in the previous section was not a voltage at the drain of MS for any in-range input
used for this purpose in order to minimize the coupling of the common-mode voltage. However, as the common-mode voltage
chopping glitches into the signal path. approaches the positive rail, MSC will eventually enter the
triode region, thereby breaking the feedback loop around ,
IV. AUXILLARY FEATURES which causes the output of to saturate at its low supply. This
A. Detection of Out-of-Range Conditions is a large voltage change that can be easily detected and used
as a logic error flag CMERR. Since it detects the condition in
A common problem in instrumentation amplifiers is detecting
which the differential pair tail current is not regulated anymore,
various conditions that can cause signal corruption even though
this is the first indication of performance reduction due to a
the amplifier’s output remains within its linear range. These
common-mode violation and tracks over process corners and
conditions can include input faults, such as wire breaks and
temperature, eliminating the need for additional design margin.
common-mode range violations, or internal clipping or limiting
Similar functions were incorporated in the internal opamps of
of the input or intermediate stages, etc. System-level indication
the PGA to detect input common mode violations, overloading
and diagnostic capabilities are desired to alert the controller of
of the input, the output being short-circuited or railing and input
a potentially invalid voltage at the amplifier output by means
clamp activation with corresponding digital flags and registers
of a logic signal. A common way to implement this is to add
for system-level diagnostics.
comparators at critical nodes (e.g. inputs and outputs of internal
opamps) [5], [6]. However, there are significant drawbacks to
B. Improving System-Level Settling Time
this approach: such comparators add a lot of circuitry, to the
system, additional reference-generation is needed, and margins Most high-voltage amplifiers incorporate over-voltage pro-
for mismatches, temperature and process variation reduce the tection circuits (clamps) to prevent damage to the precision
usable dynamic range. input transistors during overload conditions and fast input
Significant chip area, accuracy and operating range benefits transients [3], [4]. These clamps draw current from the signal
can be obtained by detecting the overload conditions within source when activated. In a typical multi-channel industrial
the amplifiers at the source of signal corruption, for example application each input channel contains an external RC-filter
when an internal control loop is broken. This approach also used to protect against high frequency disturbances, followed
maximizes the dynamic range and perfectly tracks over temper- by a multiplexer (MUX) connected to the input of our PGA.
ature and process variation. While the best location within the When the MUX channels are switched the input to the amplifier
amplifier and detection circuit approach is unique for each case, can change instantaneously. This would cause the amplifier to
SCHAFFER et al.: A 36 V PROGRAMMABLE INSTRUMENTATION AMPLIFIER WITH SUB-20 V OFFSET 2043

Fig. 10. Settling response to an 8 V step from a voltage source with 10 A

driving capability with and without activating the input current buffer.

Fig. 9. The input switch network including the HV input current buffer, diag-
nostic and calibration switches, and wire-break-detection current sources.

slew and settle to the new input value. During the slew process
the input protection clamps are activated, increasing the input
current and draining charge from the input RC-filter capacitor.
Depending on the filter and signal source impedance, the ca-
pacitor re-charging can lead to a long settling tail, significantly
exceeding the amplifier’s own settling time.
To avoid input current and thus improve system-level settling
time, an input current buffer, BUF was added as illustrated in
Fig. 9. This low precision buffer contains high-voltage MOS
Fig. 11. Chip micrograph.
transistors with thick 36 V gate-oxide that can tolerate large
differential voltages but has degraded offset and noise perfor-
mance compared to the main amplifier. The buffer is switched wire-break at the input can be detected by connecting a small
into the signal path when an overload condition (MUX channel current source to the input pins.
switch) is anticipated. It supplies the current for the clamps of
the precision stage thus preventing current drawn from the input. V. MEASUREMENT RESULTS
The duration of the time for which it stays in the signal path A chip micrograph of the PGA fabricated in a 0.35 m analog
is programmable by the user based on system requirements. In CMOS process with a 36 V extension is shown in Fig. 11. The
Fig. 10 the settling time difference is illustrated when an 8 V chip size is 3.6 2.4 mm. The performance parameters are sum-
input common-mode voltage step is applied to the PGA with marized in Table II. The common-mode rejection ratio (CMRR)
and without the input current buffer. The buffer is removed from distribution of 2000 parts is shown in Fig. 12. The untrimmed
the signal path after the clamp activating condition disappears CMRR exceeds 120 dB ( V/V error) at all gain settings.
and does not affect system accuracy and noise. The input offset voltage is better than 20 V . The
0.1 Hz to 10 Hz peak-to-peak input referred noise is measured
C. Input Switch Network to be 460 nV . Since the noise spectral density
The use of a high voltage CMOS process enables unique func- is flat due to the chopped architecture, the total noise can be
tionality not previously integrated on precision industrial in- reduced by longer integration. At low gain settings, the input
strumentation amplifiers. A typical application system requires referred offset and noise are higher due to the fact that even
calibration and diagnostic modes to measure the input offset though the current mirror provides a signal gain of 1, the noise
and common-mode voltage levels, switch to a system reference of its amplifiers is amplified by a factor 5. Despite the V-I and
source or detect input wire breaks. To accommodate these re- I-V conversions and the multiple supply domains in the signal
quirements, the PGA has an integrated input switch network path, the PGA’s gain linearity is better than 0.001% as illus-
that is shown in Fig. 9. It serves as a 2-channel multiplexer and trated in Fig. 13. The PGA has a gain range of 0.125 V/V to
provides means of reconfiguring the amplifier for system-level 128 V/V in binary steps with an auxiliary gain of 1 or 1.375
trouble-shooting and “housekeeping”. For example, the inputs implemented around the output amplifiers. The less than 0.1%
can be shorted for calibration, the single-ended voltage with re- gain error and less than 2 ppm C gain error drift is determined
spect to ground can be measured at either of the inputs or a by the matching of the untrimmed thin-film resistors. The total
2044 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

TABLE II
SUMMARY OF THE MEASURED PGA PERFORMANCE

The statistical data is from 330 samples measured. The drift statistics are from 80 sam-
ples measured.
These specifications are dominated by the four current mirror amplifiers that are in an
effective noise gain of 5 to the output.

Fig. 13. Measured gain nonlinearity on 15 samples.

Fig. 12. Common-mode rejection ratio performance of 2000 samples measured Table III, the performance of this PGA is compared to that of
inG=1 and G = 128. other general-purpose HV PGAs.

VI. CONCLUSION
quiescent current is 2.2 mA from the high-voltage input supplies A precision 36 V capable programmable gain amplifier has
and 750 A from the low voltage output supplies. The 3 dB been presented that is targeted for industrial signal-acquisition
bandwidth in is 2 MHz. For gains larger than 4, the applications. By using an architecture in which the input voltage
3 dB bandwidth is reduced by half for each 6 dB gain step. Due is converted to a current, which is mirrored by precision current
to the notch filters used in the amplifiers, the chopping glitches mirrors and then converted back into a voltage at the output am-
are practically invisible even in high gain. This is illustrated plifier, an untrimmed common-mode rejection ratio over 120 dB
on the scope photo taken with a differential probe at the two at all gain settings was achieved. Additionally, this architec-
output voltages and the output referred spectral noise density as ture increases the input common-mode range and provides for
is shown in Fig. 14. For this plot, a differential to single-ended level translation between the high-voltage input and low voltage
converter was used with limited CMRR at the chopping fre- output supply domains. The chip is implemented in a 0.35 m
quency, so the actual differential glitches are even smaller. In CMOS process with a 36 V extension. The offset voltage and
SCHAFFER et al.: A 36 V PROGRAMMABLE INSTRUMENTATION AMPLIFIER WITH SUB-20 V OFFSET 2045

[3] PGA205 Data Sheet. Texas Instruments Inc., Dallas, TX, 1993.
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Fig. 14. Output referred spectral plots of the output with G=4 and G = 128 .
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1/f noise were eliminated by the use of chopper stabilization in

all internal amplifiers. Despite using chopping throughout the
signal path, virtually no glitches are visible at the output due to Viola Schaffer was born in Szeged, Hungary, in
the utilization of notch-filters inside the amplifiers. In addition to 1974. She received the M.S. degree in electrical
engineering from the University of Arizona, Tucson,
meeting or exceeding the DC performance of existing HV PGAs in 1999.
and IAs, this PGA provides the convenience of a standard dig- She joined Texas Instruments Inc. (formerly
ital interface and additional functionality such as provisions for Burr-Brown Corporation) in 1998, working as an
analog IC design engineer first in Tucson, AZ,
improving system-level settling time, the detection of internal and since 2001, in Erlangen, Germany. She was
and system-level fault conditions and an input switch network. elected Member Technical Staff in 2005. Relating
Apart from acting as a 2-channel multiplexer, this network also to her work on instrumentation amplifiers, power
amplifiers, and industrial drivers, she holds four
enables various system-level diagnostic features. patents with several applications pending.

ACKNOWLEDGMENT
Martijn F. Snoeij (S’99–M’08) was born in
Zaandam, The Netherlands, in 1977. In 2001, he
The authors would like to thank J. Metzger, J. Doorenbos, received the M.Sc. degree in electrical engineering
S. Gulas, G. Haug, and R. Burt for their design and charac- (cum laude) from Delft University of Technology,
Delft, The Netherlands. In September 2007, he
terization support, and the layout team J. Graner, B. Young, received the Ph.D. degree from the same university
R. Emrich, D. Bellemare, and T. Lis. for his work on CMOS image sensors.
From August to December 2000, he held an intern-
ship at National Semiconductor, Santa Clara, Cali-
fornia, where he worked on precision comparators
REFERENCES and amplifiers. From 2002 to 2007, he was a research
assistant at Delft University of Technology. The main focus of his research was
[1] M. Kämäräinen et al., “A 1.5 W 1 V 2nd-order 16 sensor front-end on the design of improved analog-to-digital converters for CMOS image sen-
with signal boosting and offset compensation for a capacitive 3-axis sors, leading to higher sensor performance and lower power consumption. In
micro-accelerometer,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. March 2007, he moved to Erlangen, Germany, where he is currently working as
578–579. an analog circuit design engineer at Texas Instruments. His professional inter-
[2] Schott et al., “CMOS single-chip electronic compass with microcon- ests include analog and mixed-signal circuit design and sensors.
troller,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2923–2933, Dr. Snoeij was a co-recipient of the ISSCC Jan van Vessem Award for Out-
Dec. 2007. standing European Paper in 2006.
2046 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 7, JULY 2009

Mikhail V. Ivanov (S’96–M’98) was born in St. Pe- Dimitar T. Trifonov was born in Kalofer, Bulgaria,
tersburg, Russia, in 1971. He received the Dipl. Ing. in 1969. He received the M.S. degree in electrical
degree from St. Petersburg Electrical Engineering In- engineering from the Technical University of Sofia,
stitute in 1993 and the M.S.E.E. degree from the Ohio Bulgaria, in 1995.
State University, Columbus, OH, in 1997. From 1995 to 2001, he worked in the telecommu-
Since 1996 he has been with Texas Instruments nication industry. In 2001, he joined Texas Instru-
Inc. (formerly Burr-Brown Corp.) in Tucson, AZ, ments in Tucson, Arizona, where he works on the
and since 2001 in Erlangen, Germany, where he is design of high-performance analog and mixed-signal
currently Group Technical Staff Member and design circuits.
group manager working on the precision linear and
mixed-signal circuits. He holds six patents with
several applications pending.