STD12N60DM2AG

Datasheet

Automotive-grade N-channel 600 V, 0.380 Ω typ., 10 A MDmesh™ DM2

Power MOSFET in a DPAK package

Features
TAB Order code VDS @ TJmax RDS(on ) max. ID

STD12N60DM2AG 650 V 0.440 Ω 10 A

2 3
1

DPAK • AEC-Q101 qualified

• Fast-recovery body diode
D(2, TAB) • Extremely low gate charge and input capacitance
• Low on-resistance
• 100% avalanche tested
• Extremely high dv/dt ruggedness
• Zener-protected
G(1)

Applications
• Switching applications
S(3)
NG1D2TS3Z
Description
This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast-
recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined
with low RDS(on), rendering it suitable for the most demanding high-efficiency
converters and ideal for bridge topologies and ZVS phase-shift converters.
Product status

STD12N60DM2AG

Product summary

Order code STD12N60DM2AG

Marking 12N60DM2
Package DPAK
Packing Tape and reel

DS12209 - Rev 3 - June 2018 www.st.com

For further information contact your local STMicroelectronics sales office.
 STD12N60DM2AG
Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

Drain current (continuous) at Tcase = 25 °C 10

ID A
Drain current (continuous) at Tcase = 100 °C 6.3

IDM (1) Drain current (pulsed) 25 A

PTOT Total dissipation at Tcase = 25 °C 110 W

dv/dt(2) Peak diode recovery voltage slope 50

V/ns
dv/dt(3) MOSFET dv/dt ruggedness 50

Tstg Storage temperature range

-55 to 150 °C
Tj Operating junction temperature range

1. Pulse width is limited by safe operating area.

2. ISD ≤ 10 A, di/dt= 800 A/μs; VDS peak < V(BR)DSS,VDD = 400 V
3. VDS ≤ 480 V.

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 1.14

°C/W
Rthj-pcb (1)
Thermal resistance junction-pcb 50

1. When mounted on 1 inch² FR-4 board, 2oz Cu.

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

IAR (1) Avalanche current, repetitive or not repetitive 2 A

EAS (2)
Single pulse avalanche energy 250 mJ

1. pulse width limited by Tjmax

2. starting Tj = 25 °C, ID = IAR, VDD = 50 V.

DS12209 - Rev 3 page 2/17

 STD12N60DM2AG
Electrical characteristics

2 Electrical characteristics

(Tcase = 25 °C unless otherwise specified)

Table 4. Static

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-source breakdown
V(BR)DSS VGS = 0 V, ID = 1 mA 600 V
voltage
VGS = 0 V, VDS = 600 V 1.5
Zero gate voltage drain
IDSS VGS = 0 V, VDS = 600 V, µA
current 100
Tcase = 125 °C(1)

IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 5 V

Static drain-source on-

RDS(on) VGS = 10 V, ID = 5 A 0.380 0.440 Ω
resistance

1. Defined by design, not subject to production test.

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance - 614 -

VDS = 100 V, f = 1 MHz,
Coss Output capacitance - 32 - pF
VGS = 0 V
Crss Reverse transfer capacitance - 3.7 -

Coss eq. (1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 57 - pF

RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω

Qg Total gate charge VDD = 480 V, ID = 10 A, - 14.5 -

Qgs Gate-source charge VGS = 0 to 10 V (see Figure - 3.8 - nC

14. Test circuit for gate
Qgd Gate-drain charge charge behavior) - 6.2 -

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 300 V, ID = 5 A, - 15 -

RG = 4.7 Ω, VGS = 10 V
tr Rise time - 8 -
(see Figure 13. Test circuit for ns
td(off) Turn-off delay time resistive load switching times - 30 -
and Figure 18. Switching time
tf Fall time waveform) - 9.5 -

DS12209 - Rev 3 page 3/17

 STD12N60DM2AG
Electrical characteristics

Table 7. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 10 A

ISDM (1) Source-drain current (pulsed) - 25 A

VSD (2) VGS = 0 V, ISD = 10 A

Forward on voltage - 1.6 V

trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 70 ns

VDD = 60 V
Qrr Reverse recovery charge - 210 nC
(see Figure 15. Test circuit for
IRRM Reverse recovery current inductive load switching and - 5.9 A
diode recovery times)
trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 110 ns
VDD = 60 V, Tj = 150 °C
Qrr Reverse recovery charge - 460 nC
(see Figure 15. Test circuit for
IRRM Reverse recovery current inductive load switching and - 8.1 A
diode recovery times)

1. Pulse width is limited by safe operating area.

2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.

Table 8. Gate-source Zener diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

Gate-source breakdown
V(BR)GSO IGS = ±250 µA, ID = 0 A ±30 - - V
voltage

The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for
additional external componentry.

DS12209 - Rev 3 page 4/17

 STD12N60DM2AG
Electrical characteristics (curves)

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance

ID GIPG120420181248SOA
GC20460
(A) Operation in this area K
is limited by R DS(on)

tp =10 µs
10 1 100

10 0 tp =100 µs
TJ≤150 °C 10-1
TC=25 °C
VGS=10 V
single pulse

10 -1 tp=10 ms tp =1 ms 10-2
10 -1 10 0 10 1 10 2 VDS (V) 10-5 10-4 10-3 10-2 10-1 tp (s)

Figure 3. Output characteristics Figure 4. Transfer characteristics

ID GIPG120420181034OCH ID GIPG120420181034TCH
(A) (A)
24 24
VGS = 8, 9, 10 V VDS = 15 V
VGS = 7 V
20 20

16 16

12 12
VGS =6 V

8 8

4 4
VGS =5 V
0 0
0 4 8 12 16 VDS (V) 4.5 5 5.5 6 6.5 7 7.5 VGS (V)

DS12209 - Rev 3 page 5/17

 STD12N60DM2AG
Electrical characteristics (curves)

Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance

VGS GIPG120420181035QVG VDS RDS(on) GIPG120420181043RID

(V) (V) (Ω)
VDS VDD = 480 V 0.440
16 400 VGS = 10 V
ID = 10 A
0.420

12 Qg 300
0.400

Qgs Qgd 0.380

8 200

0.360
4 100
0.340

0 0 0.320
0 4 8 12 16 20 Qg (nC) 0 2 4 6 8 10 ID (A)

Figure 8. Normalized gate threshold voltage vs

Figure 7. Capacitance variations
temperature
C IGIPG120420181145CVR
(pF) VGS(th) GIPG120420181044VTH
(norm.)
ID=250 μA
10 3 1.2
CISS

1.0
10 2

0.8
COSS
f = 1 MHz
10 1
CRSS
0.6

10 0
10 -1 10 0 10 1 10 2 VDS (V) 0.4
-75 -25 25 75 125 Tj(°C)

Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized V(BR)DSS vs temperature

RDS(on) GIPG120420181045RON V(BR)DSS GIPG120420181045BDV

(norm.) (norm.)

2.5 1.10
VGS = 10 V ID = 1 mA

2.0 1.05

1.5 1.00

1.0 0.95

0.5 0.90

0.0 0.85
-75 -25 25 75 125 Tj(°C) -75 -25 25 75 125 Tj(°C)

DS12209 - Rev 3 page 6/17

 STD12N60DM2AG
Electrical characteristics (curves)

Figure 11. Output capacitance stored energy Figure 12. Source-drain diode forward characteristics

Eoss GIPG270516FQ6F01FEOS VSD GIPG120420181046SDF

(µJ ) (V)

4 1.2
Tj= -50 ℃

3 1.0
Tj=25 ℃

2 0.8

Tj=150 ℃
1 0.6

0 0.4
0 100 200 300 400 500 600 VDS (V) 0 2 4 6 8 10 ISD (A)

DS12209 - Rev 3 page 7/17

 STD12N60DM2AG
Test circuits

3 Test circuits

Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior

VDD

12 V 47 kΩ
1 kΩ
100 nF
RL
2200 3.3
+ μF μF VDD
VD IG= CONST
VGS 100 Ω D.U.T.

VGS
RG D.U.T. pulse width +
2.7 kΩ
2200 VG
pulse width μF
47 kΩ

1 kΩ

AM01468v1 AM01469v1

Figure 15. Test circuit for inductive load switching and

Figure 16. Unclamped inductive load test circuit
diode recovery times

A A A L
D VD
fast 100 µH
G D.U.T. diode 2200 3.3
S B 3.3 1000 + µF µF VDD
B B
25 Ω D
µF + µF VDD ID
G D.U.T.
+ RG S
Vi D.U.T.
_
pulse width

AM01471v1
AM01470v1

Figure 18. Switching time waveform

Figure 17. Unclamped inductive waveform
ton toff
V(BR)DSS
td(on) tr td(off) tf
VD

90% 90%
IDM

10% VDS 10%

ID 0

VDD VDD VGS 90%

0 10%
AM01472v1
AM01473v1

DS12209 - Rev 3 page 8/17

 STD12N60DM2AG
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.

DS12209 - Rev 3 page 9/17

 STD12N60DM2AG
DPAK (TO-252) type A2 package information

4.1 DPAK package information

Figure 19. DPAK (TO-252) type A2 package outline

0068772_type-A2_rev25

DS12209 - Rev 3 page 10/17

 STD12N60DM2AG
DPAK (TO-252) type A2 package information

Table 9. DPAK (TO-252) type A2 mechanical data

mm
Dim.
Min. Typ. Max.

A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.64 0.90
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 4.95 5.10 5.25
E 6.40 6.60
E1 5.10 5.20 5.30
e 2.159 2.286 2.413
e1 4.445 4.572 4.699
H 9.35 10.10
L 1.00 1.50
L1 2.60 2.80 3.00
L2 0.65 0.80 0.95
L4 0.60 1.00
R 0.20
V2 0° 8°

DS12209 - Rev 3 page 11/17

 STD12N60DM2AG
DPAK (TO-252) type A2 package information

Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm)

FP_0068772_25

DS12209 - Rev 3 page 12/17

 STD12N60DM2AG
DPAK (TO-252) packing information

4.2 DPAK packing information

Figure 21. DPAK (TO-252) tape outline

10 pitches cumulative
tolerance on tape +/- 0.2 mm

Top cover P0 D P2
T tape
E

F
K0 W
B1 B0

For machine ref. only A0 P1 D1

including draft and
radii concentric around B0
User direction of feed

Bending radius
User direction of feed

AM08852v1

DS12209 - Rev 3 page 13/17

 STD12N60DM2AG
DPAK (TO-252) packing information

Figure 22. DPAK (TO-252) reel outline

40mm min.
access hole
at slot location
B

D C

N
A

Tape slot G measured

in core for at hub
Full radius tape start
2.5mm min.width

AM06038v1

Table 10. DPAK (TO-252) tape and reel mechanical data

Tape Reel

mm mm
Dim. Dim.
Min. Max. Min. Max.

A0 6.8 7 A 330
B0 10.4 10.6 B 1.5
B1 12.1 C 12.8 13.2
D 1.5 1.6 D 20.2
D1 1.5 G 16.4 18.4
E 1.65 1.85 N 50
F 7.4 7.6 T 22.4
K0 2.55 2.75
P0 3.9 4.1 Base qty. 2500
P1 7.9 8.1 Bulk qty. 2500
P2 1.9 2.1
R 40
T 0.25 0.35
W 15.7 16.3

DS12209 - Rev 3 page 14/17

 STD12N60DM2AG

Revision history

Table 11. Document revision history

Date Revision Changes

23-Jun-2017 1 First release.

Removed maturity status indication from cover page. The document status is
production data.
Modified features table on cover page.
Modified Table 1. Absolute maximum ratings, Table 3. Avalanche characteristics,
16-Apr-2018 2 Table 4. Static, Table 5. Dynamic, Table 6. Switching times and Table 7. Source-drain
diode.
Updated Section 2.1 Electrical characteristics (curves).
Minor text changes.
27-Jun-2018 3 Updated Section 4 Package information.

DS12209 - Rev 3 page 15/17

 STD12N60DM2AG
Contents

Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1 DPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

DS12209 - Rev 3 page 16/17

 STD12N60DM2AG

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved

DS12209 - Rev 3 page 17/17

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