STM 32 WB 09 Ke

STM32WB09xE
Datasheet
Ultra-low power wireless 32-bit MCU Arm®-based Cortex®-M0+ with Bluetooth®

Low Energy and 2.4 GHz radio solution
Features
• Includes ST state-of-the-art patented technology
• Bluetooth® Low Energy (LE) system-on-chip supporting Bluetooth® 5.3
specifications
– 2 Mbit/s data rate
WLCSP36 (2.83 mm x 2.99 mm)
– Long range (Coded PHY)
– Advertising extensions
– Channel selection algorithm #2
– GATT caching
VFQFPN32 5x5 mm – Direction finding - angle of arrival (AoA)/ angle of departure (AoD)
– Simultaneous connections
– Concurrent link-layer roles
– LE data packet length extension
– LE ping procedure
– Periodic advertising and periodic advertising sync transfer
Product summary
– LE L2CAP connection-oriented channel
STM32WB09KE – LE power control and path loss monitoring
STM32WB09xE
STM32WB09TE – LE channel classification
– Enhanced ATT (EATT)
– Connection subrating
– Broadcast isochronous streams (BIS)
– Connection isochronous streams (CIS)
• Radio
– RX sensitivity level: -97 dBm @ 1 Mbit/s, -104 dBm @ 125 Kbit/s (long
range)
– Programmable output power up to +8 dBm (at antenna connector)
– 128 physical connections
– Data rate supported: 2 Mbit/s, 1 Mbit/s, 500 Kbit/s and 125 Kbit/s
– Integrated balun
– Support for external PA and LNA
– BlueNRG core coprocessor (DMA based) for Bluetooth® Low Energy
time critical operations
– 2.4 GHz proprietary radio driver
– Suitable for systems requiring compliance with the following radio
frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part
15, ARIB STD-T66
– Available integrated passive device (IPD) companion chip for optimized
matching and filtering
DS14210 - Rev 3 - February 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
STM32WB09xE
• Ultra-low power radio performance

– 12 nA in Shutdown mode (1.8 V)
– 0.9 μA in Deepstop mode (with external LSE, radio wakeup source and RAM retained, 1.8 V)
– 1.2 μA in Deepstop mode (with internal LSI, radio wakeup source and RAM retained, 1.8 V)
– 4.9 mA peak current in TX (@0 dBm, 3.3 V)
– 3.6 mA peak current in RX (@ sensitivity level, 3.3 V)
• High performance and ultra-low power 32-bit Arm® Cortex®-M0+ , running up to 64 MHz
• Dynamic current consumption: 15.5 µA/MHz
• Operating supply voltage: from 1.7 to 3.6 V
• -40 ºC to 105 ºC temperature range
• Supply and reset management
– High efficiency embedded SMPS step-down converter with intelligent bypass mode
– Ultra-low power power-on-reset (POR) and power-down-reset (PDR)
– Programmable voltage detector (PVD)
• Clock sources
– 64 MHz PLL
– Fail safe 32 MHz crystal oscillator with integrated trimming capacitors
– 32 kHz crystal oscillator
– Internal low-power 32 kHz RO
• On-chip non-volatile flash memory of 512 Kbytes with page protection against R/W
• On-chip RAM of 64 Kbytes and 4 Kbytes PKA RAM
• One-time-programmable (OTP) memory area of 1 Kbytes
• Embedded UART bootloader
• Ultra-low power modes with or without timer and RAM retention
• Quadrature decoder
• Enhanced security mechanisms such as:
– Flash read/write protection
– SWD disabling
– Secure bootloader
• Security features
– True random number generator (TRNG) compliant with NIST special publication 800-90B
– Hardware encryption AES maximum 128-bit security co-processor
– Hardware public key accelerator (PKA)
– Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)
– CRC calculation unit
– 64-bit unique ID
• System peripherals
– 1x DMA controller with 8 channels supporting ADC, SPI, I2C, USART, LPUART, Timers
– 1x SPI with I2S interface multiplexed
– 1x I2C (SMBus/PMBus)
– 1x LPUART (low power)
– 1x USART (ISO 7816 smartcard mode, IrDA, SPI master and modbus)
– 1x independent WDG
– 1x real time clock (RTC)
– 1x independent SysTick
– 1x 16-bit, four channels general purpose timer
– 2x 16-bit, two channels general purpose timer
– Infrared interface
DS14210 - Rev 3 page 2/72

STM32WB09xE
• Up to 20 fast I/Os
– all of them with wakeup capability
– all of them retain state in low-power mode
– all of them 5 V tolerant
• Analog peripherals
– 12-bit ADC with 8 input channels, up to 16 bits with a down sampler
– Battery monitoring
– Analog watchdog
• Development support
– Serial wire debug (SWD)
– 4 breakpoints and two watchpoints
• All packages are ECOPACK2 compliant
Applications
• Industrial
• Home and industrial automation
• Asset tracking, ID location, real-time locating system
• Smart lighting
• Fitness,wellness and sports
• Healthcare, consumer medical
• Security/proximity
• Remote control
• Assisted living
• Mobile phone peripherals
• PC peripherals
DS14210 - Rev 3 page 3/72

STM32WB09xE
Introduction
1 Introduction
This document provides the ordering information and mechanical device characteristics of the STM32WB09xE
microcontrollers, based on Arm® core.
This document must be read in conjunction with the STM32WB09xE reference manual (RM0505).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32WB09xE errata sheet (ES0576).
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ technical reference manual, available
from the www.arm.com website.
For information on Bluetooth® refer to www.bluetooth.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS14210 - Rev 3 page 4/72

STM32WB09xE
Description
2 Description
The STM32WB09xE is an ultra-low power programmable Bluetooth® Low Energy wireless SoC solution. It
embeds STMicroelectronics’ state-of-art 2.4 GHz RF radio peripherals, optimized for ultra-low-power consumption
and excellent radio performance, for unparalleled battery lifetime.
It is compliant with Bluetooth® Low Energy SIG core specification version 5.3 addressing point-to-point
connectivity and Bluetooth® Mesh networking and allows large-scale device networks to be established in a
reliable way. The STM32WB09xE is also suitable for 2.4 GHz proprietary radio wireless communication to
address ultra-low latency applications.
The STM32WB09xE embeds an Arm® Cortex®-M0+ microprocessor that can operate up to 64 MHz and also the
radio core coprocessor (DMA based) for Bluetooth® Low Energy timing critical operations.
In addition, the STM32WB09xE provides enhanced security hardware support by dedicated hardware functions:
true random number generator (TRNG) supporting NIST special publication 800-90B, security c0-processor for
128-bit AES encryption, CRC calculation unit, 64-bit unique ID, flash memory read and write protection, and a
public key accelerator (PKA).
The PKA supports: modular arithmetic including exponentiation with maximum modulo size of 3136 bits, elliptic
curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of
521 bits CRC calculation unit, security level allowing constant time operations.
The STM32WB09xE can be configured to support standalone or network processor applications. In the first
configuration, the STM32WB09xE operates as a single device running the application code and the Bluetooth®
Low Energy stack.
The STM32WB09xE embeds the following high-speed memory types: 512-Kbyte flash memory, 64-Kbyte RAM, 1-
Kbyte one-time-programmable (OTP) memory area, and 7-Kbyte ROM (ST reserved area).
Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA
channels with a full flexible channel mapping by the DMAMUX peripheral.
The STM32WB09xE embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to
three internal sources, including battery monitoring and a temperature sensor.
The STM32WB09xE has a low-power RTC and one advanced 16-bit timer.
The STM32WB09xE features standard and advanced communication interfaces: 1x SPI-I2, LPUART, 1x USART
supporting ISO 7816 (SmartCard mode), IrDA and Modbus mode, 2x I2C supporting SMBus/PMBus.
The STM32WB09xE operates in the -40 to +105 °C (+125 °C junction) temperature range from a 1.7 V to 3.6 V
power supply. A comprehensive set of power-saving modes enables the design of low-power applications.
The STM32WB09xE integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with
a fixed threshold that generates a device reset when the VDD drops under 1.65 V.
The STM32WB09xE is available in two package types: VFQFPN32 and WLCSP36. Both versions support up to
20 I/Os.
Table 1. STM32WB09xE device features and peripheral counts
Feature STM32WB09KE STM32WB09TE
Flash memory density 512 Kbytes

SRAM0 16 Kbytes
SRAM1 16 Kbytes
SRAM density
SRAM2 16 Kbytes
SRAM3 16 Kbytes
Bluetooth Low Energy Yes
2.4 GHz proprietary radio Yes
1x 16-bit, four channels and
General purpose
2x 16-bit, two channels
Timers
2.4 GHz proprietary radio timer low power 32-bit
SysTick 1
DS14210 - Rev 3 page 5/72

STM32WB09xE
Description
Feature STM32WB09KE STM32WB09TE
SPI 1 with I2S feature
I2C 1
Communication interfaces
USART 1
LPUART 1
RTC Yes
Wake-up pins 20
GPIOs 20
12-bit ADC 1 (8 channels)
True random number generator Yes
AES Yes
Public key accelerator (PKA) Yes
Maximum CPU frequency 64 MHz
Operating temperature -40 ºC to 105 ºC temperature range
Operating voltage 1.7 to 3.6 V
Package VFQFPN32 WLCSP36
Figure 1. STM3WB09xE block diagram
512 KBytes flash

NVIC
SRAM0
JTAG/SWD
Cortex®-M0+
SRAM1
SRAM2
DMA (8 ch)
SRAM3
AHB Lite
DMAMUX
PKA + RAM
RNG
PWRC
MR_BLE
RCC
LSE GPIOA
32 kHz
LSI GPIOB
32 kHz SYSCFG
CRC
ADC
APB
HSE
32 MHz RTC
I2C1
IWDG
RC64MPLL SPI3/I2S3
USART
TIM2
Power supply/POR/ LPUART
BOR/PVD
DT57462V1
TIM16
TIM17
DS14210 - Rev 3 page 6/72

STM32WB09xE
Functional overview
3 Functional overview
3.1 Arm® Cortex®–M0+ core with MPU

The STM3WB09xE contains an Arm® Cortex®-M0+ microprocessor core. The Arm® Cortex®-M0+ was developed
to provide a low-cost platform that meets the needs of CPU implementation, with a reduced pin count and low-
power consumption, while delivering outstanding computational performance and an advanced response to
interrupts. The Arm® Cortex®-M0+ can run from 1 MHz up to 64 MHz.
The Arm® Cortex®-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-
stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small
but powerful instruction set and extensively optimized design, providing high-end processing hardware including a
single-cycle multiplier.
The interrupts are handled by the Arm® Cortex®-M0+ nested vector interrupt controller (NVIC). The NVIC controls
specific Arm® Cortex®-M0+ interrupts as well as the STM3WB09xE peripheral interrupts. With its embedded
Arm® core, the STM3WB09xE family is compatible with all ARM® tools and software.
3.2 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Three masters:
– CPU (Cortex®-M0+) core S-bus
– DMA1
– Radio system
• Nine slaves:
– Internal flash memory on CPU (Cortex®-M0+) S bus
– Internal SRAM0 (16 Kbytes )
– APB0 peripherals (through an AHB to APB bridge)
– APB1 peripherals (through an AHB to APB bridge)
– AHB0 peripherals
– AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)
The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even
when several high-speed peripherals work simultaneously.
DS14210 - Rev 3 page 7/72

STM32WB09xE
Functional overview
Figure 2. Bus matrix
DT57463V1
3.3 Memory protection unit (MPU)
The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or
resources used by any other active task. This memory area is organized into up to 8 protected areas. The
protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the
misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program
accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area settings, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4 Memories
3.4.1 Embedded flash memory

The flash controller implements the erase and program flash memory operation. The flash controller also
implements the read and write protection.
The flash memory features are:
• Memory organization:
– 1 bank of 512 Kbytes
– Page size: 2 Kbytes
– Page number 256
• 32-bit wide data read
• 32-bit wide data write
• Page erase and mass erase
The flash controller features are:
• Flash memory read operations: single read or mass read
• Flash memory write operations: single data write or 4x32-bits burst write or mass write
DS14210 - Rev 3 page 8/72

STM32WB09xE
Functional overview
• Flash memory erase operations: page erase or mass erase

• Page write protect mechanism: 4 variable-size memory segments
3.4.2 Embedded SRAM

The STM3WB09xE has a total of 64 Kbytes of embedded SRAM, split into four banks as shown in the following
table:
Table 2. SRAM overview
SRAM bank Size Address Retained in Deepstop
SRAM0 16 Kbytes 0x2000 0000 Always

SRAM1 16 Kbytes 0x2000 4000 Programmable by the user
SRAM2 16 Kbytes 0x2000 8000 Programmable by the user
SRAM3 16 Kbytes 0x2000 C000 Programmable by the user
3.4.3 Embedded ROM

The STM3WB09xE has a total of 7 Kbytes of embedded ROM. This area is ST reserved and contains:
• The UART bootloader from which the CPU boots after each reset (first 6 Kbytes of ROM memory)
• Some ST reserved values including the ADC trimming values (the last 1 Kbytes of ROM memory)
3.4.4 Embedded OTP

The one-time-programmable (OTP) is a memory of 1 Kbytes dedicated for user data. The OTP data cannot be
erased.
The user can protect the OTP data area by writing the last word at address 0x1000 1BFC and by performing a
system reset. This operation freezes the OTP memory from further unwanted write operations.
3.5 Security and safety

The STM3WB09xE contains many security blocks for the Bluetooth® LE and the host application.
It includes:
• Flash read/write protections over accidental and intentional actions
• As protection against potential hacker attacks, the SWD access can be disabled
• Secure bootloader (refer to the dedicated STM3WB09xE UART bootloader protocol application note
AN5471)
• Customer storage of the Bluetooth® LE keys
• True random number generator (TRNG) supporting NIST special publication 800-90B
• Private key accelerator (PKA) including:
– Modular arithmetic including exponentiation with maximum modulo size of 3136 bits
– Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with
maximum modulo size of 521 bits
– Security level allowing constant time operations
• Cyclic redundancy check calculation unit (CRC)
3.6 Boot modes

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This
modification is performed by programming the REMAP bit in the flash controller.
The following memory can be remapped:
• Main flash memory
• SRAM0 memory
DS14210 - Rev 3 page 9/72

STM32WB09xE
Functional overview
3.7 RF subsystem
The STM32WB09xE embeds an ultra-low power radio, compliant with Bluetooth® Low Energy specification. The
device radio offers 1 Mbit/s and 2 Mbit/s transfer rates as well as long range options (125 Kbit/s, 500 Kbit/s),
supports multiple roles simultaneously acting at the same time as Bluetooth® Low Energy sensor and hub device.
The Bluetooth® LE protocol stack is implemented by an efficient system partitioned as follows:
• Hardware part: BlueCore handling time critical and time consuming Bluetooth® LE protocol parts
• Firmware part: Arm® Cortex®-M0+ core handling non time critical Bluetooth® LE protocol parts
3.7.1 RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in TX, and uses a low IF architecture in RX mode.
Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended
connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies
outside circuitry aimed at harmonic filtering and out of band interferer rejection.
In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the
power amplifier. A linearized, smoothed analog control offers a clean power ramp-up.
In receive mode, the automatic gain control (AGC) can reduce the chain gain at both RF and IF locations, for
optimized interferer rejections. Thanks to the use of complex filtering and highly accurate I/Q architecture, high
sensitivity and excellent linearity can be achieved.
Figure 3. STM3WB09xE RF block diagram
RADIO_TX_SEQUENCE
RADIO_RX_SEQUENCE
DT57464V2
Note:
VFQFPN32: VSS through exposed pad, and VSSRF pins must be connected to ground plane
WLCSP36: VSSRF pins must be connected to ground plane
DS14210 - Rev 3 page 10/72

STM32WB09xE
Functional overview
3.7.2 IPDs for STM32WB09xE

The table below lists the available IPD variants for STM32WB09xE device.
Table 3. IPDs for STM32WB09xE
IPD MCU Package STM32WB09xxx part number
VFQFPN32 STM32WB09KEV
MLPF-NRG-01D3
WLCSP36 STM32WB09TEF
3.8 Power supply management
3.8.1 SMPS step-down regulator

The device integrates a step-down converter to improve low-power performance when the VDD voltage is high
enough. The SMPS output voltage can be programmed from 1.2 V to 1.90 V. It is internally clocked at 4 MHz or 8
MHz.
The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications
where the voltage is low, or where the power consumption is not critical.
Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the VFBSD
pad.
Figure 4. Power supply configuration
DT57465V1
DS14210 - Rev 3 page 11/72

STM32WB09xE
Functional overview
3.8.2 Power supply schemes

The STM3WB09xE embeds three power domains:
• VDD33 (VDDIO or VDD):
– the voltage range is between 1.7 V and 3.6 V
– it supplies a part of the I/O ring, the embedded regulators and the system analog peripherals as
power management block and embedded oscillators
• VDD12o:
– always-on digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is supplied at 1.0 V during low-power mode (Deepstop)
• VDD12i:
– interruptible digital power domain
– this domain is generally supplied at 1.2 V during active phase of the device
– this domain is shut down during low-power mode (Deepstop)
Figure 5. Power supply domain overview
VDDIO VFBSD
SMPS
VREG PAD
VGATEN CMDNO CMDNI VGATEP
LP-Reg MLDO
RFLDOs
VDD12O VDD12I VRF

V33 Domain Always On Interruptible domain
(VDDIO)
Domain (VDD12I)
(VDD12O)
HSI Analog
HSE, LSI, LSE CPU RF
PDR, POR, PVD RF_FSM
BLE_wakeup, BLE
PWRC 33, RTC, WDOG, Peripherals
RCC 33 PWRCo, RCCi
RCCo
DT57466V1
3.8.3 Linear voltage regulators

The digital power supplies are provided by different regulators:
• The main LDO (MLDO):
– it provides 1.2 V from a 1.4-3.3 V input voltage
– it supplies both VDD12i and VDD12o when the device is active
– it is disabled during the low-power mode (Deepstop)
• Low-power LDO (LPREG):
– it stays enabled during both active and low-power phases
– it provides 1.0 V voltage
– it is not connected to the digital domain when the device is active
– it is connected to the VDD12o domain during low-power mode (Deepstop)
• A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block
An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).
DS14210 - Rev 3 page 12/72

STM32WB09xE
Functional overview
3.8.4 Power supply supervisor

The STM3WB09xE device embeds several power and voltage monitors:
• Power-on-reset (POR): during the power-on, the device remains in reset mode if VDDIO is below a VPOR
threshold (typically 1.65 V)
• Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply
voltage (VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always
enabled
• Programmable voltage detector (PVD): can be used to monitor the VDDIO (against a programmed
threshold) or an external analog input signal. When the feature is enabled and the PVD measures a
voltage below the comparator, an interrupt is generated (if unmasked)
DS14210 - Rev 3 page 13/72

STM32WB09xE
Functional overview
3.9 Reset management

The STM3WB09xE offers two different resets:
• The PORESETn: this reset is provided by the low-power management unit (LPMU) analog block and
corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset
impacts all resources of the STM3WB09xE. The exit from Shutdown mode is equivalent to a POR and thus
generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a
threshold value or when the regulator does not provide the target voltage.
• The PADRESETn (system reset): this reset is built through several sources:
– PORESETn
– Reset due to the watchdog
The STM3WB09xE device embeds a watchdog timer, which may be used to recover from software
crashes
– Reset due to CPU Lockup
The Cortex®-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an
unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex®-
M0+
– Software system reset
The system reset request is generated by the debug circuitry of the Cortex®-M0+. The debugger sets
the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system
reset request through the AIRCR can also be done by the embedded software (into the hardfault
handler for instance)
– Reset from the RSTN external pin
The RSTN pin toggles to inform that a reset has occurred
This PADRESETn resets all resources of the STM3WB09xE, except:
• Debug features
• Flash controller key management
• RTC timer
• Power controller unit
• Part of the RCC registers
The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case
of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.
3.10 Operating modes

Several operating modes are defined for the STM3WB09xE:
• Run mode
• Deepstop mode
• Shutdown mode
Table 4. Relationship between the low-power modes and functional blocks
Mode Shutdown Deepstop Idle Run
CPU OFF OFF OFF ON

Flash OFF OFF ON ON
ON/OFF granularity 12
RAM OFF ON/OFF ON/OFF
Kbytes
Radio OFF OFF ON/OFF ON/OFF
ON ( DC-DC ON/ ON ( DC-DC ON/
Supply system OFF OFF
OFF) OFF)
Register retention OFF ON ON ON
HS clock OFF OFF ON ON
LS clock OFF ON/OFF ON ON
DS14210 - Rev 3 page 14/72

STM32WB09xE
Functional overview
Mode Shutdown Deepstop Idle Run
Peripherals OFF OFF ON/OFF ON/OFF

Wake-on RTC OFF ON/OFF ON/OFF NA
Wake-on GPIOs Only from PB0 ON/OFF ON/OFF NA
Wake-on reset pin ON ON ON NA
Only PWRC pull-up/pull-
GPIOs configuration retention ON ON ON
down
3.10.1 Run mode

In Run mode the STM3WB09xE is fully operational:
• All interfaces are active
• The internal power supplies are active
• The system clock and the bus clock are running
• The CPU core and the radio can be used
The power consumption may be reduced by gating the clock of the unused peripherals.
3.10.2 Deepstop mode

The Deepstop is the only low-power mode of the STM3WB09xE allowing the restart from a saved context
environment and the application at wakeup to go on running.
The conditions to enter the Deepstop mode are:
• The radio is sleeping (no radio activity)
• The CPU is sleeping (WFI with the SLEEPDEEP bit activated)
• No unmasked wakeup sources are active
• The low-power mode selection (LPMS) bit of the power controller unit is 0 (default)
In Deepstop mode:
• The system and the bus clocks are stopped
• Only the essential digital power domain is ON and supplied at 1.0 V
• The bank RAM0 is kept in retention
• The bank RAM1, RAM2, RAM3 can be in retention or not, depending on the software configuration
• The low-speed clock can be running or stopped, depending on the software configuration:
– ON or OFF
– Sourced by LSE or by LSI
• The RTC, IWDG and LPUART stay active, if enabled and the low-speed clock is ON
• The radio wakeup block, including its timer, stayS active (if enabled and the low-speed clock is ON)
• Up to 20 GPIOs retaining their configuration:
– I/Os retain the Run mode configuration while in Deepstop mode
• Up to 20 I/Os are able to be in output driving:
– A static low or high level
• Some I/Os can be in output driving:
– The low speed clock (on PA10)
– The RTC output (on PA8)
Possible wakeup sources are:
• The radio block is able to generate two events to wake up the system through its embedded wakeup timer
running on low-speed clock:
– Radio wakeup time is reached
– CPU host wakeup time is reached
• The RTC can generate a wakeup event
• The IWDG can generate a reset event
• The LPUART is able to generate a wakeup event
DS14210 - Rev 3 page 15/72

STM32WB09xE
Functional overview
• All GPIOs can wake up the system

At wakeup, all the hardware resources located in the digital power domain that are OFF during Deepstop mode,
are reset. The CPU reboots. The wakeup reason is visible in the register of the power controller.
3.10.3 Shutdown mode

The Shutdown mode is the least power consuming mode.
The conditions to enter Shutdown mode are the same conditions needed to enter Deepstop mode except that the
LPMS bit of the power controller unit is 1.
In Shutdown mode, the STM3WB09xE is in ultra-low power consumption: all voltage regulators, clocks and the
RF interface are not powered. The STM3WB09xE can enter shutdown mode by internal software sequence. The
only way to exit shutdown mode is by asserting and deasserting the RSTN pin or through a configurable pulse on
PB0 pin.
In Shutdown mode:
• The system is powered down as both the regulators are OFF
• The VDDIO power domain is ON
• All the clocks are OFF, LSI and LSE are OFF
• The I/Os pull-up and pull-down can be controlled during Shutdown mode, depending on the software
configuration
• The only wakeup source is a low pulse on the RSTN pin or a configurable pulse on PB0 pin
• The exit from Shutdown is similar to a POR startup. The PDR feature can be enabled or disabled during
Shutdown
3.11 Clock management

Three different clock sources may be used to drive the system clock of the STM3WB09xE:
• HSI: high speed internal 64 MHz RC oscillator
• PLL64M: 64 MHz PLL clock
• HSE: high speed 32 MHz external crystal
The STM3WB09xE has also a low-speed clock tree used by some timers in the radio, RTC, IWDG and LPUART.
Three different clock sources can be used for this low-speed clock tree:
• Low-speed internal (LSI): low-speed and low drift internal RC with a fixed frequency between 24 kHz and
49 kHz depending on the sample
• Low-speed external (LSE) from:
– An external crystal 32.768 kHz
– A single-ended 32.738 kHz input signal
• A 32 kHz clock obtained by dividing HSI or HSE. In this case, the slow clock is not available in Deepstop
low-power mode
By default, after a system reset, all low-speed sources are OFF.
Both the activation and the selection of the slow clock are relevant during the Deepstop mode and at wakeup as
slow clock generates a clock for the timers involved in wakeup event generation.
The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock
output by this block can be:
• A non-accurate clock when no external XO provides an input clock to this block (HSI)
• An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)
After reset, the CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and
peripherals).
DS14210 - Rev 3 page 16/72

STM32WB09xE
Functional overview
Figure 6. Clock tree
LSI RCO
32 KHz
CLKSLOWSEL
RCC_LCOSEL
CK_RTC,
RCC_LCO CK_WDG,
CK_BLEWKUP
CLK_16MHz/512
CLK_TIM2,
RCC_OSC32_OUT CLK_TIM16,
LSE OSC
32 KHz CLK_TIM17
RCC_OSC32_IN SYSCLKDIV
SYSCLKPRE
OSC_OUT /1, /2, .., /32 CLK_SYS
HSE OSC
32 MHz 1 1 to CPU,
OSC_IN AHB0,
0 0 APB0,
SYSCLKPRE APB1,
/1, /2, .., /64 SRAM,
HSISEL PKA
HSI RCO
HSISEL
+ PLL
64 MHz SYSCLKDIV
LSE 1
CLKANA_ADC CLK_LPUART
0
CLK_SMPS
LPUCLKSEL
CLK_SYS
RCC_MCO /1, /2, .. , /16 HSE /4 1

CLK_SMPS
HSI /2 0
HIS/2048 CLKANA_ADC,
SMPSDIV CLK_USART,
/2 1 CLK_16MHz CLK_I2C,
CLK_BLE16,
RCC_MCOSEL CLK_FLASH,
/4 0 CLK_PWR,
CLK_RNG
1
HSESEL CLKSYS_BLE
0
BLECLKDIV
1 CLK_BLE32,
CLK_32MHz
CLKDIG_ADC
/2 0
HSESEL
CLK_SPI3/I2S
CLK_16MHz
DT57467V2
CLK_SYS
SPI3I2SCLKSEL
It is possible to output some internal clocks on external pads:

• The low speed clocks can be output on the RCC_LCO I/O
• The high speed clocks can be output on the RCC_MCO I/O
This is possible by programming the associated I/O in the correct alternate function.
Most of the peripherals only use the system clock except:
• I2C, USART: they use an always 16 MHz clock to have a fixed reference clock for baud rate management.
The goal is to allow the CPU to boost or slow down the system clock (depending on on-going activities)
without impacting a potential on-going serial interface transfer on external I/Os
• LPUART: always uses a 16 MHz clock or LSE to have a fixed reference clock for baud rate management.
The goal is to allow the CPU to boost or slow down the system clock (depending on on-going activities)
without impacting a potential on-going serial interface transfer on external I/Os.
• SPI: when using the I2S mode, the baud rate is managed through the always 16 MHz or always 32 MHz
clock or system clock (CLK_SYS) to reach higher baud rates. When running in other modes than the I2S,
the baud rate is managed by the system clock. This implies its baud rate is impacted by dynamic system
clock frequency changes.
• TRNG: in parallel with the system clock, the TRNG uses an always 16 MHz clock to generate at a constant
frequency the random number whatever the system clock frequency
DS14210 - Rev 3 page 17/72

STM32WB09xE
Functional overview
• Flash controller: in parallel with the system clock, the flash controller uses an always 16 MHz clock to
generate specific delays required by the flash memory during programming and erase operations for
example
• PKA: in parallel with the system clock, the PKA uses the system clock frequency
• Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a
potential divider (1 or 2 or 4). In parallel, the radio uses an always 16 MHz and an always 32 MHz for
modulator, demodulator and to have a fixed reference clock to manage specific delays
• ADC: in parallel with the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz
3.12 General purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without
pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.13 Direct memory access (DMA)

The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as
memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources
are free for other operations.
The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests.
DMA main features are:
• Eight independently configurable channels (requests)
• Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also
supported on each channel. This configuration is done by software
• Priorities among requests from channels of DMA are software programmable (four levels consisting of very
high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)
• Independent source and destination transfer size (byte, half word, word), emulating packing and
unpacking. Source/destination addresses must be aligned on the data size
• Support for circular buffer management
• Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed
together in a single interrupt request for each channel
• Memory-to-memory transfer (RAM only)
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to SRAMs and APB1 peripherals as source and destination
• Programmable number of data to be transferred: up to 65536
3.14 Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex®-M0+ nested vector interrupt controller (NVIC). NVIC controls specific
Cortex®-M0+ interrupts as well as the STM3WB09xE peripheral interrupts.
The NVIC benefits are the following:
• Nested vectored interrupt controller that is an integral part of the Arm® Cortex®-M0+
• Tightly coupled interrupt controller provides low interrupt latency
• Control system exceptions and peripheral interrupts
• NVIC supports 32 vectored interrupts
• Four programmable interrupt priority levels with hardware priority level masking
• Software interrupt generation using the Arm® exceptions SVCall and PendSV
• Support for NMI
• Arm® Cortex® M0+ vector table offset register VTOR implemented
NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
DS14210 - Rev 3 page 18/72

STM32WB09xE
Functional overview
3.15 Analog digital converter (ADC)

The STM3WB09xE embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to-
digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources
and up to two internal sources.
The ADC main features are:
• Conversion frequency is up to 1 Msps
• Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)
• Up to eight analog single-ended channels or four analog differential inputs or a mix of both
• Temperature sensor conversion
• Battery level conversion up to 3.6 V
• ADC continuous or single mode conversion is possible
• ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the
CPU (ratio adjustable from 1 to 128)
• A watchdog feature to inform when data is outside thresholds
• DMA capability
• Interrupt sources with flags.
3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor is
internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital
value.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by
ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in
read-only mode.
3.16 True random number generator (TRNG)

The true random number generator (TRNG) is a hardware module able to generate a random sequence of 128
bits. The TRNG is based on an analog source of entropy composed by free 9 running ring oscillators. The outputs
of those oscillators are XORed and sampled for providing random bits, which are then processed by a digital
stage.The digital stage is compliant with NIST SP800-90B specifications.
3.17 Timers and watchdog

The STM3WB09xE includes three general-purpose timers, one watchdog timer and a SysTick timer.
3.17.1 General-purpose timers (TIM2, TIM16, TIM17)

There are up to three general-purpose timers embedded in the STM3WB09xE.
Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.
• TIM2
– Full-featured general-purpose timer
– Features four independent channels for input capture/output compare, PWM or one-pulse mode
output
– Independent DMA request generation, support of quadrature encoders
• TIM16 and TIM17
– General-purpose timers with mid-range features:
– 16-bit auto-reload upcounters and 16-bit prescalers
– 1 channel and 1 complementary channel
– All channels can be used for input capture/output compare, PWM or one-pulse mode output
– The timers have independent DMA request generation
– The timers are internally connected to generate an infrared interface (IRTIM) for remote control
DS14210 - Rev 3 page 19/72

STM32WB09xE
Functional overview
3.17.2 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock
and it can operate in Deepstop mode. It can also be used as a watchdog to reset the device when a problem
occurs.
3.17.3 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It
features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
3.18 Real-time clock (RTC)

The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with
programmable alarm interrupt. RTC includes also a periodic programmable wakeup flag with interrupt capability.
The RTC provides an automatic wakeup to manage all low power modes.
Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of
month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also
available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the
programmable alarm sub seconds, seconds, minutes, hours, day, and date.
A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After
power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply
voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-
power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger.
3.19 Inter-integrated circuit interface (I2C)

The STM3WB09xE embeds ONE I2C. The I2C bus interface handles communications between the
microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C bus specification and user manual rev. 5 compatibilities:
– Slave and master modes
– Multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 Kbit/s
– Fast-mode (Fm), with a bitrate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os
– 7-bit and 10-bit addressing mode
– Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
– All 7-bit address acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• Power system management protocol (PMBusTM) specification rev 1.1 compatibility
DS14210 - Rev 3 page 20/72

STM32WB09xE
Functional overview
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be
independent from the PCLK reprogramming
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
3.20 Universal synchronous/asynchronous receiver transmitter (USART)

USART offers flexible full-duplex data exchange with external equipment requiring an industry standard NRZ
asynchronous serial data format. USART can communicate with a speed up to 2 Mbit/s. Furthermore, USART can
detect and automatically set its own baud rate, based on the reception of a single character.
USART peripheral supports:
• Synchronous one-way communication
• Half-duplex single wire communication
• Local interconnection network (LIN) master/slave capability
• Smart card mode, ISO 7816 compliant protocol
• IrDA (infrared data association) SIR ENDEC specifications
• Modem operations (CTS/RTS)
• RS485 driver enable
• Multiprocessor communications
• SPI-like communication capability
High speed data communication is possible by using DMA (direct memory access) for multibuffer configuration.
3.21 Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds one low-power UART, enabling asynchronous serial communication with minimum power
consumption. The LPUART supports half duplex single wire communication and modem operations (CTS/RTS),
allowing multiprocessor communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Deepstop
mode using baud rates up to 9600 baud. The wakeup events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in
Deepstop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption.
Higher speed clock can be used to reach higher baud rates in Run mode.
The LPUART interfaces can be served by the DMA controller.
DS14210 - Rev 3 page 21/72

STM32WB09xE
Functional overview
3.22 Embedded UART bootloader

The STM3WB09xE has a pre-programmed bootloader supporting UART protocol with automatic baud rate
detection. The main features of the embedded bootloader are:
• Auto baud rate detection up to 1 Mbit/s
• Flash mass erase, section erase
• Flash programming
• Flash readout protection enable/disable
The pre-programmed bootloader is an application, which is stored in the STM3WB09xE internal ROM at
manufacturing time by STMicroelectronics. This application allows upgrading the device flash with a user
application using a serial communication channel (UART).
Bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application residing in
flash is launched.
DS14210 - Rev 3 page 22/72

STM32WB09xE
Functional overview
3.23 Inter-IC sound (I2S)

The STM3WB09xE SPI interface: SPI3 supports the I2S protocol. The I2S interface can operate in slave or
master mode with half-duplex communication. It can address four different audio standards:
• Philips I2S standard
• MSB-justified standards (left-justified)
• LSB-justified standards (right-justified)
• PCM standard.
The I2S interfaces DMA capability for transmission and reception.
3.24 Serial peripheral interface (SPI)

The STM3WB09xE has one SPI interface (SPI3) allowing communication up to 32 Mbit/s in both master and
slave modes. The SPI peripheral supports:
• Master or slave operation
• Multimaster support
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• Serial communication with external devices
• NSS management by hardware or software for both master and slave: dynamic change of master/slave
operations
• SPI Motorola support
• SPI TI mode support
• Hardware CRC feature for reliable communication
All SPI interfaces can be served by the DMA controller.
3.25 Serial wire debug port

The embeds an Arm SWD interface that allows interactive debugging and programming of the device. The
interface is composed of only two pins: DEBUG_SWDIO and DEBUG_SWCLK. The enhanced debugging
features for developers allow up to four breakpoints and up to two watchpoints.
3.26 TX and RX event alert

The STM3WB09xE is provided with the RADIO_TX_SEQUENCE and RADIO_RX_SEQUENCE signals which
alert, respectively, transmission and reception activities.
A signal can be enabled for TX and RX on two pins, through alternate functions:
• RADIO_TX_SEQUENCE is available on PA10 (AF2) or PB14 (AF1).
• RADIO_RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2).
The signal is high when radio is in TX (or RX), low otherwise.
The signals can be used to control external antenna switching and support coexistence with other wireless
technologies.
Note: The RADIO_RF_ACTIVITY signal is used to notify if there is an ongoing RF operation ( either TX or RX). It is a
logical OR between the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE. This signal can be used to
enable an antenna switch component when achieving antenna switching during AoA or AoD operation.
DS14210 - Rev 3 page 23/72

STM32WB09xE
Functional overview
3.27 Direction finding

The STM3WB09xE Bluetooth® radio controller supports the angle of arrival (AoA) and angle of departure (AoD)
features by managing:
• the constant tone extension (CTE) inside a packet
• the antenna switching mechanism for both AoA and AoD.
The antenna switching mechanism provides a 7-bit antenna identifier RADIO_ANTENNA_ID[6:0] indicating the
antenna number to be used.
In a AoD transmitter or in a AoA receiver, the radio needs to switch antenna during the CTE field of the packet.
For this purpose, the RADIO_ANTENNA_ID signal can be enabled on some I/Os, by programming them in the
associated alternate function. This signal needs to be provided to an external antenna switching circuit, since
RADIO_ANTENNA_ID[0] is the least significant bit and RADIO_ANTENNA _ID[6] the most significant bit of the
antenna identifier to be used.
DS14210 - Rev 3 page 24/72

STM32WB09xE
Pinout, pin description and alternate functions
4 Pinout, pin description and alternate functions
4.1 Pinout/ballout schematics

The STM3WB09xE comes in two package versions: WLCSP36 offering 20 GPIOs, and VFQFPN32 offering 20
GPIOs.
Figure 7. VFQFPN32 pinout
VDD1 PB4 PB5 RSTN VCAP VFBSD VSS VLXSD
32 31 30 29 28 27 26 25
PB3
1 24 VDDSD
PB2 2 23 PB6
PB1 3 22 PB7
PB0 4 21 PB12/RCC_OSC32_OUT
GND
pad PB13/RCC_OSC32_IN
PA3 5 20
PA2 6 19 PB14
PA1 7 18 PB15
PA0 8 17 OSCIN
9 10 11 12 13 14 15 16
PA8 PA9 PA10 PA11 VDD2 RF1 VDDRF OSCOUT
DT57468
1. The above figure shows the package top view.
DS14210 - Rev 3 page 25/72

STM32WB09xE
Figure 8. WLCSP36 ballout
1 2 3 4 5 6 7
A4
A A2
VSSSD
VDDA
VCAP
A6
VDD2
B B1
VDDSD
B3
VFBSD
B5
RSTN
B7
VSSA
C C4
PB6
C6
PB3
D D1
VLXSD
D3
PB12
D5
PB2
D7
PB0
E E4
PB7
E6
PB1
F F1
PB14
F3
PB13
F5
PB4
F7
PA2
G G2
PB15
G6
PA3
H H5
PB5
J J1
VSSSX
J3
VSSIO
J7
PA1
K4
K VSS
IFADC
K6
PA9
L L1
OSCIN
L5
PA10
L7
PA0
M4
M M2
VDDRF
VSS
FTRX
M6
PA11
N1
N OSCOU
N5 N7
DT57469
RF1 PA8
T
1. The above figure shows the package top view.
4.2 Pin description
Table 5. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below, the pin name and the pin function during
Pin name
and after reset are the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
RF RF I/O
RST Bidirectional reset pin with weak pull-up resistor
I/O structure
Options for TT or FT I/Os
_f(1). I/O, Fm+ capable
I/O, with analog switch function supplied by IO

_a(2).
BOOSTER(3)
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset
Alternate functions Functions selected through GPIOx_AFR registers
Pin functions
Additional functions Functions directly selected/enabled through peripheral registers
1. The related I/O structures in Table 6. Pin description are: FT_f
DS14210 - Rev 3 page 26/72

STM32WB09xE
2. The related I/O structures in Table 6. Pin description are: FT_a

3. IO BOOSTER block allows the good behavior of those switches to be guaranteed when the VBAT goes below 2.7 V. Refer
to the STM3WB09xE reference Manual (RM0491) for more details.
Table 6. Pin description
Pin number Pin name

Pin I/O
(function after Alternate functions Additional functions
VFQFPN32 WLCSP36 type structure
reset)
USART_CTS, LPUART_TX,
SPI3_SCK, TIM2_CH4,
ADC_VINP0,
1 C6 PB3 I/O FT_a TIM17_CH1,
PWR_WKUP3
RADIO_ANTENNA_ID[3],
I2S3_SCK
USART_RTS_DE, TIM2_CH3,
ADC_VINM0,
2 D5 PB2 I/O FT_a TIM16_BK,
PWR_WKUP2
RADIO_ANTENNA_ID[2]
USART_CK, TIM2_ETR,
ADC_VINP1,
3 E6 PB1 I/O FT_a TIM16_CH1N,
PWR_WKUP1
RADIO_ANTENNA_ID[1]
USART_RX,
LPUART_RTS_DE, ADC_VINM1,
4 D7 PB0 I/O FT_a
TIM16_CH1, PWR_WKUP0
RADIO_ANTENNA_ID[0]
DEBUG_SWCLK,
USART_RTS_DE, SPI3_SCK, ADC_VINP2,
5 G6 PA3 I/O FT_a
TIM2_CH2, TIM16_CH1N, PWR_WKUP15
I2S3_SCK
DEBUG_SWDIO, USART_CK,
ADC_VINM2,
6 F7 PA2 I/O FT_a SPI3_MCK, TIM2_CH1,
PWR_WKUP14
TIM16_CH1, I2S3_MCK
I2C1_SDA, IR_OUT,
7 J7 PA1 I/O FT_f PWR_WKUP13
USART_TX, TIM2_CH4
I2C1_SCL, USART_CTS,
8 L7 PA0 I/O FT_f PWR_WKUP12
IR_OUT, TIM2_CH3
USART_RX,
RADIO_RX_SEQUENCE, PWR_WKUP8,
9 N7 PA8 I/O FT
SPI3_MISO, TIM2_CH3, RTC_OUT
TIM16BK, I2S3_MISO
USART_TX, RTC_OUT,
10 K6 PA9 I/O FT SPI3_NSS, TIM2_CH4, PWR_WKUP9
TIM17_CH1, I2S3_WS
LPUART_CTS,
RADIO_TX_SEQUENCE, PWR_WKUP10,
11 L5 PA10 I/O FT
SPI3_MCK, TIM17_CH1N, RCC_LCO
I2S3_MCK
RCC_MCO,
RADIO_RX_SEQUENCE,
12 M6 PA11 I/O FT PWR_WKUP11
SPI3_MOSI, TIM17_BK,
I2S3_SD
1.7-3.6 battery voltage
13 A6 VDD2 S - -
input
RF input/output.
14 N5 RF1 I/O RF -
Impedance 50 Ω
15 M2 VDDRF S - -
input
16 N1 OSCOUT I/O FT_a - 32 MHz crystal
DS14210 - Rev 3 page 27/72

STM32WB09xE
Pin number Pin name

Pin I/O
(function after Alternate functions Additional functions
VFQFPN32 WLCSP36 type structure
reset)
17 L1 OSCIN I/O FT_a - 32 MHz crystal

18 G2 PB15 I/O FT_a USART_TX PWR_WKUP19
RADIO_TX_SEQUENCE,
PVD_IN,
19 F1 PB14 I/O FT_a I2C1_SDA, TIM2_ETR,
PWR_WKUP18
RCC_MCO, USART_RX
RCC_OSC32_IN,
20 F3 PB13 I/O FT_a TIM2_CH4
PWR_WKUP17
LPUART_CTS, RCC_LCO, RCC_OSC32_OUT,
21 D3 PB12 I/O FT_a
TIM2_CH3 PWR_WKUP16
USART_CTS, I2C1_SDA,
22 E4 PB7 I/O FT_f LPUART_RX, TIM2_CH2, PWR_WKUP7
RF_ACTIVITY
I2C1_SCL, LPUART_TX,
23 C4 PB6 I/O FT_f TIM2_CH1, TIM17_CH1, PWR_WKUP6
RADIO_ANTENNA_ID[6]
24 B1 VDDSD S - -
input
25 D1 VLXSD S - - SMPS input/output
26 A2 VSSSD S - - SMPS Ground
27 B3 VFBSD S - - SMPS output
28 A4 VDDA_VCAP S - - 1.2 Vdigital core
29 B5 RSTN I/O RST - Reset pin
LPUART_RX, TIM2_CH2,
PWR_WKUP5,
30 H5 PB5 I/O FT_a TIM17_BK,
ADC_VINP3
RADIO_ANTENNA_ID[5]
LPUART_TX, TIM2_CH1,
PWR_WKUP4,
31 F5 PB4 I/O FT_a TIM17_CH1N,
ADC_VINM3
RADIO_ANTENNA_ID[4]
32 - VDD1 S - -
input
Ground analog ADC
- B7 VSSA S - -
core
- J3 VSSIO S - - Ground I/O
- K4 VSSIFADC S - - Ground analog RF
- J1 VSSSX S - - Ground analog RF
- M4 VSSRFTRX S - - Ground analog RF
Exposed pad - GND S - - Ground
DS14210 - Rev 3 page 28/72

4.3 Alternate functions
DS14210 - Rev 3
Table 7. Alternate function port A
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port
I2C1/SYS_AF/USART IR/LPUART/USART IR/RTC USART/RF SPI3 TIM2 SYS_AF TIM16/TIM17 SYS_AF
PA0 I2C1_SCL USART_CTS IR_OUT - TIM2_CH3 - - -

PA1 I2C1_SDA IR_OUT USART_TX - TIM2_CH4 - - -
PA2 DEBUG_SWDIO USART_CK - SPI3_MCK/ I2S3_MCK TIM2_CH1 DEBUG_SWDIO TIM16_CH1 DEBUG_SWDIO
PA3 DEBUG_SWCLK USART_RTS_DE - SPI3_SCK/ I2S3_SCK TIM2_CH2 DEBUG_SWCLK TIM16_CH1N DEBUG_SWCLK
Port A PA8 USART_RX - RADIO_RX_SEQUENCE SPI3_MISO/ I2S3_MISO TIM2_CH3 - TIM16_BK -
PA9 USART_TX - RTC_OUT SPI3_NSS/ I2S3_WS TIM2_CH4 - TIM17_CH1 -
PA10 - LPUART_CTS RADIO_TX_SEQUENCE SPI3_MCK/ I2S3_MCK - - TIM17_CH1N -
PA11 RCC_MCO - RADIO_RX_SEQUENCE SPI3_MOSI/ I2S3_SD - - TIM17_BK -
Table 8. Alternate function port B
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port LPUART/TIM2 TIM16/
I2C1/ USART/LPUART SYS_AF/ LPUART TIM2/SYS_AF/LPUART TIM2 - RF/USART -
RIM17
PB0 USART_RX LPUART_RTS_DE TIM16_CH1 - - - RADIO_ANTENNA_ID[0] -
Pinout, pin description and

PB1 USART_CK - TIM16_CH1N TIM2_ETR - - RADIO_ANTENNA_ID[1] -
PB2 USART_RTS_DE - TIM16_BK TIM2_CH3 - - RADIO_ANTENNA_ID[2] -
PB3 USART_CTS LPUART_TX TIM17_CH1 TIM2_CH4 SPI3_SCK/ I2S3_SCK - RADIO_ANTENNA_ID[3] -
PB4 LPUART_TX - TIM17_CH1N - TIM2_CH1 - RADIO_ANTENNA_ID[4] -
PB5 LPUART_RX - TIM17_BK - TIM2_CH2 - RADIO_ANTENNA_ID[5] -
Port B
PB6 I2C1_SCL - TIM17_CH1 LPUART_TX TIM2_CH1 - RADIO_ANTENNA_ID[6] -
PB7 I2C1_SDA - USART_CTS LPUART_RX TIM2_CH2 - RADIO_RF_ACTIVITY -
STM32WB09xE
alternate functions
PB12 - RCC_LCO LPUART_CTS - TIM2_CH3 - - -
PB13 - - - - TIM2_CH4 - - -
PB14 I2C1_SMBA RADIO_TX_SEQUENCE TIM2_ETR RCC_MCO - - USART_RX -
page 29/72
PB15 - - - - - - USART_TX -
STM32WB09xE
Application circuits
5 Application circuits
The schematics below are purely indicative.
Figure 9. Application circuit: DC-DC converter, WLCSP36 package

VDD VDD
C1 C2 C3 C4
VDD
C7
C5 C6 M2
A6
A4
B1
B5
U1 V DDA _V CAP
V DDRF
V DD2
V DDSD
RSTN
L7
PA0
J7
PA1
F7 B3
PA2 VFBSD
G6 L1 L2
PA3 D1
N7 VLXSD
PA8
K6 C8
PA9 C9
L5
PA10
M6
PA11
D7 L3 A1
PB0
E6
PB1
STM32WB09xE
C10
D5
PB2 WLCSP36 L4
C6 N5
PB3 RF1
F5
PB4 C13 C11 C12
H5
PB5
C4 C14
PB6
E4
PB7
F1
PB14
F3
PB13
X1 D3
V SS_IFA DC
PB12 L1
V SS_FTRX
G2 OSCIN
PB15 N1 X2
V SSSD
V SSSX
V SSIO
OSCOUT
V SSA
XTAL_LS
C15 C16
XTAL_HS
K4
A2
B7
J3
M4
J1
DT57471
DS14210 - Rev 3 page 30/72

STM32WB09xE
Figure 10. Application circuit: DC-DC converter, VFQFPN32 package
X1
VDD C15 XTAL_LS C16
C5 C6 X2
24
23
22
21
20
19
18
17
U1
XTAL_HS VDD
PB6
PB7
PB12/RCC_OSC32_OUT
PB13/RCC_OSC32_IN
V D D SD
PB15
OSCIN
PB14
C3 C4
L2 L1
25 L3 A1
VLXSD 16
26 OSCOUT
VSS 15 C10
VDDRF L4
27
VFBSD 14
28 RF1
VCAP 13
29 VDD2
RSTN 12 C13 C11 C12
C8 C9 30 PA11
C7
31
PB5 STM32WB09xE PA10
11
C14
PB4 10
32 VFQFPN32 PA9
9
VDD
VDD VDD1
PA8
C1 C2
33
GND
PB3
PB2
PB1
PB0
PA 3
PA 2
PA 1
PA 0
C20
DT57472
1
8
2
6
7
Table 9. Application circuit external components
Component Description
C1 Decoupling capacitor
C7 Main LDO capacitor
C8 DC – DC converter output capacitor
C9 DC – DC converter output capacitor
C10 DC block capacitor
C12 RF Matching capacitor
C15 32 kHz crystal loading capacitor
C16 32 kHz crystal loading capacitor
L1 DC-DC converter output inductor
L2 DC-DC converter noise filter
L3 RF matching inductor
L4 RF matching inductor
X1 Low speed crystal
X2 High speed crystal
U1 STM3WB09xE
DS14210 - Rev 3 page 31/72

STM32WB09xE
Note: In order to make the board DC–DC OFF, the inductance L1 must be removed and the supply voltage must be
applied to the VFBSD pin.
DS14210 - Rev 3 page 32/72

STM32WB09xE
Electrical characteristics
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to ground (GND).
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the following standard
conditions:
• Ambient temperature is TA = 25 °C
• Supply voltage is VDD: 3.3 V
• System clock frequency is 32 MHz (clock source HSI)
• SMPS clock frequency is 4 MHz
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes and are not tested in production. Based on characterization, the minimum and maximum values
refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They are given only as design
guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean ± 2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are only given as design guidelines and are not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in the figure below.
Figure 11. Pin loading conditions
MCU pin
C = 50 pF
DT57473V1
DS14210 - Rev 3 page 33/72

STM32WB09xE
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in the figure below.
Figure 12. Pin input voltage
MCU pin
VIN
DT57474V1
DS14210 - Rev 3 page 34/72

STM32WB09xE
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 10. Voltage characteristics
Symbol Ratings Min. Max. Unit
VDD1, VDD2, VDDRF, VDDSD DC-DC converter supply voltage input and output -0.3 +3.9
VCAP, VDDA DC voltage on linear voltage regulator -0.3 +1.32
FXTALOUT, FXTALIN DC Voltage on HSE -0.3 +1.32
V
PA0 to PA3, PA8 to PA11, PB0 to PB7, PB14 to PB15 DC voltage on digital input/output pins
-0.3 +3.9
VLXSD, VFBSD DC voltage on analog pins
RCC_OSC32_OUT/PB12, RCC_OSC32_IN/PB13 DC voltage on XTA +3.6
-0.3
RF1 DC voltage on RF pin +1.4 -
Variations between different VDDX
|ΔVDD| - 50 mV
power pins of the same domain
Note: All the main power and ground pins must always be connected to the external power supply, in the permitted
range.
Table 11. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD power lines (source) 130
ΣIVGND Total current out of sum of all ground lines (sink) 130
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVGND(PIN) Maximum current out of each ground pin (sink) 100
Output current sunk by any I/O and control pin 20 mA

IIO(PIN)
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins 100
ΣIIO(PIN)
Total output current sourced by sum of all I/Os and control pins 100
Σ|IIN(PIN)| Total injected current (sum of all I/Os and control pins) -5/0
Table 12. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -40 to -125

°C
TJ Maximum junction temperature 125
DS14210 - Rev 3 page 35/72

STM32WB09xE
6.3 Operating conditions
6.3.1 General operating conditions
Table 13. General operating conditions
Symbol Parameter Conditions Min. Max. Unit
fHCLK Internal AHB clock frequency - 1 64
fPCLK0 Internal APB0 clock - 1 64

MHz
fPCLK1 Internal APB1 clock frequency - 1 64
fPCLK2 Internal APB2 clock frequency - 16 32
VDD Standard operating voltage - 1.7 3.6
VFBSMPS SMPS feedback voltage - 1.4 3.6

V
VDDRF Minimum RF voltage - 1.7 3.6
VIN I/O input voltage - -0.3 VDD+0.3
PD Power dissipation at TA=105 °C(1) VFQFPN32 package - 30 mW
TA Ambient temperature Maximum power dissipation -40 105 °C
TJ Junction temperature range - -40 105 -
1. TA cannot exceed the TJ max.
6.3.2 Summary of main performance
Table 14. Main performance SMPS ON
Typ. Typ.
Symbol Parameter Test conditions Unit
VDD = 1.8 V VDD = 3.3 V
Shutdown 12 25 nA
Deepstop, no timer, wakeup
0.618 0.649
GPIO, RAM0 retained
Deepstop, no timer, wakeup
0.767 0.792
GPIO, all RAM retained
Deepstop (32 kHz LSI), RAM0
1.103 1.197
retained
Deepstop (32 kHz LSI), all RAMs
1.245 1.344
retained
Deepstop (32 kHz LSE), RAM0
Core current 0.892 0.981
ICORE retained
consumption µA
Deepstop (32 kHz LSE), all RAM
0.978 1.074
retained
CPU in Run (64 MHz).
3850 2679
Dhrystone, clock source PLL64
2998 2216
CPU in RUN (16 MHz).
2161 1759
CPU in RUN (16 MHz).
1726 1523
Dhrystone, clock source HSE
DS14210 - Rev 3 page 36/72

STM32WB09xE
Typ. Typ.
VDD = 1.8 V VDD = 3.3 V
CPU in WFI (64 MHz), all

peripherals off, clock source 1860 1582
PLL64
PLL64
PLL64
Core current CPU in WFI (16 MHz), all

ICORE peripherals off, clock source 1447 1360 µA
consumption
Direct HSE
Radio RX at sensitivity level 6862 3693
Radio TX 0 dBm output power 8669 4916
Radio RX at sensitivity level with
CPU in WFI (32 MHz), clock 7878 4815
source Direct HSE
Radio TX 0 dBm output power
with CPU in WFI (32 MHz), clock 9683 6047
source Direct HSE
Computed value (CPU 64 MHz
IDYNAMIC Dynamic current Dhrystone - CPU 32 MHz 26.63 14.47 µA/MHz
Dhrystone) / 32
DS14210 - Rev 3 page 37/72

STM32WB09xE
Table 15. Main performance SMPS bypassed
Typ. Typ.
VDD = 1.8 V VDD = 3.3 V
Shutdown 12 25 nA
Deepstop, no timer,
wake up GPIO, RAM0 0.59 0.60
retained
Deepstop, no timer,
wake up GPIO, all 0.72 0.74
RAM retained
Deepstop (32 kHz
1.05 1.15
LSI), RAM0 retained
Deepstop (32 kHz
LSI), all RAMs 1.19 1.28
retained
Deepstop (32 kHz
0.85 0.94
LSE ), RAM0 retained
Deepstop (32 kHz
0.98 1.08
LSE), all RAM retained
Dhrystone, clock 4617 4635
source PLL64
Dhrystone, clock 3532 3627
source PLL64
CPU in RUN (16
MHz), all peripherals
Core current 1930 1630
ICORE off, clock source
consumption PLL64 µA
CPU in RUN (16
MHz), all peripherals 1497 1395
off, clock source HSE
CPU in WFI (64 MHz),
all peripherals off, 1904 1926
clock source PLL64
clock source PLL64
clock source PLL64
all peripherals off,
829 853
clock source Direct
HSE
Radio RX at sensitivity
- 8301
level
Radio TX 0 dBm
- 9681
output power
Radio RX at sensitivity
level with CPU in WFI
- 9171
(32MHz), clock source
Direct HSE
DS14210 - Rev 3 page 38/72

STM32WB09xE
Typ. Typ.
VDD = 1.8 V VDD = 3.3 V
Radio TX 0 dBm
Core current output power with
ICORE CPU in WFI (32MHz), - 10526 µA
consumption
clock source Direct
HSE
Computed value (CPU
64 MHz Dhrystone -
IDYNAMIC Dynamic current - 31.5 µA/MHz
CPU 32 MHz
Dhrystone) / 32
Table 16. Peripheral current consumption at VDD = 3.3 V, system clock (32 MHz), SMPS on
Parameter Typ. Unit
ADC 25
DMA 34
GPIOA 1
GPIOB 1
I2C1 40
IWDG 7
LPUART 54
PKA 358
TRNG 67
µA
RTC 10
SPI3/I2S3 38/43
Systick 8
TIM2 132
TIM16 80
TIM17 77
USART 87
SYSCFG 23
CRC 6
DS14210 - Rev 3 page 39/72

STM32WB09xE
6.3.3 RF general characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design.
Table 17. Bluetooth® Low Energy RF general characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
FRANGE Frequency range(1) - 2400 - 2483.5

MHz
RFCH RF channel center frequency(1) - 2402 - 2480
PLLRES RF channel spacing(1) - - 2 - MHz
ΔF Frequency deviation(1) - - 250 - kHz
Δf1 Frequency deviation average(1) - 450 - 550 kHz
During the packet and including both

CFdev Center frequency deviation(1) - - ±150 kHz
initial frequency offset and drift
Frequency deviation Δf2 (average) / Δf1
Δfa - 0.80 - - -
(average)(1)
Rgfsk On-air data rate(1) - 1 - 2 Mbit/s
STacc Symbol time accuracy(1) - - - ±50 ppm
MOD Modulation scheme - GFSK -

BT Bandwidth-bit period product - - 0.5 - -
Mindex Modulation index(1) - 0.45 0.5 0.55 -
At antenna connector, VSMPS = 1.9 V,

PMAX Maximum output - +8 - dBm
LDO code
PMIN Minimum output At antenna connector - -20 - dBm
@ 27 °C - ±1.5 -
PRFC RF power accuracy dB
All temperatures - ±2.5 -
1. Tested according to Bluetooth® SIG radio frequency physical layer (RF PHY) test suite (not tested in production).
DS14210 - Rev 3 page 40/72

STM32WB09xE
6.3.4 RF transmitter characteristics

Table 18. Bluetooth® Low Energy RF transmitter characteristics at 1 Mbit/s not coded
6 dB bandwidth for modulated

PBW1M Using resolution bandwidth of 100 kHz - 670 - kHz
carrier
Using resolution bandwidth of 100 kHz and
PRF1, 1 Ms/s In-band emission at ±2 MHz(1) - -41 - dBm
average detector
In-band emission at ±[3+n]MHz, Using resolution bandwidth of 100 kHz and
PRF2, 1 Ms/s - -45 - dBm
where n=0,1,2..(1) average detector
Harmonics included. Using resolution

PSPUR Spurious emission - - -41 dBm
bandwidth of 1 MHz and average detector
Integration interval #n – integration interval
Freqdrift Frequency drift(1) -50 - +50 kHz
#0, where n=2,3,4..k
Integration interval #1 – integration interval
IFreqdrift Initial carrier frequency drift(1) -23 - +23 kHz
#0
Intermediate carrier frequency Integration interval #n – integration interval
IntFreqdrift -20 - +20 kHz
drift(1) #(n-5), where n=6,7,8..k
Between any two 10-bit groups separated by kHz/50

Drift Rate max Maximum drift rate(1) -20 - +20
50 µs µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
(impedance at RF1 pin)
Table 19. Bluetooth® Low Energy RF transmitter characteristics at 2 Mbit/s not coded

PBW1M Using resolution bandwidth of 100 kHz - 1140 - kHz
carrier
PRF1, 2 Ms/s In-band emission at ±4 MHz(1) - -47 - dBm
average detector
PRF2, 2 Ms/s In-band emission at±5 MHz(1) - -47 - dBm
average detector
In-band emission at ±[6+n]MHz, Using resolution bandwidth of 100 kHz and
PRF3, 2 Ms/s - -48 - dBm
where n=0,1,2..(1) average detector

#0, where n=2,3,4..k
IFreqdrift Initial carrier frequency drift(1) Integration interval #1 – integration interval #0 -23 - +23 kHz

IntFreqdrift -20 - +20 kHz
drift(1) #(n-5), where n=6,7,8..k
Between any two 20-bit groups separated by

DriftRatemax Maximum drift rate(1) -20 - +20 kHz/50µs
50 µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
DS14210 - Rev 3 page 41/72

STM32WB09xE
Table 20. Bluetooth® Low Energy RF transmitter characteristics at 1 Mbit/s LE coded (S=8)

PBW Using resolution bandwidth of 100 kHz - 670 - kHz
carrier
PRF1, LE coded In-band emission at ±2 MHz(1) - -41 - dBm
average detector
In-band emission at ±[3+n] Using resolution bandwidth of 100 kHz and
PRF2, LE coded - -45 - dBm
MHz, where n=0,1,2..(1) average detector

#0, where n=1,2,3..k
Integration interval #3 – integration interval
IFreqdrift Initial carrier frequency drift(1) -19.2 - +19.2 kHz
#0
IntFreqdrift -19.2 - +19.2 kHz
drift(1) #(n-3), where n=7,8,9..k
Between any two 16-bit groups separated kHz/48

DriftRatemax Maximum drift rate(1) -19.2 - +19.2
by 48 µs µs
Optimum RF load
ZRF1 @ 2440 MHz - 40 - Ω
(Impedance at RF1 pin)
DS14210 - Rev 3 page 42/72

STM32WB09xE
6.3.5 RF receiver characteristics

Table 21. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s uncoded
RXSENS Sensitivity PER < 30.8% - -97 - dBm
PSAT Saturation PER < 30.8% - 8 - dBm
Optimum RF source
ZRF1 @ 2440 MHz - 40 - Ω
RF selectivity with Bluetooth® LE equal modulation on interfering signal

Co-channel interference
C/ICO-channel Wanted signal = -67 dBm, PER < 30.8% - 8 - dBc
fRX = finterference
Adjacent interference
C/I1 MHz Wanted signal = -67 dBm, PER < 30.8% - -1 - dBc
finterference = fRX ± 1 MHz
Adjacent Interference
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -67 dBm, PER < 30.8% - -47 - dBc
[n = 0,1,2…]
Image frequency interference
C/IImage Wanted signal = -67 dBm, PER < 30.8% - -25 - dBc
finterference = fimage
Adjacent channel-to-image frequency

C/IImage±1 MHz Wanted signal= -67 dBm, PER < 30.8% - -25 - dBc
finterference = fimage ± 1 MHz
Out of band blocking (interfering signal CW)

Interfering signal frequency 30 MHz – Wanted signal = -67 dBm, PER < 30.8%,
C/IBlock - 5 - dB
2000 MHz measurement resolution 10 MHz
C/IBlock - -5 - dB
C/IBlock - -5 - dB
C/IBlock - 10 - dB
12.75 GHz measurement resolution 25 MHz
Intermodulation characteristics (CW signal at f1, Bluetooth® LE interfering signal at f2)
Input power of IM interferer at 3 and 6

P_IM(3) Wanted signal = -64 dBm, PER < 30.8% - -27 - dBm
MHz distance from wanted signal
Input power of IM interferer at -3 and -6
P_IM(-3) Wanted signal = -64 dBm, PER < 30.8% - -40 - dBm
Input power of IM interferer at ±4 and ±8
P_IM(4) Wanted signal= -64 dBm, PER < 30.8% - -32 - dBm
P_IM(5) Wanted signal = -64 dBm, PER < 30.8% - -32 - dBm
DS14210 - Rev 3 page 43/72

STM32WB09xE
Table 22. Bluetooth® Low Energy RF receiver characteristics at 2 Msym/s uncoded
RXSENS Sensitivity PER < 30.8% - -94 - dBm
PSAT Saturation PER < 30.8% - 8 - dBm
Optimum RF source
ZRF1 @ 2440 MHz - 40 - Ω

C/ICO-channel Wanted signal= -67 dBm, PER < 30.8% - 8 - dBc
fRX = finterference
C/I6 MHz finterference = fRX ± (6+2n) MHz Wanted signal = -67 dBm, PER < 30.8% - -45 - dBc
[n = 0,1,2…]
C/IImage Wanted signal = -67 dBm, PER < 30.8% - -25 - dBc
finterference = fimage-2M
Adjacent channel-to-image frequency -

C/IImage±1 MHz Wanted signal= -67 dBm, PER < 30.8% -14 - dBc
finterference = fimage-2M ± 2 MHz -
Out of band blocking (interfering signal CW)

Interfering signal frequency 30 MHz – Wanted signal= -67 dBm, PER < 30.8%,
C/IBlock - 5 - dB
C/IBlock - -5 - dB
C/IBlock - -5 - dB
C/IBlock - 10 - dB
12.75 GHz measurement resolution 25 MHz
Intermodulation characteristics (CW signal at f1, Bluetooth® LE interfering signal at f2)
Input power of IM interferer at 6 and 12

Input power of IM interferer at -6 and -12
P_IM(-6) Wanted signal= -64 dBm, PER < 30.8% - -30 - dBm
Input power of IM interferer at ±10 and
±20 MHz distance from wanted signal
DS14210 - Rev 3 page 44/72

STM32WB09xE
Table 23. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2)
RXSENS Sensitivity PER < 30.8% -100 - dBm
PSAT Saturation PER < 30.8% 8 - dBm

-
Optimum RF source
ZRF1 @ 2440 MHz 40 - Ω

C/ICO-channel Wanted signal = -72 dBm, PER < 30.8% 2 - dBc
fRX = finterference
C/I1 MHz Wanted signal = -72 dBm, PER < 30.8% -5 - dBc
Adjacent interference -
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -72 dBm, PER < 30.8% -50 - dBc
[n = 0,1,2…]
C/IImage Wanted signal = -72 dBm, PER < 30.8% -30 - dBc

C/IImage±1 MHz Wanted signal = -72 dBm, PER < 30.8% -34 - dBc
Table 24. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8)
RXSENS Sensitivity PER < 30.8% -104 - dBm
PSAT Saturation PER < 30.8% 8 - dBm

-
Optimum RF source
ZRF1 @ 2440 MHz 40 - Ω

C/ICO-channel Wanted signal = -79 dBm, PER < 30.8% 1 - dBc
fRX = finterference
Adjacent interference -
C/I3 MHz finterference = fRX ± (3+n) MHz Wanted signal = -79 dBm, PER < 30.8% -53 - dBc
[n = 0,1,2…]
C/IImage Wanted signal = -79 dBm, PER < 30.8% -33 - dBc

C/IImage ± 1 MHz Wanted signal = -79 dBm, PER < 30.8% -32 - dBc
DS14210 - Rev 3 page 45/72

STM32WB09xE
6.3.6 Embedded reset and power control block characteristics
Table 25. Embedded reset and power control block characteristics
Reset temporization after

TRSTTEMPO VDD rising - - 500 μs
PDR is detected
VPDR Power-down reset threshold - - 1.58 -
VPVD0 PVD0 threshold PVD0 threshold at the falling edge of VDDIO - 2.05 -
V
PVD7 threshold (VBGP) at the falling edge of

VPVD7 PVD threshold for VIN_PVD - 1 -
VIN_PVD
6.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as: the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number
• When the peripherals are enabled fPCLK = fHCLK
Table 26. Current consumption
Typ.
Symbol Parameter Conditions Unit
25 °C 85 °C 105 °C
fHCLK = 64 MHz
2349 2428 2476
All peripherals disabled
fHCLK = 32 MHz
IDD(Run) Supply current in Run mode(1) 1964 2040 2086 µA
fHCLK = 16 MHz
1617 1686 1729
Clock OFF 742 5197 12499
Clock source LSI 1290 5791 13294
Clock source LSI
1358 5900 13298
RTC ON
IDD(Deepstop) Supply current in Deepstop(2) nA
Clock source LSI
1300 5864 13298
IWDG ON
Clock source LSI
1373 5946 13395
RTC, LPUART and IWDG ON(3)
DS14210 - Rev 3 page 46/72

STM32WB09xE
Typ.
Symbol Parameter Conditions Unit
25 °C 85 °C 105 °C
Clock source LSE 1023 5547 12929

Clock source LSE
1090 5682 13007
RTC ON
Clock source LSE
1043 5599 13003
IDD(Deepstop) Supply current in Deepstop(2) IWDG ON
nA
Clock source LSE.
1128 5682 13035
LPUART ON
Clock source LSE
1212 5816 13160
RTC, LPUART and IWDG ON
IDD(Shutdown) Supply current in Shutdown SMPS ON 20 279 871
IDD(RST) Current under reset condition - 956 1073 1160 µA
1. The CPU executes a "while(1)" loop

2. The current consumption in Deepstop is measured considering the entire SRAM retained.
3. LPUART not functional in deepstop mode with LSI (only LSE)
6.3.8 Wakeup time from low-power modes

The wakeup times reported are the latency between the event and the execution of the instruction. The device
goes to low-power mode after WFI (wait for interrupt) instructions.
Table 27. Low-power mode wakeup timing
Symbol Parameter Conditions Typ. Unit
TWUDEEPSTOP Wakeup time from Deepstop mode to Run mode Wakeup from GPIO VDD = 3.3 V flash memory 170 µs
6.3.9 High speed crystal requirements

The high speed external oscillator must be supplied with an external 32 MHz crystal that is specified for a 6 to 8
pF loading capacitor. The STM32WB09 includes internal programmable capacitances that can be used to tune
the crystal frequency in order to compensate the PCB parasitic one. These internal load capacitors are made by a
fixed one, in parallel with a 6-bit binary weighted capacitor bank. Thanks to low CL step size (LSB is typically 0.07
pF), very fine crystal tuning is possible. With a typical XTAL sensitivity of -14 ppm/pF, it is possible to trim a 32
MHz crystal, with a resolution of 1 ppm.
The requirements for the external 32 MHz crystal are reported in the table below.
Table 28. HSE crystal requirements
Symbol Parameter Conditions Min. Typ. Max. Unit
fNOM Oscillator frequency - - 32 - MHz
Includes initial accuracy, stability over temperature,

fTOL Frequency tolerance aging and frequency pulling due to incorrect load - - ±50 ppm
capacitance
ESR Equivalent series resistance - - - 100 Ω
PD Drive level - - - 100 µW
CL HSE crystal load capacitance 27 °C, GMCONF = 3 5 (1) 7(2) 9.2(3) pF
HSE crystal load capacitance LSB 27 °C, GMCONF = 3

CLstep - 0.07 - pF
value XOTUNE code between 32 and 33
1. XOTUNE programed at minimum code = 0
DS14210 - Rev 3 page 47/72

STM32WB09xE
2. XOTUNE programed at center code = 32

3. XOTUNE programed at maximum code = 63
6.3.10 Low speed crystal requirements

Low speed clock can be supplied with an external 32.768 kHz crystal oscillator. Requirements for the external
32.768 kHz crystal are reported in the table below.
Table 29. LSE crystal requirements
fNOM Nominal frequency - - 32.768 - kHz
ESR Equivalent series resistance - - - 90 kΩ

PD Drive level - - - 0.1 µW
6.3.11 High speed ring oscillator characteristics
Table 30. HSI oscillator characteristics
fNOM Nominal frequency - - 64 - MHz
6.3.12 Low speed ring oscillator characteristics
Table 31. LSI oscillator characteristics
VDD =3 .3 V
fNOM Nominal frequency Ambient temperature - 33 - kHz
Typical corner
ΔFRO_ΔT/FRO Frequency spread vs. temperature Standard deviation - 140 - ppm/ºC
6.3.13 PLL characteristics

Characteristics measured over recommended operating conditions unless otherwise specified.
Table 32. PLL characteristics
At ±1 MHz offset from carrier

- -110 - dBc/Hz
(measured at 2.4 GHz)
At 2.4 GHz ±3 MHz offset from carrier
- -114 - dBc/Hz
PNSYNTH RF carrier phase noise (measured at 2.4 GHz)
At 2.4 GHz±6 MHz offset from carrier
- -128 - dBc/Hz
(measured at 2.4 GHz)
At ±25 MHz offset from carrier - -135 - dBc/Hz
LOCKTIMETX PLL lock time to TX With calibration @2.5 ppm - 150 - µs
LOCKTIMERX PLL lock time to RX With calibration @2.5 ppm - 110 - µs
DS14210 - Rev 3 page 48/72

STM32WB09xE
LOCKTIMERXTX PLL lock time RX to TX Without calibration @2.5 ppm - 47 - µs
LOCKTIMETXRX PLL lock time TX to RX Without calibration @2.5 ppm - 32 - µs
6.3.14 Flash memory characteristics

The characteristics below are guaranteed by design.
Table 33. Flash memory characteristics
Symbol Parameter Test conditions Typ. Max. Unit
tprog 32-bit programming time - 20 40

µs
tprog_burst 4x32-bit burst programming time - 4x20 4x40
tERASE Page (2 kbyte) erase time - 20 40

ms
tME Mass erase time - 20 40
Write mode 3 -
IDD Average consumption from VDD Erase mode 3 - mA
Mass erase 5 -
Table 34. Flash memory endurance and data retention
Symbol Parameter Test conditions Min. Unit
NEND Endurance TA = -40 to +105 ºC 10 kcycles
tRET Data retention TA = 105 ºC 10 Years
6.3.15 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each
sample according to each pin combination. The sample size depends on the number of supply pins in the device
(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard.
Table 35. ESD absolute maximum ratings
Symbol Parameter Conditions Class Max.(1) Unit
Electrostatic discharge voltage (human body

VESD(HBM) Conforming to ANSI/ESDA/JEDEC JS-001 2 2000
model)
V
Electrostatic discharge voltage (charge Conforming to ANSI/ESDA/STM5.3.1
VESD(CBM) C2a 500
device model) JS-002
1. Guaranteed by design.
DS14210 - Rev 3 page 49/72

STM32WB09xE
6.3.16 I/O port characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests performed under the
conditions summarized in Table 13. All I/Os are designed as CMOS-compliant.
The characteristics below are guaranteed by characterization.
Table 36. I/O static characteristics
VIL I/O input low level voltage - - 0.3 x VDD

1.62 V < VDD < 3.6 V V
VIH I/O input high level voltage 0.7 x VDD - -
0 <= VIN <= Max(VDDx)(1) - - +/-100
Ilkg Input leakage current Max(VDDx)(1) <= VIN <= Max(VDDx)(1) +1 V - - 650 nA
Max(VDDx)(1) + 1 V < VIN <= 5.5 V - - 200
RPU Pull-up resistor VIN = GND 25 40 55

kΩ
RPD Pull-down resistor VIN = VDD 25 40 55
CIO I/O pin capacitance - - 5 - pF
1. Max(VDDx) is the maximum value among all the I/O supplies.
All I/Os are CMOS-compliant (no software configuration required).

GPIOs (general purpose input/outputs) can sink or source up to ±8 mA and sink or source up to ± 20 mA (with a
relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to respect the absolute
maximum rating specified.
• The sum of currents sourced by all I/Os on VDD, plus the maximum consumption of MCU sourced on VDD,
cannot exceed the absolute maximum rating ΣIVDD
• The sum of currents sunk by all I/Os on VSS, plus the maximum consumption of the MCU sunk on GND,
cannot exceed the absolute maximum rating ΣIVGND
The characteristics below are guaranteed by characterization.
Table 37. Output voltage characteristics
Symbol Parameter Conditions Min. Max. Unit
VOL Output low level voltage for I/O pin - 0.4

CMOS port(1) |IIO| = 8 mA VDD ≥ 2.7 V
VOH Output high level voltage for I/O pin VDD -0.4 -

|IIO| = 20 mA VDD ≥ 2.7 V V
VOH Output high level voltage for I/O pin VDD -1.3 -

|IIO| = 4 mA VDD ≥ 1.62 V
VOH Output high level voltage for I/O pin VDD-0.45 -
1. CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
6.3.17 RSTN pin characteristics

The RSTN pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 13.
DS14210 - Rev 3 page 50/72

STM32WB09xE
Table 38. RSTN pin characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit.
VIL(RSTN) RSTN input low level voltage - - - 0.3 x VDD

V
VIH(RSTN) RSTN input high level voltage - 0.7 x VDD - -
Vhys(RSTN) RSTN Schmitt trigger voltage hysteresis - - 200 - mV
RPU Weak pull-up equivalent resistor VIN=GND 25 40 55 kΩ
Figure 13. Recommended RSTN pin protection
DT57475V1
1. The external reset circuit protects the device against parasitic resets.
2. The user must ensure that the level on the RSTN pin can go below the VIL(RSTN) max. level specified in the
table, otherwise the reset is not taken into account by the device.
3. The external capacitor on RSTN must be placed as close as possible to the device.
6.3.18 ADC characteristics
Table 39. ADC characteristics (HSI must be set to PLL mode)
Symbol Parameter Test conditions Min. Typ. Max. Units
Number of channels for

Ch_diff_num VFQFPN32, WLCSP36 - - 4 -
differential mode
Number of channels for
Ch_se_num VFQFPN32, WLCSP36 - - 8 -
single ended mode
ADC biasing consumption at
IBATADCBIAS Biasing blocks turned on - 145 - µA
battery
ADC active consumption at
IBATADCACTIVE ADC activated in differential mode - 185 - µA
battery
VDDA Analog supply voltage - 1.2 - 1.32 V
RAIN Input impedance In DC - 250 - kΩ
Rin Internal access resistance VBOOST is enabled for VBAT < 2.7 V - - 550 Ω
Cin Input sampling capacitor - - 4 - pF
Ts Sampling period Default configuration - 1 - µs
Tsw Sampling time Default configuration - 125 - ns
DR Output data rate - - 200 - k samples/s
DS14210 - Rev 3 page 51/72

STM32WB09xE
Symbol Parameter Test conditions Min. Typ. Max. Units
FRMToutput Output data format - - 16 - bits
TL Latency time 200 kSps - 5 - µs

TSTARTUP Start-up time From ADC enable to conversion start - - 1 µs
DNL Differential non-linearity - - ±0.7 - LSB

INL Integral non-linearity - - ±1 - LSB
Differential input
SNR Diff Signal to noise ratio - 72 - dB
@1 kHz, -1 dBFs, FS = 1 MHz with DF
Signal to THD ratio (10 Differential input

STHD Diff - 75 - dB
harmonics) @1 kHz, -1 dBFs, FS = 1 MHz with DF
Differential input
ENOB Diff Effective number of bits - 11.5 - bits
Single ended
SNR SE Signal-to-noise ratio - 70 - dB
Signal-to THD ratio (10 Single ended

STHD SE - 70 - dB
harmonics) @1 kHz, -1 dBFs, FS = 1 MHz with DF
Single ended
ENOB SE Effective number of bits - 11 - bits
- ADC_ERR_1V7 - 13 -
- ADC_ERR_2V4 Absolute error when used for battery - 0 -
mV
- ADC_ERR_3V0 measurements at 1.7 V, 2.4 V, 3.0 V, 3.6 V - -9 -
- ADC_ERR_3V6 - -22 -
6.3.19 Temperature sensor characteristics
Table 40. Temperature sensor characteristics
Symbol Parameter Min. Typ. Max. Unit
TrERR Error in temperature - ±4 - °C
TSLOPE Average temperature coefficient - 8 - LSB/°C
TICC Current consumption - 415 - µA
TTS-out Output Code at 30°C (+-5°C) - - 2533 bit
6.3.20 Timer characteristics

Table 41. TIM1 characteristics
tres(TIM) Timer resolution time fTIMxCLK = 64 MHz - 15.625 - ns
ResTIM Timer resolution - - 16 - bit
tCOUNTER 16-bit counter clock period fTIMxCLK = 64 MHz 0.015625 - 1024 μs
tMAX_COUNT Maximum possible count time fTIMxCLK= 64 - - 67.10 s
DS14210 - Rev 3 page 52/72

STM32WB09xE
Table 42. IWDG min./max. timeout period at 32 kHz (LSE)
Prescaler divider PR[2:0] bits Min. timeout RL[11:0] = 0x000 Max. timeout RL[11:0] = 0xFFF Unit
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
6.3.21 I2C interface characteristics

The I2C interface meets the timing requirements of the I2C-Bus specifications and user manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 Kbit/s
• Fast-mode (Fm): bit rate up to 400 Kbit/s
• Fast-mode plus (Fm+): bit rate up to 1 Mbit/s
SDA and SCL I/O requirements are met with the following restrictions: SDA and SCL I/O pins are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still
present. The 20 mA output drive requirement in fast-mode plus is supported partially.
This limits the maximum load Cload supported in fast-mode plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min.) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up.
All I2C SDA and SCL I/Os embed an analog filter.
Table 43. I2C analog filter characteristics
Symbol Parameter Min. Max. Unit
tAF Maximum pulse width of spikes that are suppressed by the analog filter 50 110 ns
6.3.22 SPI characteristics

The parameters for SPI are derived from tests performed according to fPCLKx frequency and supply voltage
conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Table 44. SPI characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
Master mode 32
fSCK SPI clock frequency - - MHz
Slave mode 32(1)
tsu(NSS) NSS setup time - 4 / fPCLK - - -
th(NSS) NSS hold time - 2 / fPCLK - - -
DS14210 - Rev 3 page 53/72

STM32WB09xE
Symbol Parameter Conditions Min. Typ. Max. Units
tw(SCKH) 1 / fPCLK - 1.5 1 / fPCLK 1 / fPCLK+1

SCK high and low time Master mode
tw(SCKL) 1 / fPCLK- 1.5 1 / fPCLK 1 / fPCLK+1
tsu(MI) Data input set-up time Master mode 2 - -
tsu(SI) Data input set-up time Slave mode 1 - -
th(MI) Data input hold time Master mode 2 - -
th(SI) Data input hold time Slave mode 0 - -

ns
ta(SO) Data output access time Slave mode 6 - 30
tdis(SO) Data output disable time Slave mode 6 - 32
tv(MO) Master mode - 5 9

Data output valid time
tv(SO) Slave mode - 12 35
th(MO) Master mode 1 -

Data output hold time -
th(SO) Slave mode 6 -
1. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while duty(SCK) = 50 %.
Figure 14. SPI timing diagram - slave mode and CPHA = 0
DT57476V1
DS14210 - Rev 3 page 54/72

STM32WB09xE
Figure 15. SPI timing diagram - slave mode and CPHA = 1
DT57477V1
Figure 16. SPI timing diagram - master mode
DT57478V1
DS14210 - Rev 3 page 55/72

STM32WB09xE
Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK2
packages, depending on their level of environmental compliance. ECOPACK2 specifications, grade definitions
and product status are available at: www.st.com. ECOPACK2 is an ST trademark.
7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers and microprocessors”
(TN1433 ) available on http://www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation
of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example is provided in the corresponding package information subsection.
DS14210 - Rev 3 page 56/72

STM32WB09xE
Package information
7.2 VFQFPN32 package information (42)

This VFQFPN is a 32 lead, 5 x 5 mm, 0.50 mm pitch, very fine pitch quad flat no lead package.
Figure 17. VFQFPN32 - Outline
ddd C
SEATNG PLANE
A1
A3
SIDE VIEW
17 e
8
b
E2 E
24 L
42_VFQFPN32_CALAMBA_ME_V1
PIN #1 ID 32 25
CHAMFER 0.35
b L
D2
BOTTOM VIEW
1. Drawing is not to scale.

2. Package outline exclusive of any mold flashes dimensions and metal burrs.
3. Details of terminal 1 are optional but must be located on the top surface of the package by using either a mold
or marked features.
DS14210 - Rev 3 page 57/72

STM32WB09xE
Package information
Table 45. VFQFPN32 - Mechanical data
Millimetres Inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) 0.80 0.90 1.00 0.0315 0.0354 0.0394
A1 0 - 0.05 0 - 0.0020
A3 - 0.20 - - 0.008 -
b 0.18 0.25 0.30 0.0070 0.0098 0.0118
D 4.90 5.00 5.10 0.1929 0.19 0.2008
E 4.90 5.00 5.10 0.1929 0.19 0.2008
D2 3.60 3.70 3.80 0.1417 0.1457 0.1496
E2 3.60 3.70 3.80 0.1417 0.1457 0.1496
e - 0.50 - - 0.0197 -
L 0.30 0.40 0.50 0.0118 0.0157 0.0197
ddd - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 3 decimal digits.

2. VFQFPN stands for thermally Enhanced very thin fine pitch quad flat package No lead . Very thin profile 0.80 < A ≤ 1.00
mm.
Figure 18. VFQFPN32 - Footprint example
3.50
0.80
0.25 0.25
0.50 3.50 5.70
42_VFQFPN32_CALAMBA_FP_V1
4.10
0.30
DS14210 - Rev 3 page 58/72

STM32WB09xE
Package information
7.3 WLCSP36 package information (B0LY)

This WLCSP is a 36-ball, 2.83 x 2.99 mm, 0.40 mm pitch, wafer level chip scale package.
Figure 19. WLCSP36 - Outline
bbb Z
(0.335)
e1 A1
A2 BALL LOCATION
F e C
G 6 4 2 (0.269)
7 5 3 1
A
B
C
D DETAIL A
e E
F
(0.630) G e2
H
J
K
L
M
N e
(0.289) K
e A
(0.421)
H
BOTTOM VIEW SIDE VIEW
A3 A2
b
FRONT VIEW
B
BUMP
A1
eee
1 2 b (36x) Z
ccc Z X Y
B0LY_WLCSP36_ME_V2
ddd Z
SEATING PLANE
(4x) aaa 4
3
D A DETAIL A
ROTATED 90°
TOP VIEW
1. Drawing is not to scale.

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the
pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
DS14210 - Rev 3 page 59/72

STM32WB09xE
Package information
Table 46. WLCSP36 - Mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) - - 0.43 - - 0.0168
A1 - 0.15 - - 0.0059 -
A2 - 0.25 - - 0.0098 -
A3(3) - 0.025 - - 0.0010 -
b(4) 0.19 0.22 0.24 0.0076 0.0086 0.0096
D 2.81 2.83 2.85 0.1108 0.1116 0.1124

E 2.97 2.99 3.01 0.1168 0.1176 0.1184
e - 0.40 - - 0.0157 -
e1 - 2.08 - - 0.0818 -
e2 - 2.43 - - 0.0957 -
F(5) - 0.419 - - 0.0164 -
G(5) - 0.269 - - 0.0106 -
H(5) - 0.333 - - 0.0131 -
K(5) - 0.289 - - 0.0113 -
N 36
aaa - - 0.10 - - 0.004
bbb - - 0.10 - - 0.004
ccc(6) - - 0.10 - - 0.004

(7) - - 0.05 - - 0.002
eee - - 0.05 - - 0.002
1. Values in inches are converted from mm and rounded to 3 decimal digits.

2. The maximum total package height is calculated by the RSS method (root sum square) using nominal and tolerances values
of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of the pattern of
balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc perpendicular to datum Z and
located on true position with respect to datums X and Y as defined by e. The axis perpendicular to datum Z of each ball
must lie within this tolerance zone.
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball
there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true position as defined by e. The axis
perpendicular to datum Z of each ball must lie within this tolerance zone. Each tolerance zone ddd in the array is contained
entirely in the respective zone ccc above. The axis of each ball must lie simultaneously in both tolerance zones.
DS14210 - Rev 3 page 60/72

STM32WB09xE
Package information
Figure 20. WLCSP36 - Footprint example
Dpad
Dsm
1. Dimensions are expressed in millimeters.
Table 47. WLCSP36 - Example of PCB design rules
Dimension Values
Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
DS14210 - Rev 3 page 61/72

STM32WB09xE
Package information
7.3.1 Device marking example for WLCSP36

The following figure gives an example of topside marking versus pin 1 position identifier location. The printed
markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend
on supply chain operations, are not indicated below.
Figure 21. WLCSP36 marking example (package top view)
Dot
Product identification(1)
Revision code
Y WW
DT58390
Date code
1. Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting from
such use. In no event will ST be liable for the customer using any of these engineering samples in production.
ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a
qualification activity.
DS14210 - Rev 3 page 62/72

STM32WB09xE
Package information
7.4 Thermal characteristics

The maximum chip junction temperature (TJmax.) must never exceed the values in general operating conditions.
The maximum chip-junction temperature, TJ max., in degrees Celsius, can be calculated using the equation:
T Jmax . = TAmax. + PDmax × θJA (1)
where:
• TA max. is the maximum ambient temperature in °C
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W
• PD max. is the sum of PINT max. and PI/O max. (PD max. = PINT max. + PI/O max.)
• PINT max. is the product of IDD and VDD, expressed in Watt. This is the maximum chip internal power
PI/O max represents the maximum power dissipation on output pins:
• PI/O max. = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the applications.
Note: When the SMPS is used, a portion of the power consumption is dissipated into the external inductor, therefore
reducing the chip power dissipation. This portion depends mainly on the inductor ESR characteristics.
Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the chip power
consumption.
Note: RF characteristics (such as: sensitivity, Tx power, consumption) are provided up to 85 °C.
Table 48. Package thermal characteristics
Symbol Parameter Value Unit
Thermal resistance junction-ambient

ΘJA 26.9 ºC/W
VFQFPN32 - 5 mm x 5 mm
DS14210 - Rev 3 page 63/72

STM32WB09xE
Ordering information
8 Ordering information
Table 49. Ordering information scheme
Example: STM32 WB 09 K E V 6 TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
WB = wireless Bluetooth®
Device subfamily
09 = full set of features
Pin count
K = 32 pins
T = 36 pins
Flash memory size
E = 512 Kbytes
Package(1)
F = WLCSP
V = VFQFPN
Temperature range
6 = -40 °C up to +85 °C
7 = -40 °C up to +105 °C
Packing
TR = tape and reel
1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants).
Note: For a list of available options (memory, package, and so on) or for further information on any aspect of this
device, contact your nearest ST sales office.
DS14210 - Rev 3 page 64/72

STM32WB09xE
Important security notice
9 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST
product(s) identified in this documentation may be certified by various security certification bodies and/or may
implement our own security measures as set forth herein. However, no level of security certification and/or built-in
security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for
meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like),
including but not limited to any enhanced security features added by ST, are provided on an "AS IS"
BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS14210 - Rev 3 page 65/72

STM32WB09xE
Revision history
Table 50. Document revision history
Date Version Changes
21-Sep-2023 1 Initial release.

Removed Section 5 Memory mapping.
Added Table 1. STM32WB09xE device features and peripheral counts
Updated:
• Section Features (ultra-low power radio performance figures)
• Section 3.11: Clock management
• Figure 6. Clock tree
• Section 3.25: Serial wire debug port
06-Feb-2024 2
• Section 3.26: TX and RX event alert
• Section 3.27: Direction finding
• Table 6. Pin description
• Table 7. Alternate function port A
• Table 8. Alternate function port B
• Table 10. Voltage characteristics
• Table 14. Main performance SMPS ON
• Table 15. Main performance SMPS bypassed
• Removed unresolved product link from Product summary .
16-Feb-2024 3
• Replaced generic product path used in document.
DS14210 - Rev 3 page 66/72

STM32WB09xE
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Arm® Cortex®–M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Memory protection unit (MPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.3 Embedded ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.4 Embedded OTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7.1 RF front-end block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7.2 IPDs for STM32WB09xE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8.1 SMPS step-down regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8.3 Linear voltage regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8.4 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Reset management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.10 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.10.1 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10.2 Deepstop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10.3 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12 General purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.15 Analog digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.16 True random number generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17 Timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.17.1 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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3.17.2 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . 21
3.21 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . 21
3.22 Embedded UART bootloader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.23 Inter-IC sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.25 Serial wire debug port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.26 TX and RX event alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.27 Direction finding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4 Pinout, pin description and alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.2 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.3 RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.4 RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5 RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.9 High speed crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.10 Low speed crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.11 High speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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6.3.12 Low speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.3.13 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.14 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.15 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.17 RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.3.18 ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.19 Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.20 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.21 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.22 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.2 VFQFPN32 package information (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 WLCSP36 package information (B0LY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.3.1 Device marking example for WLCSP36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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List of tables
List of tables
Table 1. STM32WB09xE device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. SRAM overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. IPDs for STM32WB09xE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Relationship between the low-power modes and functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8. Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Application circuit external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Main performance SMPS ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Main performance SMPS bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Peripheral current consumption at VDD = 3.3 V, system clock (32 MHz), SMPS on . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Bluetooth® Low Energy RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Bluetooth® Low Energy RF transmitter characteristics at 1 Mbit/s not coded . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. Bluetooth® Low Energy RF transmitter characteristics at 2 Mbit/s not coded . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Bluetooth® Low Energy RF transmitter characteristics at 1 Mbit/s LE coded (S=8) . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s uncoded . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. Bluetooth® Low Energy RF receiver characteristics at 2 Msym/s uncoded . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2) . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Bluetooth® Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8) . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. Low-power mode wakeup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. LSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 34. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 36. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 37. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 38. RSTN pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 39. ADC characteristics (HSI must be set to PLL mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 40. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 41. TIM1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 42. IWDG min./max. timeout period at 32 kHz (LSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 43. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 44. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 45. VFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 46. WLCSP36 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 47. WLCSP36 - Example of PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 48. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 49. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DS14210 - Rev 3 page 70/72

STM32WB09xE
List of figures
List of figures
Figure 1. STM3WB09xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. STM3WB09xE RF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Power supply domain overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. VFQFPN32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. WLCSP36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Application circuit: DC-DC converter, WLCSP36 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Application circuit: DC-DC converter, VFQFPN32 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Recommended RSTN pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 14. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. VFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18. VFQFPN32 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 19. WLCSP36 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 20. WLCSP36 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21. WLCSP36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DS14210 - Rev 3 page 71/72

STM32WB09xE
IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
DS14210 - Rev 3 page 72/72

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STM32WB09xE

Ultra-low power wireless 32-bit MCU Arm®-based Cortex®-M0+ with Bluetooth®

DS14210 - Rev 3 - February 2024 www.st.com

• Ultra-low power radio performance

DS14210 - Rev 3 page 2/72

DS14210 - Rev 3 page 3/72

DS14210 - Rev 3 page 4/72

Table 1. STM32WB09xE device features and peripheral counts

Feature STM32WB09KE STM32WB09TE

Flash memory density 512 Kbytes

DS14210 - Rev 3 page 5/72

Feature STM32WB09KE STM32WB09TE

SPI 1 with I2S feature

Figure 1. STM3WB09xE block diagram

512 KBytes flash

DS14210 - Rev 3 page 6/72

3.1 Arm® Cortex®–M0+ core with MPU

3.2 System architecture

DS14210 - Rev 3 page 7/72

Figure 2. Bus matrix

3.4.1 Embedded flash memory

DS14210 - Rev 3 page 8/72

• Flash memory erase operations: page erase or mass erase

3.4.2 Embedded SRAM

Table 2. SRAM overview

SRAM bank Size Address Retained in Deepstop

SRAM0 16 Kbytes 0x2000 0000 Always

3.4.3 Embedded ROM

3.4.4 Embedded OTP

3.5 Security and safety

3.6 Boot modes

DS14210 - Rev 3 page 9/72

3.7.1 RF front-end block diagram

Figure 3. STM3WB09xE RF block diagram

DS14210 - Rev 3 page 10/72

3.7.2 IPDs for STM32WB09xE

Table 3. IPDs for STM32WB09xE

IPD MCU Package STM32WB09xxx part number

3.8 Power supply management

3.8.1 SMPS step-down regulator

Figure 4. Power supply configuration

DS14210 - Rev 3 page 11/72

3.8.2 Power supply schemes

Figure 5. Power supply domain overview

VGATEN CMDNO CMDNI VGATEP

VDD12O VDD12I VRF

3.8.3 Linear voltage regulators

DS14210 - Rev 3 page 12/72

3.8.4 Power supply supervisor

DS14210 - Rev 3 page 13/72

3.9 Reset management

3.10 Operating modes

Table 4. Relationship between the low-power modes and functional blocks

Mode Shutdown Deepstop Idle Run

CPU OFF OFF OFF ON

DS14210 - Rev 3 page 14/72

Mode Shutdown Deepstop Idle Run

Peripherals OFF OFF ON/OFF ON/OFF

3.10.1 Run mode