24 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO.

1, WINTER 2023

Efficient PV-Based Microinverter With Enhanced

ROI for Lower Economic Zone Habitants
Efficacité de micro-onduleur basé sur PV avec un
meilleur retour sur investissement pour les
habitants de zone économique inférieure
Anuradha Tomar , Senior Member, IEEE
Abstract— In this article, the conceptualization, design, development, and real-field validation of a photo-
voltaic (PV)-based single-phase microinverter (SPµI) to address three major challenges of rural standalone
PV-based electrical systems: 1) to perform efficiently over a wide range of input voltage variations/irradiance;
2) maintains system efficiency within a satisfactory limit even under lightly loaded conditions; and 3) robust and
stable operation under harsh/outdoor operating environments has been done. The developed novel dual-stage
SPµI adapts the benefits of the interleaved dc–dc boost converter for 180◦ phase-shifted harmonic cancellation
and integration of voltage doubler circuit benefits in lessened transformer’s turn ratio with decreased flux
leakage, thus resulting in improved energy conversion efficiency at a reduced magnetic size and Si-GaN.
Furthermore, adapted high- and low-frequency switching at the first and second legs of the full-bridge converter,
respectively, ensures minimized switching losses even at lightly loaded conditions. Based on a per watt comparison
to a 500-W inverter, the proposed SPµI achieves 6.16% and 8.5% higher efficiency at 100% and 10% loading,
respectively, at a reduced cost of 9.33% and an increased return on investment (ROI) of 12.23%.
Résumé— Dans cet article, la conceptualisation, la conception, le développement et la validation sur le terrain
réel d’un micro-onduleur monophasé (SPµI) à base de photovoltaïque(PV) pour relever trois défis majeurs
des systèmes électriques autonomes ruraux à base de PV : 1) fonctionner efficacement sur une large gamme
de variations de tension d’entrée/irradiance ; 2) maintenir l’efficacité du système dans une limite satisfaisante
même dans des conditions de charge légère ; et 3) un fonctionnement robuste et stable dans des environnements
de fonctionnement difficiles/extérieurs a été effectué. Le nouveau SPµI à deux étages développés adapte les
avantages du convertisseur élévateur cc-cc entrelacé pour l’annulation des harmoniques déphasées de 180◦
et l’intégration des avantages du circuit doubleur de tension dans un rapport de rotation du transformateur
réduit avec une fuite de flux diminuée, ce qui entraîne une efficacité de conversion d’énergie améliorée avec
une taille magnétique réduite et du Si-GaN. En outre, une commutation adaptée à haute et basse fréquence sur
les première et deuxième broches du convertisseur en pont complet, respectivement, permet de minimiser les
pertes de commutation même dans des conditions de faible charge. Sur la base d’une comparaison par watt
avec un onduleur de 500 W, le SPµI proposé atteint une efficacité supérieure de 6,16 % et 8,5 % à une charge
de 100 % et 10 %, respectivement, pour un coût réduit de 9,33 % et un retour sur investissement (ROI) accru
de 12,23 %.
Index Terms— DC–AC inverter, interleaved dc–dc converter, microinverter (µIs), photovoltaic (PV) standalone
system, rural electrification.

I. I NTRODUCTION verters (μIs) have become more popular due to their benefits
such as modular architecture, improved reliability, ability
T HE photovoltaic (PV) technology is coming up as a
favorable electrification solution for rural/remote areas
due to technoeconomic benefits [1], [2]. However, return on
to ensure MPPT operation even under mismatching operat-
ing scenarios, plug-and-play approach for capacity expansion
investment (ROI) is still a major concern [3]. ROI can be along with the ease of use, and maintenance [5]. The single-
improved by ensuring: 1) maximum power point tracking phase microinverter (SPμI) with high-frequency (HF) ac-link
(MPPT) operation of PV modules; 2) increasing the utilization configurations could be divided into two categories: 1) phase-
of available PV power [4]; 3) optimal sizing and appropriate modulated dc/dc converter architecture [5] and 2) the series
selection of system components; and 4) matching inverter resonant dc/ac dual-active-bridge converter [6].
characteristics with PV panels. In the past few years, microin- SPμIs suffer from the problem of pulsations at the dc bus
and thus require a large capacitor across it [7]. A pulsewidth
Manuscript received 25 May 2022; revised 30 August 2022 and 7 October modulation (PWM)-based SPμI configuration aiming to avoid
2022; accepted 11 November 2022. Date of publication 27 February 2023;
date of current version 3 March 2023. the need for bulky, large electrolytic capacitors at the dc
The author is with the Department of Instrumentation and Control Engi- bus has been presented in [8]. Bulky capacitor size may be
neering, Netaji Subhas University of Technology, Delhi 110078, India (e-mail: considerably reduced by using integrated chips like MIN1072
anuradha.tomar@nsut.ac.in).
Associate Editor managing this article’s review: John Lam. [9]. A two-stage interleaved flyback μI comprising a two-
Digital Object Identifier 10.1109/ICJECE.2022.3223294 phase interleaved flyback dc–dc converter and an H5 inverter
2694-1783 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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TOMAR: EFFICIENT PV-BASED MICROINVERTER WITH ENHANCED ROI FOR LOWER ECONOMIC ZONE HABITANTS 25

as a dc–ac conversion stage is introduced in [10]. Although it TABLE I

provides stable power conversion, the configuration involves S YSTEM S PECIFICATION FOR THE P ROPOSED PV-BASED SPμI
an increased number of switches. A transformer-less single-
stage μI configuration with high voltage gain is presented
in [11]. It aims to overcome the limitations of interfacing the
ac systems with the dc sources and freeing output from 100-Hz
ripples. Furthermore, a hybrid configuration having the advan-
tages of low cost, simple circuitry, and ease of integration
is presented in [12]. It is observed from the literature that a
variety of efficient μIs have been investigated, developed, and
tested but mostly confined to grid-connected applications.
An interleaved flyback converter topology-based PV μI
aimed at remote regions is proposed in [13]. It comprises a at the first and the second leg of the full-bridge converter,
flyback isolated transformer and utilizes a full-bridge inverter respectively, ensures lower switching losses even under lightly
configuration to achieve the desired frequency and ac output loaded conditions. The novelty of the presented work can
voltage. A single-stage, isolated, PV μI based on the dual- be considered as introducing optimized, low-power capacity
active-bridge principle with two full-bridge cells and floating SPμI suitable for wide input voltage variations/irradiations and
dc bus capacitors is presented in [14]. A dual-active-bridge works efficiently under various loading conditions while being
converter-based μI topology, which enables active power sustainable in harsh operating environments. The proposed
decoupling by injecting low-frequency power components SPμI is developed considering high ROI and is dedicated to
without any additional switch, is illustrated in [15]. The pre- the lower economic zone people living in remote/rural regions
sented topology needs further experimental investigation and that are not connected to the public utility grid. The main
analysis. A μI comprises two electrically coupled series boost contribution of the work is given as follows.
converters, having a forward resonant inverter, and supplied 1) The proposed work provides “best fit to application”
through two PV sources as proposed in [16]. A complete as it presents a dedicated SPμI for rural applications
solution in form of a PV kit is presented in [17]. The kit compared to general SPμIs that are presently being
consists of PV panels, battery energy storage (BES), and commonly used for urban as well as rural applications.
dc–dc–ac μI along with all related control functionalities. 2) It provides a step-by-step design example with its practi-
Though the kit introduced in [17] provides a complete solution cal implementation and validation, which may be easily
for rural areas, however, experimental validation is required. further developed as an industrial product.
Most of the μIs available in the market are generic. 3) It verifies the work through real-time outdoor field
PV-based rural power systems have application-specific issues hardware application for a snag-free model.
like: 1) should remain stable and perform satisfactorily over
a wide input voltage range; 2) maintain reasonable system II. S YSTEM D ESCRIPTION FOR THE P ROPOSED SPμI
efficiency over a wide range of system loading; and 3) able A schematic of the considered system for the proposed
to work efficiently under harsh operating conditions and rela- PV-based SPμI for rural applications is given in Fig. 1.
tively high ambient temperatures. Apart from these challenges, The overview of the system specifications has been tabulated
SPμIs should be compact, low cost with ease of handling, and in Table I. The SPμI consists of three intermediate stages:
scalable. Therefore, the need of developing high-tech, lost- 1) interleaved dc–dc boost converter along with doubler cir-
cost, efficient, compact μI dedicated to rural applications has cuit; 2) HF transformer with comparatively lower turns ratio;
been realized so that the overall ROI of the PV-based rural and 3) power converter using Si-GaN power devices with high
electric power systems can be improved. Dedicated μI for rural and low switching frequency for reduced losses and heatsink
applications will not only improve the system’s performance volume.
but also will enhance the system’s overall efficiency. Although As a prestage to dc/ac conversion, the two-phase interleaved
a lot of efforts have been done to improve the performance topology with HF switching is adapted, which enables 180◦
of the PV-based μIs, however, limited work has been reported phase cancellation and thus results in reduced harmonics.
related to dedicated μI for rural standalone applications. Voltage doubler circuit with rectifying actions of the diode
This work presents the conceptualization, design, and and capacitor bridge boosts the dc bus voltage in the range
technology development of an energy-efficient, low-cost, dual- of 190–356 V. Furthermore, to minimize the switching ripples
stage, isolated, PV-based SPμI specifically suitable for low- and harmonics, the concept of dual switching is adapted.
power applications and dedicated to the lower economic zone It means switching one leg of the power bridge at HF
people living in remote/rural areas. The proposed dual-stage (15–20 kHz) with blocking diodes and the second leg of
SPμI is an extension of work carried out in [18] and adapts the power bridge at the nominal operating frequency of the
the benefits of the interleaved dc–dc boost converter for 180◦ system (50 Hz).
phase-shifted harmonic cancellation and integration of voltage The control architecture of SPμI enables functionalities like:
doubler circuit benefits in lessened transformer’s turn ratio 1) MPPT operation of PV modules; 2) maintaining desired sta-
with decreased flux leakage, thus resulting in improved energy ble voltage at the prestage of dc/ac conversion; and 3) ensuring
conversion efficiency at a reduced magnetics size and Si-GaN. the desired ac output voltage level under varying loading
Furthermore, introducing high- and low-frequency switching conditions. The control, monitoring, and multiplexed outgoing
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26 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO. 1, WINTER 2023

Fig. 1. Schematic of the PV-based system configuration with the proposed SPμI and its control architecture.

processing are executed as per the concerned algorithms may be considered into two parts, namely, ON period and
simultaneously for MPPT, boost converter, and SPμI loading. OFF period for a switching period as shown in the following
Conventional perturb and observe (P&O) algorithm-based equations, considering a small voltage drop across MOSFET,
[19] MPPT control is included in this work considering its diode forward voltage, and voltage across resistive part of
advantages. inductor:
Vin
III. SPμI D ESIGN I L1 (+) = ∗ TON (1)
L
Aiming for a PV-based SPμI operating in standalone mode Vout− Vin
I L1 (−) = ∗TOFF (2)
at 230-V ac and 50-Hz frequency, an initial dc boosting L1
stage to accommodate the PV intermittency along with MPPT where I L1 is the change in current flowing through induc-
implementation is planned. Furthermore, considering human tor L 1 , Vin is the voltage across dc bus, Vout is the volt-
and equipment safety, a priority, isolated configuration; is a age across output terminals of interleaved boost converter
desirable feature at a little efficiency sacrifice. Considering the (see Fig. 1), and TON and TOFF depict ON and OFF time,
above requirements, a two-stage interleaved inductor configu- respectively.
ration with an HF transformer followed by rectification with Furthermore, as per energy conservation law, both energy
capacitive doublers voltage circuit is proposed as a boosting parts during switching on the period of the inductor and
stage. It includes interleaved inductor’s switching at HF by during discharge or transfer part, both (1) and (2) may be
opto-isolated gate drivers at more than 50% duty cycle, using equalized and considering switching duty D = TON /Ts , where
Si-GaN power devices to cancel 180◦ phase-shifted harmonics: Ts = (TON + TOFF ) and 1 − D = TOFF /Ts ; the equation may
while improving power density and reducing the volume of be solved as follows:
heat sinks. The application of the voltage doubler circuit in 1
the proposed SPμI results in a reduced turns ratio of the Vout = Vin . (3)
(1 − D)
transformer with low flux leakage and thus improved power
Considering various parameters as in [3], the output voltage
conversion operational efficiency at a reduced magnetic size.
in CCM is mentioned in the following equation:
The second design aspect is to make use of HF switching in
(Vin − I L1 ×R L1 ) D
the range from 10 to 35 kHz for the leg one and 50/60 Hz Vout = − Vd − Vds × . (4)
for the second one, as needed in the user’s zone. It helps to (1 − D) 1− D
minimize the switching losses over wide loading conditions To ensure ≥50% duty cycle for specified input–output voltage
and thus achieves higher overall operational efficiency. ratio, the duty cycle factor D value range could be chosen
as 0.65–0.7 for reducing flux leakage, and taking N as
A. Design of Interleaved Boost DC–DC Converter high-frequency transformer’s turn ratio is estimated as follows:
As per Fig. 1, under a steady-state condition in continuous Vout (1 − D)
N= . (5)
conduction mode (CCM), the total inductor switching period 2 ∗ V in
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TOMAR: EFFICIENT PV-BASED MICROINVERTER WITH ENHANCED ROI FOR LOWER ECONOMIC ZONE HABITANTS 27

The input power is found by rated output power by dividing The output electrolytic capacitor value and its ripples can be
it by a reasonable efficiency factor as follows: calculated as per the following equations:
Pout Iout ∗ D ∗ Ts
Pin = (6) Cout ≥ (17)
η Vmax
I L1 _ max
where Pin and Pout represent input and output power, respec- Icout = (18)
2∗N
tively, and η is the considered efficiency factor. where Icout is the current through capacitance Cout .
For ensuring power supply at 100% loading, the input The equivalent series resistance (ESR) is calculated by the
current and its corresponding rms value can be found as per following equation:
the following equations: Vmax
ESR = . (19)
Pin Iout
I L1_max = (7)
V Additional ripples due to ESR are added as per the following
in_min
2− D equation:
I L1_rms_max = I in_max . (8)  
2 Iout I L1
VoutESR = ESR × + . (20)
1− D 2
The average current of a switching cycle in the inductor can
be written as in the following equation: The breakdown voltage of the capacitor considering a 30%
margin may be found by the following equation:
TOFF Vout
I L1_average ∗ = I L1_average ∗ (1 − D) = Iout . (9) Vbrkdn ≥ 1.3 ∗ . (21)
Ts 2∗ N
It is observed that the average inductor current is propor- The rms value of the ripple current flowing to the capacitor is
tional to the output current at a given duty cycle. The given by the following equation:

maximum value of the output current can be calculated as D
follows: Icout_rms = Iout × . (22)
1− D
Pin The choice of low impedance aluminum capacitor is the cheap-
Ioutmax = . (10)
Vin_min est but offers higher ESR compared to tantalum and organic
semiconductor capacitor, which offers both low ESR and
To ensure CCM, the average inductor current at any time
higher capacitance. The inductor power losses are calculated
in the switching cycle should be given as in the following
by knowing the average inductor current, winding resistance,
equation:
and core losses as shown in the following equation:
I L1  2
I L1_min_average = . (11) I0
2 Pind = Rind + Pcore (23)
1− D
To ensure the CCM mode in all operating scenarios, 10% where Pind and Pcore represent inductor and core power losses,
is considered as the minimum loading, the corresponding respectively.
minimum power transfer is depicted in (12), and the limiting The diode conducts when the MOSFET switch is switched
load current is given in (13) OFF carrying the inductor current. It should be a low for-
ward voltage drop with fast switching time, sufficient current
Plimit = 10% ∗ Pin = 0.1 ∗ 250 = 25 W (12) carrying capability, and margin for breakdown voltage. The
1 Plimit
Ilimit = . (13) diode current should be at least two times the rms value of
2 Vin_max the output current. A Schottky diode is preferred until the
Another way of finding ripples current is by estimat- cost and complexity of the synchronous rectifier are justified.
ing 20%–40% of output current as in the following Diode power rating and junction temperature are important in
equation: the selection process. The diode breakdown voltage may be
considered as shown in the following equation:
Vout
I L1 = (0.2 to 0.4) × Io × . (14) Vdiode_brkdn ≥ 1.3 ∗ Vout . (24)
Vin_min
The N channel MOSFET is preferable due to its simplicity in
This shows that if a higher ripple current is considered, then gate driving circuitry. The power dissipation is given by the
the inductor value will be reduced following equation:
Vin_min ∗ D
L1 = . (15) PD_MOSFET
I L1 ∗ fmin  
Iout 2 1
= × RDS_ON × D + × Vout
The related diode current is given by the following equation: 1− D 2
 
√ Iin_max Iout 2
ID = 2− D∗ . (16) × (TON + TOFF ) × f s + Q g × Vgs × f s . (25)
2∗ N 1− D

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28 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO. 1, WINTER 2023

TABLE II TABLE IV
C OMPONENTS FOR DC–DC C ONVERTER AS AN P ROPERTIES OF S ELECTED F ERRITE C ORE M ATERIAL
I NTEGRAL PART OF THE SPμI FOR C OMPARATIVE S TUDY

central leg winding. A comparative study of the ferrite core

TABLE III material is included in Table IV for arriving at a distinctive
P ROJECTED D ESIGN S PECIFICATIONS OF HF T RANSFORMER conclusion.
The amount of energy lost as core losses is governed by core
properties. The energy stored in the core over one switching
period is governed by the following equation:
 T
ET = V (t) × i (t)dt. (28)
0
As per Faraday’s law
dB
.
V (t) = n × Ac (29)
dt
Furthermore, as Ampere’s law, it may be expressed as follows:
The junction temperature is estimated as per power losses
and ambient temperature conditions as follows: d H (t) n di (t) lcore
= or di (t) = d H (t). (30)
dt lcore dt n
T j = T A + PD × Rθ J A (26)
Substituting v(t) and i (t) in (27) using (30), it may be written
where T j and T A are junctions and ambient temperatures, as (31)
respectively, PD is power losses in the device, and Rθ JA is  T
the thermal resistance of the device. E T = lcore × Ac d B × d H (t) (31)
The above design procedure and calculations are considered  0
as the base while selecting the components for the interleaved E T = Volume H d B. (32)
dc–dc boost converter and the details are given in Table II.
Thus, (32) gives the total energy, which is consumed by the
core volume multiplied by the area of the B-H loop formed
B. High-Frequency Transformer Design during one switching cycle.
The projected design specification of the HF transformer is
tabulated in Table III. D. HF Transformer Design Calculation
The output power of the transformer can be derived as
follows: The core shape, its size, and power handling capacity are
investigated based on Wa Ac value, which is defined as follows,
Pin_txr
Ptxr = . (27) and the related magnetic data, which are published by the
ηtxr manufacturers, would be helpful in design calculations:
C. Overview of Magnetic Ferrite Core Properties Po×Dcma
Wa∗Ac = cm4 (33)
To maximize the effective inductance and winding area at K t × B× f
a minimized cost, weight, and volume, the design search for where Wa denotes the window area of core shape (cm2 ); Ac
optimal ferrite core shape is important in commanding flux denotes the effective cross-sectional area of core (cm2 ); Pmax
path, leakage, thermal heat dissipation without hot spots, and denotes the maximum power (W); K t denotes a constant,
core losses. In the EI core shape, the center leg shape is which is based on the topology of use; B denotes maximum
wounded round such that the radius of the winding wire is flux density in gauss; f denotes the switching frequency in
shorter and smooth in laying, resulting in reduced bending hertz; and Dcma denotes the current density in a circle.mils
stress along with better airflow aces and flux linkages, thus area/A.
achieving overall minimized winding losses and resulting The value of flux density B (1500 G) at a 30-kHz frequency
in 8%–11% higher efficiency compared to a square-shaped for a general-purpose ferrite material is selected based on the

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TOMAR: EFFICIENT PV-BASED MICROINVERTER WITH ENHANCED ROI FOR LOWER ECONOMIC ZONE HABITANTS 29

TABLE V is reduced, which in turn reduces the required amp-turn both

P OSSIBLE C ORE C HOICES AT 30-kHz O PERATION at the primary/secondary side. Selecting a high switching
frequency further reduces the required window area and core
size. Third, the core shape and its high permeability lock flux
leakage. Adding all these aspects helped in reducing overall
magnetic size.

TABLE VI
IV. D ESIGN C HECKS FOR E XPECTED P ERFORMANCE
M AGNETIC C ORE P ROPERTIES U NDER C ONSIDERATION FOR HF
T RANSFORMER
It is necessary to ensure the operation with thermal stability,
and therefore, design checks for projected temperature rise,
core losses, copper losses, and overall efficiency are important
for the design process. The following considerations are made.
1) Winding Factor: Low fill factor (30% single layer) has
lessened the utilization but provides ease in manufactur-
ing with less capacitance. The normal fill factor value
is between 35% and 45%. High fill factor winding-core
utilization of up to 65% is achievable.
2) Mean Length Per Turn (MLT) and DC Resistance Ver-
ification: The wire gauge, MLT, number of turns, and
winding factor should be verified from the data table
manufacturer’s data considering frequency–flux plots. Based for resistance value.
on the above Wa Ac value in (30), the following cores with 3) Copper Losses: The copper loss for dc resistance and
power handling capability as shown in Table V may be ac impedance should be estimated.
considered and compared for selection. 4) Core Losses: If the ac losses are too high and heating
Based on the above core properties, Wa Ac is studied in is involved, then the use of a larger core and/or low
Table VI for further refinement. The values corresponding permeability should be considered to reduce ac flux
to the EE core shape 280 W depict an optimized design density.
solution, and however, toroid (at S.no. 3) would be a safer
The chart fit-based core loss is governed as follows:
choice considering less saturation possibility, performance, and
light in weight. Furthermore, another alternative could be the Ploss = a × Bpeak
b
× f c mW/cm3 (38)
third EE core with the round shape at the center (at S.no. 3)
will hold winding with a lower fill factor. Other important where Ploss is core losses in mW/cm3 ; a, b, and c are the
considerations are resulting cost and ease of availability. curve fitting constants as per manufacturer; Bpeak is the flux
The next step is to find a primary number of turns using density at ac flux swing at peak location (Tesla); and f is the
the following equations: frequency in kilohertz.
Furthermore, Bpeak may be expressed as follows:
V p × 108 ×D max
Np = (34) B Bac_max−Bac_min
4 × B × Ac× × f Bpeak = = . (39)
Ns = N × N p Turns. (35) 2 2
The value of flux density from field intensity H (A.T/cm),
Considering the skin effect impact, the current penetration which involves winding variables, is expressed as follows:
depth is calculated as follows:   
N I
66.2 66.2 Hac_max = Idc + (40)
δ= √ = √ = 0.3822 mm. (36) l 2
f 30 000  e 
N I
To avoid skin effect, the maximum wire diameter is given by Hac_min = Idc − . (41)
le 2
d = 2δ = 0.76 mm. (37) Therefore, the field H may be worked out from variable values
2
Considering 5 A/mm current density, the primary wire area and using (8), (14), (40), and (41) in (39)
and the wire diameter result as 2.9 mm2 and 1.92 mm,
Ploss_txr = Ploss × le × Ae mW. (42)
respectively. The primary-side wire gauge is 13 AWG with
2.84 mm2 and the resistance value is 0.00656 /m in length. The MLT is 50 mm; the primary number of turns is 10,
Similarly, the secondary wire cross-sectional area is calculated the resistance value is 0.00656 /m (for 13-gauge wire), the
as 0.172 mm2 and the diameter as 0.46 mm corresponds to primary current is 14.3 A, and the primary copper losses work
24 gauge with 0.25-mm2 cross-sectional area and the corre- out to be 0.67 W. Similarly, the secondary turns is 25, the
sponding current carrying capacity as 1.02 A, with a resistance resistance value is 0.08422 , and the secondary-side copper
value of 0.08422 /m. losses are 0.0467 W. The total copper losses are 0.7167 W. The
With the amalgamation of the voltage doubler scheme just estimated core losses and copper losses are 2.37% and 0.277%,
after interleaved dc–dc stage, the ratio of output/input voltage respectively. The total losses are 6.8467 W, which is 2.3727%

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30 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO. 1, WINTER 2023

of the rating of the HF transformer. The estimated losses are

2.373%, and therefore, the estimated design efficiency is given
by the following equation:
Po
Efficiency(estimated) = ηestimated = . (43)
Po + Plosses_txr
Temperature Rise: The heat generation due to copper and
core losses should be dissipated, but there are many factors
such as core shape, winding factor, surface area, mounting, Fig. 2. Voltage response of PV, dc bus, and BES.
ventilation, and ambient temperature. An estimation based on
a 40% fill factor is given in the following equation:
 0.833
◦ Total Losses(mW)
T ( C) = . (44)
Component Surface Area cm2
Considering the toroid selected size as (36 × 23 × 15) mm,
the unwound surface area is 3400 mm2 with a 50% fill factor
(68.00 cm2 ). As the losses are 2.37%, this temperature rise
is reasonable. However, if further temperature rise is to be
reduced, the next higher core size (46.7 × 24.1 × 18 mm) Fig. 3. Power response of PV, dc bus, load, and BES.
may be necessary with increased unwound surface area as
6900 mm2 , and with a 50% fill factor, the temperature rise C. Bridge MOSFET Device Sizing
will be limited to 23.3 ◦ C as per the above equation. The load may be considered at a power factor of 0.6 (Io as
1.8 A), switching frequency as 8 kHz for the high-frequency
A. Output Rectifier Stage leg and 50 Hz for the low-frequency leg; taking common
The rectification operation is influenced by the intrinsic MOSFET device for both legs of the bridge, the thermal losses
properties of the diode, the transition time of change of state are given as follows:
from OFF to ON and vice versa, and the behavior of voltage PD_MOSFET
and current during the transition. The peak voltage across  2
Io 1
the diode due to transformer leakage inductance and internal = × RDS_ON × D + × Vo
inductance of the diode may impact an additional 30%–40%, 1− D 2
 2
apart from dc bus voltage and maximum ac voltage as 324 V, Io
× Tsw_ON + Tsw_OFF × f s + Q g × Vgs × f s .
and therefore, the resultant maximum peak could be 843 V. 1− D
The diode peak current may be found by a transformer ratio (48)
as 5.7 A. The selected diode is of 16 A, 1200-V rating.
V. S IMULATION R ESULTS
B. HF Transformer Design Calculation The list of designed hardware components based on the
discussed design and calculation is presented in Table VII.
The SPμI produces a time-varying sinusoidal current with
To validate the functional aspects of the proposed SPμI,
a phase angle difference ϕ as expressed in the following
system configuration (see Fig. 1) is simulated in a MATLAB
equation:
environment and a snapshot of obtained responses is presented
Po (t) = Vo Cos(ωt) ∗ Io Cos(ωt − ϕ). (45) in this section. Although the simulation has been performed
considering various scenarios to understand the system per-
Furthermore, (42) may be break up into two parts as the sum of
formance at morning, day, and evening times, due to space
average power and a time-varying sinusoidal current at twice
and similarities reasons, one such simulation performance is
the grid frequency as shown in the following equation:
presented in Figs. 2–4. The voltage stability at the PV stage
1 1 working with MPPT at 100% irradiance is shown in Fig. 2.
Vo Io + Vo Io Cos2ωt.
Po (t) = (46)
2 2 The next important node on the power side is a two-stage
Based on (46), considering ripples magnitude up to 40% of the interleaved boost converter neutralizing harmonics due to 180◦
supply voltage at twice the grid frequency, the capacitor across shifted switching across HF transformer with comparatively
the dc bus is necessary to act as a buffer during instantaneous low turns ratio, and however, its step-up secondary is being
power change during MPPT at PV panels, ripples, and load rectified by diode-capacitive-based voltage doubler bridge.
fluctuations, which may be calculated as follows: This reasonably good voltage stability is observed due to CCM
mode working and reduced ripples and harmonics. The BES
Po
Cdc = . (47) is being charged up to 84% and further is being limited due
2π f × Vripple × Vo to additional load (see Fig. 3) across the inverter.
Here, the selected value could be twice the calculated value, The power flow from the PV panel toward BES and
and hence, 47-μF rating 450-V four numbers may be selected. simultaneously toward interleaved boost converter following

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TOMAR: EFFICIENT PV-BASED MICROINVERTER WITH ENHANCED ROI FOR LOWER ECONOMIC ZONE HABITANTS 31

TABLE VII
L IST OF D ESIGNED H ARDWARE C OMPONENTS OF μI

Fig. 4. (a) SPμI output voltage. (b) SPμI output current.

MPPT execution is shown in Fig. 3. It is being controlled

by adjusting the duty cycle to maintain the current CCM
mode so that varying load power is supported. The role of
analog-to-digital converter (ADC) sampling and filtering is
Fig. 5. SPμI waveform at prestage and output ac stage.
important and followed by its algorithmic implementation by
a microcontroller, which is responsible for such functions,
as shown in Fig. 3. In case load power is not fully met
by PV panels, it will draw additional power from BES. The
simulation shown in Fig. 4(a) and (b) are related to ac voltage
and current at the output stage of SPμI. In normal conditions,
the current waveform is sinusoidal as per 50-Hz frequency. The
voltage wave shape is symmetrical in shape with its magnitude
value. Thus, the overall output stage is performing well at its
full load variation range. It will be seen in the next section that
the simulation results are well matching with the experimental
Fig. 6. BES scenario of burst charging and deep discharge.
hardware performance.

VI. R EAL -T IME F IELD H ARDWARE R ESULTS AND

A NALYSIS
After a preliminary design, simulation, and laboratory-
based prototype development referring to Fig. 1, the SPμI
was de-snagged for day performance assessment, to validate
its performance and response with PV setup at real-field
location (latitude: 26.431◦ and longitude: 74.707◦). Energy
extraction under varying irradiance in a harsh environment is a
primary objective to finalize technoeconomic parameters such Fig. 7. DC bus current during varying load conditions.
as efficiency under a wide range of load variation and, finally,
a per watt efficiency comparison with a market-selected 500-W
inverter [21], [22]. duration are covered in Fig. 6. Furthermore, Fig. 7 shows the
The day-performing observations related to PV genera- change in injected current during varying load conditions.
tion, load, BES support data, and efficiency are recorded in There are two power stages in the proposed SPμI (see
Table VIII. As observed in Table VIII and Fig. 5, a close Fig. 1). The first one is the prestage dc bus, which is
similarity between the observed results and the recorded mea- being evaluated to assess its various losses at a fixed 30-kHz
surement data has been observed. The obtained SPμI output switching frequency. The primary data for a day are tabulated
sinusoidal waveform is free from notches and overlapping in Table IX.
of unwanted harmonic ripples. BES charging during excess Despite varying input irradiance from morning to evening,
energy cases (lower load and good weather scenario) and the prestage dc bus is stabilized. For high-efficiency achieve-
its support up to discharge limit under bad weather or night ment up to 96.35%, there are three major contributions:

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32 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO. 1, WINTER 2023

TABLE VIII
P ERFORMANCE D URING D AYTIME AND SPμI E FFICIENCY
D ETERMINATION

Fig. 10. SPμI efficiency comparison at different loading conditions.

TABLE IX
I NTERLEAVED B OOST DC–DC C ONVERTER AS P RESTAGE OF THE SPμI
AT 30 K H Z

Fig. 11. SPμI losses during the whole day.

Fig. 8. Inductor current under CCM of operation.

Fig. 12. PWM switching of prestage interleaved boost converter of SPμI.

Fig. 9. Hourly efficiency performance of the proposed SPμI.

1) interleaving inductor’s switching for harmonic cancellation

with PWM duty cycle control under CCM mode; 2) Si-GaN
base MOSFET responsible for high power density PCB; and
3) good permeability base core and low turns ratio of HF Fig. 13. Opto-isolated gate driver TTL waveform.
transformer. The MOSFET losses data are based on the design
procedure (45). Magnetic core losses are derived via the man-
ufacturer’s software simulation and other recommendations Starting from the morning, say, if the PV power is insuffi-
[20]. A snapshot of the inductor current during CCM mode is cient, the load is supported by BES also. On a later day time,
shown in Fig. 8. when PV power with MPPT is sufficient, the BES starts getting

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TOMAR: EFFICIENT PV-BASED MICROINVERTER WITH ENHANCED ROI FOR LOWER ECONOMIC ZONE HABITANTS 33

Fig. 14. Experimental step-up for the proposed SPμI.

charged. This type of coordination among PV MPPT and TABLE X

prestage interleaved booster converter working in CCM mode T ECHNOECONOMIC F EASIBILITY A NALYSIS
with varying load is achieved at reasonably good efficiency
(see Fig. 9) throughout the day. As load varies, the PWM
duty of the booster stage is changed to compensate for load
power and regulates MPPT action in a synchronized manner
under the CCM mode of operation.
As remote/rural load varies with a wide range due to eco-
nomic conservative inclinations, the prototype was extensively
tested from 10% to 100% load variation so that hidden losses
are identified. The efficiency is found 91.73% at the rated
load and fallen to 77.74% at 10% load (see Fig. 10). It is
due to the fact that minimum magnetic energization and flux
leakage may not be fully avoided or else costlier magnetic
cores may be used. In phase II, more refinement is expected,
especially by improving switching frequency and synchronous
rectification. Recently, research work on the use of IC for
controlling the electrolytic size is going on. The performance
of the 500-W base inverter selected from the market is also
included in Fig. 10 for efficiency comparison. Its efficiency is
66.68% at 10% load and 87.35% at rated load capacity. Apart
from overall efficiency, other economic parameters are being
compared on a per watt basis in the next section. basis (excluding BES), a comparison to the system illustrated
Optimization of the SPμI power stage is one such area in [21] and [22] has been presented in Table X. The following
where extensive alternative evaluations are needed. The considerations are considered for energy yield, cost, and ROI
present data are based on 17 kHz for the first leg and 50 Hz for comparison.
the second one. MOSFET switching losses, core losses, copper
losses, and boosting prestage losses are shown in Fig. 11. The 1) Total investment, i.e., the amount which is being spent
PWM switching waveforms of interleaved booster converter as in procurement and commissioning of setup for the
prestage of SPμI are shown in Fig. 12. For the opto-isolated start-up.
gate driving TTL, waveforms in Fig. 13 may be referred. 2) Estimated life of equipment/setup (considered as ten
A reasonably enhanced efficiency of 96.35% is observed at years).
100% load and 80.48% at 10% load. The Si-GaN losses 3) Energy yield (kilowatthour) saving due to higher
are 1.96 W, while core losses are 3.5 W under rated load efficiency.
conditions (see Table IX). 4) The daily energy yield period is 6 h.
5) The average energy is estimated on a daily/per
month/per year basis for the whole year with varying
VII. T ECHNOECONOMIC G AINS season considerations. The average energy yield is con-
Based on the bill of material for the whole off-grid power sidered by the number of kilowatthour units, which are
setup of the PV panel with SPμI on a per unit power (watt) multiplied by per unit energy cost (INR 10/kWh).

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34 IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, VOL. 46, NO. 1, WINTER 2023

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A PPENDIX com/Upload/PDF/TS-400/TS-400-SPEC.PDF
The experimental setup and the developed prototype for the
proposed work are shown in Fig. 14.

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power decoupling function,” in Proc. Int. Power Electron. Conf. (ECCE cal Energy Systems Group, Eindhoven University of Technology (TU/e),
ASIA), Jun. 2010, pp. 2918–2923. Eindhoven, The Netherlands, and has completed European Commission’s
[8] S. Jana and S. Srinivas, “An approach to mitigate line frequency Horizon 2020, UNITED GRID, and UNICORN TKI Urban Research projects.
harmonics in a single-phase PV-microinverter system,” IEEE Trans. She has committed her research work efforts toward the development of
Power Electron., vol. 34, no. 12, pp. 11521–11525, Dec. 2019. sustainable, energy-efficient solutions for the empowerment of society, and
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products/mine-cap/mine-cap/min1072m reputed international, national journals, and conferences. She has granted and
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phase grid connected transformer-less solar micro-inverter topology with distribution systems, artificial intelligence and machine learning applications
power decoupling capability,” in Proc. IEEE Int. Conf. Power Electron., in power systems, energy conservation, and automation.
Drives Energy Syst. (PEDES), Dec. 2020, pp. 1–6. Dr. Tomar is a Life Member of ISTE, IETE, IEI, and IAENG.

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