FA3687V

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FUJI Power Supply Control IC

FA3687V

Application Note

May –2001
Fuji Electric Co., Ltd.
Matsumoto Factory

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WARNING
1.This Data Book contains the product specifications, characteristics, data, materials, and structures as of May 2001.
The contents are subject to change without notice for specification changes or other reasons. When using a
product listed in this Data Book, be sure to obtain the latest specifications.

2. All applications described in this Data Book exemplify the use of Fuji's products for your reference only. No right or
license, either express or implied, under any patent, copyright, trade secret or other intellectual property right
owned by Fuji Electric Co., Ltd. is (or shall be deemed) granted. Fuji makes no representation or warranty,
whether express or implied, relating to the infringement or alleged infringement of other's intellectual property
rights, which may arise from the use of the applications, described herein.

3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of semiconductor products
may become faulty. When using Fuji Electric semiconductor products in your equipment, you are requested to
take adequate safety measures to prevent the equipment from causing a physical injury, fire, or other problem if
any of the products become faulty. It is recommended to make your design fail-safe, flame retardant, and free of
malfunction.

4.The products introduced in this Data Book are intended for use in the following electronic and electrical equipment,
which has normal reliability requirements.
• Computers • OA equipment • Communications equipment (pin devices)
• Measurement equipment • Machine tools • audiovisual equipment • electrical home appliances
• Personal equipment • Industrial robots etc.

5.If you need to use a product in this Data Book for equipment requiring higher reliability than normal, such as for the
equipment listed below, it is imperative to contact Fuji Electric to obtain prior approval. When using these products
for such equipment, take adequate measures such as a backup system to prevent the equipment from
malfunctioning even if a Fuji's product incorporated in the equipment becomes faulty.
• Transportation equipment (mounted on cars and ships) • Trunk communications equipment
• Traffic-signal control equipment • Gas leakage detectors with an auto-shut-off feature
• Emergency equipment for responding to disasters and anti-burglary devices • Safety devices

6. Do not use products in this Data Book for the equipment requiring strict reliability such as (without limitation)
• Space equipment • Aeronautic equipment • Atomic control equipment
• Submarine repeater equipment • Medical equipment

7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be reproduced in
any form or by any means without the express permission of Fuji Electric.

8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales agents before using the
product. Neither Fuji nor its agents shall be liable for any injury caused by any use of the products not in
accordance with instructions set forth herein.

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CONTENTS

page
1. Description ･･･････････････････ 4
2. Features ･･･････････････････ 4
3. Outline ･･･････････････････ 4
4. Block diagram ･･･････････････････ 5
5. Pin assignment ･･･････････････････ 5
6. Ratings and characteristics ･･･････････････････ 6
7. Characteristic curves ･･･････････････････ 10
8. Description of each circuit ･･･････････････････ 17
9. Design advice ･･･････････････････ 21
10. Application circuit ･･･････････････････ 25

Note
• Parts tolerance and characteristics are not defined in all application described in this Data book. When design an
actual circuit for a product, you must determine parts tolerances and characteristics for safe and stable operation.

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1. Description

FA3687V is a PWM type DC-to-DC converter control IC with 2ch outputs that can directly drive power MOSFETs.
CMOS devices with high breakdown voltage are used in this IC and low power consumption is achieved. This IC is
suitable for very small DC-to-DC converters because of their small and thin package (1.1mm max.), and high
frequency operation (to 1.5MHz). You can select Pch or Nch of MOSFETs driven, and design any topology of DC-to-
DC converter circuit like a buck, a boost, a inverting, a fly-back, or a forward.

2. Features

・ Wide range of supply voltage: VCC=2.5 to 20V

・ MOSFET direct driving
・ Selectable output stage for Pch/Nch MOSFET on each channel
・ Low operating current by CMOS process: 2.5mA (typ.)
・ 2ch PWM control IC
・ High frequency operation: 300kHz to 1.5MHz
・ Simple setting of operation frequency by timing resistor
・ Soft start function at each channel
・ Adjustable maximum duty cycle at each channel
・ Built-in undervoltage lockout
・ High accuracy reference voltage: VREF: 1.00V±1%, VREG: 2.20V±1%
・ Adjustable built-in timer latch for short-circuit protection
・ Thin and small package: TSSOP-16

3. Outline

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4. Block diagram
⑬ ＶＲＥＧ ⑥ ＶCC ⑦ CS2 ⑩ CS1

ＵＶＬＯ
Reference 2.20V
voltage
Soft
Regulated
1.00V start
voltage

⑫ RT Oscillator

Er.Amp.1
Comp.1
＋
＋ N/P ch.
⑭ IN1- − ⑨ OUT1
− drive

⑮ FB1
Er.Amp.2 ⑯ SEL1
⑤ IN2+ ＋ Comp.2
− N/P ch.
④ IN2- − drive ⑧ OUT2
＋

③ FB2
② SEL2

FB voltage
detection

Timer
latch

① CP ⑪ GND

5. Pin assignment
Pin Pin
Description
No. symbol
1 CP Timer latched short circuit protection
2 SEL2 Selection of type of driven MOSFET (OUT2)
3 FB2 Ch.2 output of error amplifier
4 IN2- Ch.2 inverting input to error amplifier
5 IN2+ Ch.2 non-inverting input to error amplifier
6 VCC Power supply
7 CS2 Soft start for Ch.2
8 OUT2 Ch.2 output
9 OUT1 Ch.1 output
10 CS1 Soft start for Ch.1
11 GND Ground
12 RT Oscillator timing resistor
13 VREG Regulated voltage output
14 IN1- Ch.1 inverting input to error amplifier
15 FB1 Ch.1 output of error amplifier
16 SEL1 Selection of type of driven MOSFET (OUT1)

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6. Ratings and characteristics
(1) Absolute maximum ratings

Item Symbol Test condition rating Unit

Power supply voltage VCC 20 V
SEL1・SEL2 pin voltage VSEL -0.3 to 5.0 V
FB1・IN1-・FB2・IN2-・IN2+
VEA_IN -0.3 to 5.0 V
pin voltage
CS1･CS2･CP･RT･VREG
VCTR_IN -0.3 to 5.0 V
pin voltage
OUT1/2 OUT pin source current IOUT- -400(peak) mA
OUT pin sink current IOUT+ 150(peak) mA
OUT1/2 OUT pin source current IOUT- -50(continuous) mA
OUT pin sink current IOUT+ 50(continuous) mA
Power dissipation ※1 Pd Ta≦25℃ 300 mW
Operating junction temperature TJ +125 ℃
Operating ambient temperature TOPR -30 to +85 ℃
Storage temperature TSTG -40 to +125 ℃
※1 Derating factor Ta≧25℃ : 3mW/℃
Maximum power dissipation curve
350
Maximun power dissipation

300
250
200
[mW］

150
100
50
0
-30 0 30 60 90 120 150
Ambient temperature [℃]
(2) Recommended operating conditions
Item Symbol Test condition MIN. TYP. MAX. Unit
Supply voltage VCC 2.5 ‐ 18 V
CS1･CS2･CP pin voltage VCTR_IN 0.0 ‐ 2.5 V
SEL1･SEL2 pin voltage VSEL_IN 0.0 - 2.5 V
IN1-･IN2-･IN2+ pin voltage VEA_IN 0.0 ‐ 2.5 V
Oscillation frequency fOSC 300 500 1500 kHz
Vcc＜10V 0.1 1.0 4.7 μF
VREG pin capacitance CREG
10V≦Vcc＜18V 0.47 1.0 4.7 μF
VREG pin current IREG ‐ ‐ 1.0 mA
VCC pin capacitance CVCC 1.0 ‐ ‐ μF
CS1 pin capacitance CCS1 Between CS1 and GND 0.01 ‐ ‐ μF
CS2 pin capacitance CCS2 Between CS2 and VREG 0.01 ‐ ‐ μF
CP pin capacitance CCP Between CP and VREG ※2 ０．０１ ― ― μＦ
※2. If the timer latched mode is not needed, connect the CP pin to GND.

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(3) Electrical characteristics

* The characteristics is based on the condition of VCC=3.3V, CREG=1.0μF, RT=12kΩ, Ta=+25℃, unless
otherwise specified.

(1) Regulated voltage for internal control blocks (VREG pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
Regulated voltage VREG 2.178 2.200 2.222 V
Line regulation VREG_LINE VCC=2.5 to 18V ― ±5 ±15 mV
Load regulation VREG_LOAD IREG=0 to 1mA -5 -1 mV
Variation with temperature VREG_TC Ta=-30 to +85℃ ±0.5 %

(2) Oscillator section (RT pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
Oscillation frequency fOSC 435 500 565 kHz
Line regulation fOSC_LINE VCC=2.5 to 18V ― ±1 ±5 %
Variation with temperature fOSC_TC1 Ta=-30 to +85℃ ±3 %

(3) Error Amplifier section (IN1-・FB1・IN2-・IN2+・FB2 pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
Reference voltage (ch.1) VREF1 ※3 0.99 1.00 1.01 V
VREF1 Line regulation (ch.1) VREF_LINE VCC=2.5 to 18V ― ±2 ±5 mV
VREF1Variation VREF_TC1 Ta=-30 to +85℃ ±0.5 %
with temperature (ch.1)
Input offset voltage (ch.2) VOFFSET VIN2+=1.0V，IN2+・IN2- ― ― ±10 ｍＶ
VOFFSET Line regulation (ch.2) VOFF_LINE VCC=2.5～18V 0 ｍＶ
Input bias current IIN- VINx-=0.0 to 2.5V 0.0 mA
Common mode input voltage VCOM IN2+・IN2- 0.7 1.5 Ｖ
Open loop gain AVO 70 dB
Unity gain bandwidth fT 1.5 MHz
Output current (sink) ISIFB VFB1=0.5V,VIN1-=VREG 2.3 3.5 4.7 mA
VFB2=0.5V,VIN2-=VREG,VIN2+=1V
Output current (source) ISOFB VFB1=VREG-0.5V,VIN1-=0V -360 -270 -180 μA
VFB2=VREG-0.5V,VIN2-=0V,VIN2+=1V

* 3: The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of
the error amplifier is included.

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(4) Soft start section (CS1・CS2 pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
VCS1D0N Duty cycle=0%, VFB1=1.4V 0.82 Ｖ
Threshold voltage (CS1) VCS1D20N Duty cycle =20%, VFB1=1.4V 0.89 0.925 0.96 Ｖ
(Driving Nch-MOSFET) VCS1D80N Duty cycle =80%, VFB1=1.4V 1.25 1.285 1.32 Ｖ
VCS1D100N Duty cycle =100%, VFB1=1.4V 1.38 Ｖ
VCS1D0P Duty cycle =0%, VFB1=1.4V 0.82 Ｖ
Threshold voltage (CS1) VCS1D20P Duty cycle =20%, VFB1=1.4V 0.90 0.935 0.97 Ｖ
(Driving Pch-MOSFET) VCS1D80P Duty cycle =80%, VFB1=1.4V 1.26 1.295 1.33 Ｖ
VCS1D100P Duty cycle =100%, VFB1=1.4V 1.38 Ｖ
VCS2D0N Duty cycle =0%, VFB2=0.7V 1.33 Ｖ
Threshold voltage (CS2) VCS2D20N Duty cycle =20%, VFB2=0.7V 1.21 1.245 1.28 Ｖ
(Driving Nch-MOSFET) VCS2D80N Duty cycle =80%, VFB2=0.7V 0.85 0.885 0.92 Ｖ
VCS2D100N Duty cycle =100%, VFB2=0.7V 0.80 Ｖ
VCS2D0P Duty cycle =0%, VFB2=0.7V 1.33 Ｖ
Threshold voltage (CS2) VCS2D20P Duty cycle =20%, VFB2=0.7V 1.20 1.235 1.27 Ｖ
(Driving Pch-MOSFET) VCS2D80P Duty cycle =80%, VFB2=0.7V 0.84 0.875 0.91 Ｖ
VCS2D100P Duty cycle =100%, VFB2=0.7V 0.80 Ｖ

(5) Pulse width modulation (PWM) section (FB1・FB2 pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
VFB1D0N Duty cycle =0%, VCS1=VREG 0.82 Ｖ
Threshold voltage (FB1) VFB1D20N Duty cycle =20%, VCS1=VREG 0.925 Ｖ
(Driving Nch-MOSFET) VFB1D80N Duty cycle =80%, VCS1=VREG 1.285 Ｖ
VFB1D100N Duty cycle =100%, VCS1=VREG 1.38 Ｖ
VFB1D0P Duty cycle =0%, VCS1=VREG 0.82 Ｖ
Threshold voltage (FB1)
VFB1D20P Duty cycle =20%, VCS1=VREG 0.935 Ｖ
(Driving Pch-MOSFET)
VFB1D80P Duty cycle =80%, VCS1=VREG 1.295 Ｖ
VFB1D100P Duty cycle =100%, VCS1=VREG 1.38 Ｖ
VFB2D0N Duty cycle =0%, VCS2=0V 1.33 Ｖ
Threshold voltage (FB2) VFB2D20N Duty cycle =20%, VCS2=0V 1.245 Ｖ
(Driving Nch-MOSFET) VFB2D80N Duty cycle =80%, VCS2=0V 0.885 Ｖ
VFB2D100N Duty cycle =100%, VCS2=0V 0.80 Ｖ
VFB2D0P Duty cycle =0%, VCS2=0V 1.33 Ｖ
Threshold voltage (FB2) VFB2D20P Duty cycle =20%, VCS2=0V 1.235 Ｖ
(Driving Pch-MOSFET) VFB2D80P Duty cycle =80%, VCS2=0V 0.875 Ｖ
VFB2D100P Duty cycle =100%, VCS2=0V 0.80 Ｖ

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(6) Timer latch protection section (CP pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
Threshold voltage of FB1 VTHFB1TL ※6-1 1.5 ― 2.0 V
Threshold voltage of FB2 VTHFB2TL ※6-2 0.2 ― 0.6 V
Threshold voltage of CS1 VTHFB3TL ※6-3 0.2 ― 0.6 V
Threshold voltage of CS2 VVTHCS1TL ※6-4 1.5 ― 2.0 V
Charge current of CP ICP VCP=0.5V,VFB1=2.1V -2.4 -2.0 -1.5 μA
Threshold voltage of CP VTHCPTL 1.6 ― 2.1 V

(7) Under voltage lockout circuit section (VCC pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
ON threshold voltage of VCC VUVLO 2.0 2.2 2.35 V
Hysteresis voltage ΔVUVLO 0.1 V

(8) Output section (OUT1・OUT2･SEL1･SEL2 pin)

Item Symbol Test condition MIN. TYP. MAX. Unit
IOUT2=-50mA 10 20 Ω
High side on resistance
RONHI IOUT1=-50mA,VCC=5V 9 Ω
of OUT1/2
IOUT1=-50mA,VCC=15V 8 Ω
IOUT1=50mA 5 10 Ω
Low side on resistance
RONLO IOUT2=50mA,VCC=5V 5 Ω
of OUT1/2
IOUT2=50mA,VCC=15V 5 Ω
Rise time of OUT1/2 tRISE CL=1000pF 25 ns
Fall time of OUT1/2 tFALL CL=1000pF 40 ns
SEL pin voltage for driving
VSELN 0.0 ― 0.2 Ｖ
Nch-MOSFET
SEL pin voltage for driving
VSELP VREG-0.2 ― VREG Ｖ
Pch-MOSFET

(9) Overall section

Item Symbol Test condition MIN. TYP. MAX. Unit
ICCA Ch.1, Ch.2 operating mode 2.5 3.5 mA
Operating mode ICCA1 Ch.1, Ch.2 off mode 2.0 mA
supply current ICCA2 Ch.1, Ch.2 operating mode, Vcc=18V 3.0 mA
ICCA3 Latch mode 2.0 mA

*6-1: The current source of the CP pin operates when the voltage of FB1 exceeds the threshold voltage as shown in the
table.
*6-2: The current source of the CP pin operates when the voltage of FB2 falls below the threshold voltage as shown in the
table.
* 6-3: The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table.
* 6-4: The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table.

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7. Characteristic curves

Oscillation frequency vs.Timing resistor Oscillation frequency vs. Supply voltage Vcc
Vcc=3.3V,Ta=25℃ Ta=25℃,RT=12kΩ(fosc=500kHz)
1800 510
1600 508

Oscillation frequency [kHz]

Oscillation frequency [kHz]

1400 506
504
1200
502
1000
500
800 498
600 496
400 494

200 492
490
0
0 5 10 15 20
1 10 100
Timing resistor R T[kΩ] Vcc [V]

Oscillation frequency vs. ambient temperature Regulated voltage vs. Supply voltage Vcc
Vcc=3.3V,RT=12kΩ(fosc=500kHz) Ta=25℃,RT=12kΩ(fosc=500kHz)
570 2.23

550 Load current

2.22
Oscillation frequency [kHz]

Regulated voltage V REG[V]

IREG=0A
530
2.21
510
2.20
490
2.19
470

450 2.18

430 2.17
-50 -25 0 25 50 75 100 125 150 0 5 10 15 20
Ambient temperature Ta [℃] Vcc[V]

Regulated voltage vs. ambient temperature Regulated voltage vs. load current
Vcc=3.3V,RT=12kΩ(fosc=500kHz) Vcc=3.3V,RT =12kΩ(fosc=500kHz)
2.23 2.23

2.22 2.22
Regulated voltage V REG[V]

Regulated voltage V REG[V]

Ta=85℃
2.21 2.21

2.20 2.20
Ta=25℃
2.19 2.19

Ta=-30℃
2.18 2.18

2.17 2.17
-50 -25 0 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Ambient temperature Ta[℃] Load current IREG[mA]

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Reference voltage vs. Supply voltage Vcc Reference voltage vs. ambient temperature
Ta=25℃,RT=12kΩ(fosc=500kHz) Vcc=3.3V,RT=12kΩ(fosc=500kHz)
1.020 1.020
1.015 1.015
Reference voltage V REF [V]

Reference voltage V REF[V]

1.010 1.010
1.005 1.005
1.000 1.000
0.995 0.995
0.990 0.990

0.985 0.985
0.980 0.980
0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 150
Vcc[V] Ambient temperature Ta[℃]

Error amp. Output current(sink) vs. Error amp. Output current(source) vs.
ambient temperature ambient temperature
5.0 Vcc=3.3V,RT=12kΩ(fosc=500kHz) -150
Vcc=3.3V,RT=12kΩ(fosc=500kHz)
Output current (source) ISOFB[uA]
Output current (sink) ISIFB [mA]

4.5
-200
4.0

3.5 -250

3.0
-300
2.5

2.0 -350
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Ambient temperature Ta[℃] Ambient temperature Ta[℃]

charge current of CP vs. ambient temperature Threshold voltage of CP vs. ambient temperature
Vcc=3.3V,RT=12kΩ(fosc=500kHz) Vcc=3.3V,RT=12kΩ(fosc=500kHz)
-1.0 2.3

2.2
Charge current of CP[uA]

Threshold voltage of CP [V]

-1.5 2.1

2.0
-2.0
1.9

1.8
-2.5
1.7

-3.0 1.6
-50 -25 0 25 50 75 100 125 150
1.5
Ambient temperature Ta[℃] -50 -25 0 25 50 75 100 125 150
Ambient temperature Ｔａ[℃]

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Output duty cycle vs.CS voltage (ch.1) Output duty cycle vs.
Oscillation frequency (ch.1)
100 100
fosc=300kHz VCS1=1.35V Driving Nch MOSFET
90 fosc=500kHz 90 VCS1=1.30V
Vcc=3.3V，Ta=25℃

80 80 VCS1=1.25V
Output duty cycle (ch.1) [％]

Output duty cycle (ch.1) [％]

70 70 VCS1=1.20V
fosc=760kHz
60 60
VCS1=1.15V

fosc=1.5MHz VCS1=1.10V
50
50
VCS1=1.05V
40
40
VCS1=1.00V
30 Driving Nch MOSFET
Vcc=3.3V，Ta=25℃ 30 VCS1=0.95V

20 VCS1=0.90V
20
10 VCS1=0.85V
10
0
0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0
VCS1 [V] 300 500 700 900 1100 1300 1500
oscillation frequency [ｋＨｚ]

Output duty cycle vs.CS voltage (ch.1) Output duty cycle vs.
Oscillation frequency (ch.1)
100 100
fosc=300kHz
90 90
VCS1=1.35V Driving Pch MOSFET
fosc=500kHz Vcc=3.3V，Ta=25℃
80 80 VCS1=1.30V
Output duty cycle (ch.1) [％]

Output duty cycle (ch.1) [％]

VCS1=1.25V
70 70
VCS1=1.20V
60 fosc=760kHz 60
VCS1=1.15V
50
50 VCS1=1.10V
fosc=1.5MHz
40
40 VCS1=1.05V

30 VCS1=1.00V
Driving Pch MOSFET 30
20 Vcc=3.3V，Ta=25℃ VCS1=0.95V
20
VCS1=0.90V
10
10
VCS1=0.85V
0
0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0
VCS1 [V] 300 500 700 900 1100 1300 1500
Oscillation frequency [kHz]

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Output duty cycle vs.CS voltage (ch.2) Output duty cycle vs.
Oscillation frequency (ch.2)
100 100
fosc=300kHz VCS2=0.80V Driving Nch MOSFET
90 90 Vcc=3.3V，Ta=25℃
fosc=500kHz VCS2=0.85V
80 80
VCS2=0.90V

Output duty cycle (ch.2) [％]

Output duty cycle (ch.2) [％]

70 Driving Nch MOSFET 70

Vcc=3.3V，Ta=25℃ VCS2=0.95V
fosc=760kHz
60 60 VCS2=1.00V

VCS2=1.05V
50 50
fosc=1.5MHz
VCS2=1.10V
40 40
VCS2=1.15V
30 30
VCS2=1.20V

20 20 VCS2=1.25V

10 10 VCS2=1.30V

0 0
0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 300 500 700 900 1100 1300 1500
VCS2 [V] Oscillation frequency [kHz]

Output duty cycle vs. CS voltage (ch.2) Output duty cycle vs.
100 Oscillation frequency (ch.2)
100
Driving Pch MOSFET
90 fosc=300kHz VCS2=0.80V
Vcc=3.3V，Ta=25℃
90
80
fosc=500kHz 80
VCS2=0.85V
Output duty cycle (ch.2) [％]

Output duty cycle (ch.2) [％]

70 70 VCS2=0.90V

Driving Pch MOSFET

60 60 VCS2=0.95V
Vcc=3.3V，Ta=25℃
fosc=760kHz
VCS2=1.00V
50 50
VCS2=1.05V
40 40 VCS2=1.10V
fosc=1.5MHz
30 30 VCS2=1.15V

20 20 VCS2=1.20V

VCS2=1.25V
10 10
VCS2=1.30V
0 0
0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 300 500 700 900 1100 1300 1500
VCS2 [V] Oscillation frequency [kHz]

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OUT1 terminal source current vs. OUT2 terminal source current vs.
H level output voltage Ta=25℃ H level output voltage Ta=25℃
0 0
-50 -50
-100 -100
Vcc=2.5V Vcc=2.5V
-150 -150
IOUT1[mA]

IOUT2[mA]
-200 -200
Vcc= 3V Vcc= 3V
-250 -250
-300 -300
Vcc= 5V
-350 Vcc= 5V
-350
-400 -400
Vcc=12V Vcc=12V
-450 -450
-500 -500
0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT1[V] Vcc-VOUT2[V]

OUT1 terminal source current vs. OUT2 terminal source current vs.
H level output voltage Vcc=3.3V H level output voltage Vcc=3.3V
0 0

-50 -50

-100 -100
IOUT2[mA]
IOUT1[mA]

Ta=85℃ Ta=85℃
-150 -150

Ta=25℃
-200 Ta=-30℃ -200
Ta=25℃
Ta=-30℃
-250 -250

-300 -300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc-VOUT1[V] Vcc-VOUT2[V]

OUT1 terminal source currentvs. OUT2 terminal source current vs.

H level output voltage Vcc=12V H level output voltage Vcc=12V
0 0

-100 -100
IOUT1[mA]

IOUT2[mA]

-200 -200

-300 Ta=85℃ -300

Ta=85℃

Ta=-30℃ Ta=-30℃
-400 -400
Ta=25℃ Ta=25℃

-500 -500
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT1[V] Vcc-VOUT2[V]

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OUT1 terminal sink current vs. L level voltage OUT2 terminal sink current vs. L level voltage

200 200

Ta=25℃ Ta=25℃
Ta=-30℃ Ta=-30℃
150 150

IOUT2[mA]
IOUT1[mA]

Ta=85℃
Ta=85℃
100 100

50 50

0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VOUT2[V]
VOUT1[V]

OUT1 terminal Rise time vs. Supply voltage Vcc OUT2 terminal Rise time vs. Supply voltage Vcc
CL=1000pF CL=1000pF
60 60
OUT1 terminal Rise time t RISE[ns]

OUT2 terminal Rise time t RISE[ns]

50 50
Ta=85℃ Ta=85℃
40 Ta=25℃ 40
Ta=25℃

30 30

Ta=-30℃
20 20
Ta=-30℃
10 10

0 0
0 5 10 15 20 0 5 10 15 20
Vcc[V] Vcc[V]

OUT1 terminal Fall time vs. Supply voltage Vcc OUT2 terminal Fall time vs. Supply voltage Vcc
CL=1000pF
CL=1000pF
200 200
FALL [ns]
FALL [ns]

Ta=85℃ Ta=85℃
150 150 Ta=25℃
Ta=25℃
OUT2 terminal Fall time t
OUT1 terminal Fall time t

100 100
Ta=-30℃ Ta=-30℃

50 50

0 0
0 5 10 15 20 0 5 10 15 20
Vcc[V] Vcc[V]

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Operating mode supply current vs. UVLO ON threshold vs. ambient temperature
Oscillation frequency Ta=25℃
6.0 2.5

2.4
Operating mode supply current I CCA[mA]

UVLO ON threshold VUVLO[V]

Vcc=18V
5.0 Vcc=12V
2.3

2.2
4.0 Vcc=5V
2.1

2.0
3.0
Vcc=3.3V
Vcc=2.5V 1.9

2.0 1.8
300 500 700 900 1100 1300 1500 -50 -25 0 25 50 75 100 125 150
Oscillation frequency [kHz] Ambient temperature Ta[℃]

CS1 internal discharge switch current vs. voltage CS2 internal discharge switch current vs. voltage
Vcc=3.3V,RT=12kΩ(fosc=500kHz) Vcc=3.3V,RT=12kΩ(fosc=500kHz)
400 0
Ta=-30℃
350

300 -50
Ta=25℃
250
ICS1off[uA]

ICS2off[uA]

200 Ta=85℃ -100

Ta=85℃
150

100 -150
Ta=25℃
50 Ta=-30℃

0 -200
0.00 0.50 1.00 1.50 2.00 2.50 0.00 0.50 1.00 1.50 2.00
VCS1[V] V REG-VCS2[V]

Error Amplifier Gain and Phase vs. frequency

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8. Description of each circuit

(1) Reference voltage circuit (VREF)

This circuit generates the reference voltage of 1.00V±1% compensated in temperature from VCC voltage, and is
connected to the non-inverting input of the error amplifier. The voltage cannot be observed directly because there is no
external pin for this purpose.

(2) Regulated Voltage circuit (VREG)

This circuit generates 2.20V±1% based on the reference voltage VREF, and is used as the power supply of the internal
IC circuits. The voltage is generated when the supply voltage, VCC, is input. The VREG voltage is also used as a
regulated power supply for Soft Start, Maximum Duty cycle limitation, and others. The output current for external circuit
should be within 1mA. A capacitor connected between VREG pin and GND pin is necessary to stabilize the VREG
voltage (To determine capacitance, refer to Recommended operating conditions). The VREG voltage is regulated in
VCC voltage of 2.4V or above.

(3) Oscillator
The oscillator generates a triangular waveform by charging and
discharging the built-in capacitor. A desired oscillation frequency can be set OSC
by the value of the resistor connected to the RT pin (Fig. 1). The built-in
capacitor voltage oscillates between approximately 0.82V and 1.38V at 12
fosc=500kHz(that of ch1 and ch2 are slightly different) with almost the RT
same charging and discharging gradients (Fig. 2). You can set the desired
oscillation frequency by changing the gradients using the resistor RT Fig.1
connected to the RT pin. (Large RT: low frequency, Small RT: high
frequency) The oscillator waveform cannot be RT value: small RT value: large
1.38V
observed from the outside because a pin for this
purpose is not provided. The RT pin voltage is
approximately 1V DC in normal operation. The 0.82V
oscillator output is connected to the PWM Fig.2
comparator.

(4) Error Amplifier Circuit

The error amplifier 1 has the inverting input of IN1(-) pin (Pin14). Vout1 RNF1
The non-Inverting input is internally connected to the reference
voltage VREF (1.00V±1%; 25℃). The error amplifier 2 has the R1 Er.Amp.1
inverting input IN2(-) pin (Pin4) and non-inverting input IN2(+)
14 FB1
pin (Pin5) externally. Since each input of error amplifier 2 is IN1- 15

connected to the pins, CH2 is suitable for any circuit topology. R2

+

The FB pins (Pin3, Pin15) are the output of the error amplifier. VREF
Comp
(1.0V)
An external RC network is connected between FB pin and IN- Vout2
VREG
13
pin for gain and phase compensation setting. (Fig. 3) For
R3 R5 Comp
connecting of each topology, see Design Advice. Er.Amp.2
IN2+
5 FB2
IN2- 3
4

R4 R6

RNF2
Fig.3

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(5) PWM comparator
The PWM output generates from the oscillator
output, the error amplifier output (FB1, FB2)
PWM PWM output1
and CS voltage (CS1, CS2) (Fig. 4). The
FB1 Comp.1
oscillator output is compared with the preferred OUT1
N/P ch.
9
lower voltage between FB1 and CS1 for ch1. drive

While the preferred voltage is lower than CS1 16

oscillator output, the PWM output is low. While Oscillato SEL1

r
the preferred voltage is higher than oscillator UVLO
output
output, the PWM output is high. Since the
phase of Ch2 is the opposite phase of Ch1, CS2 PWM output2
higher voltage between FB2 and CS2 is N/P ch.
OUT2
8
preferred and while the preferred voltage is FB2 drive
lower than the oscillator output, the PWM PWM
2
Comp.2
output 2 is high. (Cannot be observed SEL2
Fig.4
externally) The output polarity of OUT1, OUT2
changes according to the condition of SEL pin. (See Fig. 6)

(6) Soft start function

This IC has a soft start function to protect DC-to-DC converter circuits from damage when starting operation. CS1 pin
(Pin10), and CS2 pin (Pin7) are used for soft start function of ch1 and ch2 respectively. (Fig. 5) When the supply
voltage is applied to the VCC pin and UVLO is cancelled,
capacitor CCS1 and CCS2 is charged by VREG through the R7 VREG VREG
13 13
resistor R7 or R9. Therefore, CS1 voltage gradually CCS2
increases and CS2 voltage gradually decreases. Since CS1 10 7

and CS2 pin are connected to the PWM comparator C CS1 CS1 CS2

internally, the pulses gradually widen and then the soft start R9
Fig.5
function operates. (Fig. 6)
The maximum duty cycle can be set by using the CS pins. (See Design Advice about the detail)

Er.Amp.1 output
ＣＳ2 pin voltage
CS1 pin voltage Oscillator output Er.Amp.2 output
Oscillator output

PWM output 1 PWM output2

OUT2
OUT1
Pch.drive
Pch.drive
(SEL2：VREG)
(SEL1：VREG)

OUT1 OUT2
Nch.drive Nch.drive
(SEL1：GND) (SEL2：GND)

Fig.6

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(7) Timer latch short-circuit protection circuit
This IC has the timer latch short-circuit protection circuit. This circuit cuts off
the output of all channels when the output voltage of DC-to-DC converter Icp
drops due to short circuit or overload. To set delay time for timer latch Vcp 1
operation, a capacitor CCP should be connected to the CP pin (Fig. 7). When CP
one of the output voltage of the DC-to-DC converter drops due to short circuit CCP
or overload, the FB1 pin voltage increases up to around the VREG voltage for Fig.7
ch 1, or the FB2 pin voltage drops down to
around 0 V for ch 2.When FB1 pin voltage momentary short
circuit short circuit
exceeds 2.0V(max.) or FB2 pin voltage
VREG pin voltag
2.1V(max)
falls below 0.2V(min.), constant-current
2.0

CP pin voltage [V]

source (2 μ A typ.) starts charging the Start-up
capacitor CCP connected to the CP pin. If short circuit
the voltage of the CP pin exceeds 2.1 V 1.0 protection
(max.), the circuit regards the case as
abnormal. Then the IC is set to off latch tp

mode and the output of all channels is shut

Time t
off, (Fig. 8) and the current consumption
Fig.8
become 2mA(typ.) The period (tp) between
the occurrence of short-circuit in the converter output and setting to off latch mode can be calculated by the following
equation:

VTHCPTL
tp[ s ] = CCP *
ICP
VTHCPTL: CP pin latched mode threshold voltage [V]
ICP: CP charge source current [μA]
CCP: capacitance of CP pin capacitor

You can reset off latched mode of the short-circuit protection by either of the following ways about 1) CP pin, or 2) VCC
pin, or 3) CS1or CS2 pin:
1) CP voltage = 0V
2) VCC voltage UVLO voltage (2.2V, typ.) or below
3) Set the CS pin of the cause of OFF latched mode as follows
CS1 pin voltage = 0V, CS2 pin voltage = VREG

If the timer-latched mode is not necessary, connect the CP pin to GND.

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(8) Output circuit
The IC contains a push-pull output stage and can directly drive MOSFETs. The maximum peak current of the output
stage is sink current of +150mA, and source current of - 400mA. The IC can also drive NPN and PNP transistors. The
maximum current in such cases is ± 50mA. You must design the output current considering the rating of power
dissipation. (See Design Advice)
You can switch the types of external discrete MOSFETs by wiring of the SEL pins (Pin 2, Pin 16). For driving Nch MOS,
connect the SEL pins to GND. For driving Pch MOS, connect the SEL pins to VREG. You can design buck converter
or inverting converter by driving Pch MOS, and boost converter by driving Nch MOS.
Connect them either to GND or to VREG surely.

(9) Under voltage lockout circuit

The IC contains a under voltage lockout circuit to protect the circuit from the damage caused by malfunctions when the
supply voltage drops. When the supply voltage rises from 0V, the IC starts to operate at VCC of 2.2V(typ.) and outputs
generate pulses. If a drop of the supply voltage occurs, it stops output at VCC of 2.1V(typ.). When it occurs, the CS1 pin
is turned to low level and the CS2 pin to high level, and then these pins are reset.

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9. Design Advice
(1) Setting the oscillation frequency
As described at Section 8-(1), “Description of Each Circuit,” a desired oscillation frequency can be determined by the
value of the resistor connected to the RT pin. When designing an oscillation frequency, you can set any frequency
between 300kHz and 1.5MHz. You can obtain the oscillation frequency from the characteristic curve “Oscillation
frequency (fosc) vs. timing resistor resistance (RT)” or the value can be approximately calculated by the following
expression.

fosc = 4050 * RT −0.86

fosc: oscillation frequency [kHz]
1.16
 4050  RT: timing resistor [kΩ]
RT =  
 fosc 
This expression, however, can be used for rough calculation, the obitained value is not guaranteed. The operation
frequency varies due to the conditions such as tolerance of the characteristics of the ICs, influence of noises, or external
discrete components. When determining the values, examine the effectiveness of the values in an actual circuit. The
timing resistor RT should be wired to the GND pin as shortly as possible because the RT pin is a high impedance pin and
is easy affected by noises.

(2) Operation near the maximum or the minimum output duty cycle
As described in “Output duty cycle vs. voltage”, the output duty cycle of this IC changes sharply near the minimum and
the maximum output duty cycle. Note that these phenomena are conspicuous for high frequency operation (when the
pulse width is narrow).

(3) Determining soft start period

The period from the start of charging the capacitor CCS to widening n% of output duty cycle can be roughly calculated
by the following expression: (see Fig. 5 for symbols)

 VCS1n 
t[ms] = − R7 * CCS1 * ln1 −  for CS1 pin
 VREG 

 VCS 2 n 
t[ms] = − R9 * CCS 2 * ln  for CS2 pin
 VREG 
CCS1, CCS2: Capacitance connected to CS1or CS2 pin [μF]
R7, R9: Resistance connected to CS1 or CS2 pin [kΩ]

VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in n% of output duty cycle, and vary in accordance with
operating frequency. The value can be obtained from the characteristic curve “Output duty cycle vs. CS voltage”

To reset the soft start function, the supply voltage VCC is lowered below the UVLO voltage (2.1V typ.) and then the
internal switch discharges the CS capacitor. The characteristics of the internal switch for discharge are shown in
following the characteristics curves of “Characteristics of CS1 internal discharge switch current vs. voltage” and
“Characteristics of CS2 internal discharge switch current vs. voltage”. Therefore, when determining the period of soft
start at restarting the power supply, consider the characteristics carefully.

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(4) Setting Maximum Duty Cycle
As described in the Fig. 9, you can limit maximum duty VREG
R7 VREG
cycle by connecting a resistor divider "R7, R8 or R9, 13 CCS2 13

R10" between CS1, CS2 and VREG pin. Set the R10
10 7
maximum duty cycle considering that relation between CS1 CS2
the maximum output duty cycle and the CS pin R8 CCS1 R9
voltage changes with operation frequency as
described in the characteristics curves of “Output duty Fig.9
cycle vs. Oscillation frequency” and “Output duty cycle vs. CS voltage”. When the maximum duty cycle is limited, CS
pin voltage at start-up is described in Fig. 10, and the approximate value of soft start period can be obtained by the
following expressions:

VCC VCC
Threshold voltage
Threshold voltage VREG pin voltage
R8
⋅ VREG
R7 + R8
VCS1n

VCS2n
R9
⋅ VREG
R9 + R10

ｔ0 ｔ ｔ0 ｔ
t0: Time from power-on of VCC to reaching unlock voltage of UVLO
Fig.10

 VCS1n  R7 * R8
t[ms] = − R 0 * CCS1 * ln1 −  R0 = for CS1
 VCS1  R7 + R8
The divided CS1 voltage is obtained by:

R8
VCS1 = * VREG
R7 + R8

 VCS 2 n − VCS 2  R9 * R10

t[ms] = − R 0 * CCS 2 * ln  R0 = for CS2
 VREG − VCS 2  R9 + R10
The divided CS2 voltage is obtained by:

R9
VCS 2 = * VREG
R9 + R10
CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [μF]
R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [kΩ]

VCS1n and VCS2n are the voltages of CS1 and CS2 under a certain output duty cycle and varies with operation
frequencies. The values of VCS1n and VCS2n can be obtained from the characteristics curve of “Output duty cycle vs.
CS voltage”.
The charging of CCS1 and CCS2 after UVLO is unlocked.
Therefore, the period from power-on of Vcc to widening n% of output duty cycle is the sum of t0 and t

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(5) Determining the output voltage of DC-DC converters
The ways to determine the output voltage of the DC-
DC converter of each channel is shown in Fig. 10 ch1
and the following equations.
OUT1
Vout1
9
VREG
SEL1
For ch1: R1 16
Vout1
IN1-
The positive output voltage of DC-to-DC converter 14
15 FB1
(a buck, a boost) is determined by:

+
R2
VREF
(1.0V)
R1 + R 2 buck
Vout1 = * VREF
R2
For ch2: OUT1
Vout1
The positive output voltage of DC-to-DC converter is 9
SEL1
Vout1

determined by: R1
IN1-
16

14 GND

R3 + R 4 15 FB1

Vout 2 = V 1 * boost

+
R2
R3 VREF
(1.0V)

R6 ch2
Here,V 1 = VREG *
R5 + R 6 OUT2
8
Vout2
When R5=R6, VREG
13 SEL2
VREG
2 Vout2

 R3 + R 4 
R4 R5

Vout 2 = VREG * 
IN2+
 5 FB2

 2 R3 
IN2- 3
V1 4
R3
R6
buck
The negative output voltage of DC-to-DC converter
(inverting) is determined by: OUT2
8

R3 + R 4 R4 Vout2 Vout2
Vout 2 = *V1 −
VREG
* VREG 13
2
SEL2

R3 R3 R4 R5
IN2+ GND
5 FB2
The ratio of resistances is determined by: V1
IN2-
4
3

R3
R3 VREG − V 1 boost
R6

=
R 4 Vout 2 + V 1
(Use the absolute value of the Vout2 voltage.) OUT2
8

VREG VREG
13 SEL2
When R5=R6, R3 R5
2 Vout2

IN2+
 R3 − R 4 
V1 FB2
5

Vout 2 = VREG *  
3
4

 2 R3  R4 R6
IN2-
inverting
Connect the SEL1 and SEL2 pin to GND or VREG Vout2
Fig.11
surely.

(6) Restriction of external discrete components and Recommended operating conditions

To achieve a stable operation of the IC, the value of external discrete components connected to VCC, VREG, CS, CP
pins should be within the recommended operating conditions. And the voltage and the current applied to each pin
should be also within the recommended operating conditions. If the pin voltage of OUT1, OUT2, or VREG becomes
higher than the VCC pin voltage, the current flows from the pins to the VCC pin because parasitic three diode exist
between the VCC pin and these pins. Be careful not to allow this current to flow.

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(5) Loss Calculation
Since it is difficult to measure IC loss directly, the calculation to obtain the approximate loss of the IC connected directly
to a MOSFET is described below.
When the supply voltage is VCC, the current consumption of the IC is ICCA, the total input gate charge of the driven
MOSFET is Qg and the switching frequency is fsw, the total loss Pd of the IC can be calculated by:
Pd ≒ VCC*(ICCA+Qg*fsw).
The value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of
temperature, or the tolerance of parameter. Therefore, evaluate the appropriateness of IC loss sufficiently considering
the range of values of above parameters under all conditions.

Example)
ICCA=2.5mA for VCC=3.3V in the case of a typical IC from the characteristics curve. Qg=6nC, fsw=500kHz, the IC
loss ”Pd” is as follows.
Pd≒3.3*(2.5mA+6nC*500kHz)≒18.2mW
if two MOSFETs are driven under the same condition for 2 channels, Pd is as follows:
Pd≒3.3*{2.5mA+2*(6nC*500kHz)}=28.1mW

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10.Application circuit

5V/500mA
7to18V

40kΩ
10uF
GND
10uF
GND
10kΩ

0.1uF 100kΩ 3.3V/500mA

0.1uF 100kΩ 0.01uF 22kΩ

VCC CS2 OUT2
GND CS1 OUT1
9

100Ω
10

10uF
0.47uF
FA3687V
6
11

11kΩ
6.2kΩ
IN2- IN2+
RT
12

10kΩ
IN1- VREG

1uF
13

1MΩ
FB2

0.01uF
14

10kΩ 10kΩ
SEL2
SEL1 FB1
15

10kΩ 0.01uF
CP
16

0.068uF

25