ATmega32A

Figure 11-3. MCU Start-up, RESET Extended Externally

VPOT
VCC

VRST
RESET

tTOUT
TIME-OUT

INTERNAL
RESET

11.2.2 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse
width (see “System and Reset Characteristics” on page 289) will generate a reset, even if the clock is not running.
Shorter pulses are not ensured to generate a reset. When the applied signal reaches the Reset Threshold Voltage
– VRST – on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired.

Figure 11-4. External Reset During Operation

CC

11.2.3 Brown-out Detection

ATmega32A has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by
comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be
2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to
ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT
+ VHYST/2 and VBOT- = VBOT - VHYST/2.
The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed),
and VCC decreases to a value below the trigger level (VBOT- in Figure 11-5), the Brown-out Reset is immediately
activated. When VCC increases above the trigger level (VBOT+ in Figure 11-5), the delay counter starts the MCU
after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given
in “System and Reset Characteristics” on page 289.

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 ATmega32A

Figure 11-5. Brown-out Reset During Operation

VCC VBOT+
VBOT-

RESET

TIME-OUT tTOUT

INTERNAL
RESET

11.2.4 Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of
this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to “Watchdog Timer” on page 41 for
details.

Figure 11-6. Watchdog Reset During Operation

CC

CK

11.3 Internal Voltage Reference

ATmega32A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be
used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the
internal bandgap reference.

11.3.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given
in “System and Reset Characteristics” on page 289. To save power, the reference is not always turned on. The ref-
erence is on during the following situations:
1. When the BOD is enabled (by programming the BODEN Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power con-
sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is
turned off before entering Power-down mode.

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 ATmega32A

11.4 Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at
VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer pres-
caler, the Watchdog Reset interval can be adjusted as shown in Table 11-1 on page 50. The WDR – Watchdog
Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a
Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega32A resets and executes from the Reset Vector. For
timing details on the Watchdog Reset, refer to page 47.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watch-
dog is disabled. Refer to the description of the Watchdog Timer Control Register for details.

Figure 11-7. Watchdog Timer

WATCHDOG
OSCILLATOR

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 ATmega32A

11.5 Register Description

11.5.1 MCUCSR – MCU Control and Status Register

The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
Bit 7 6 5 4 3 2 1 0
JTD ISC2 – JTRF WDRF BORF EXTRF PORF MCUCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction
AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as
early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can
be found by examining the Reset Flags.

11.5.2 WDTCR – Watchdog Timer Control Register

Bit 7 6 5 4 3 2 1 0
– – – WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bits 7:5 – Reserved Bits

These bits are reserved bits in the ATmega32A and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once
written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a
Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the
Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit has logic level one. To disable an
enabled Watchdog Timer, the following procedure must be followed:

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 ATmega32A

1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be written to WDE even
though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 11-1.

Table 11-1. Watchdog Timer Prescale Select

Number of WDT Typical Time-out Typical Time-out
WDP2 WDP1 WDP0 Oscillator Cycles at VCC = 3.0V at VCC = 5.0V
0 0 0 16K (16,384) 17.1ms 16.3ms
0 0 1 32K (32,768) 34.3ms 32.5ms
0 1 0 64K (65,536) 68.5ms 65ms
0 1 1 128K (131,072) 0.14s 0.13s
1 0 0 256K (262,144) 0.27s 0.26s
1 0 1 512K (524,288) 0.55s 0.52s
1 1 0 1,024K (1,048,576) 1.1s 1.0s
1 1 1 2,048K (2,097,152) 2.2s 2.1s

The following code example shows one assembly and one C function for turning off the WDT. The example
assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur
during execution of these functions.

Assembly Code Example

WDT_off:
; reset WDT
wdr
; Write logical one to WDTOE and WDE
in r16, WDTCR
ori r16, (1<<WDTOE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* reset WDT */
_WDR();
/* Write logical one to WDTOE and WDE */
WDTCR |= (1<<WDTOE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}

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 ATmega32A

12. Interrupts
This section describes the specifics of the interrupt handling as performed in ATmega32A. For a general explana-
tion of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 21.

12.1 Interrupt Vectors in ATmega32A

Table 12-1. Reset and Interrupt Vectors

Program
Vector No. Address(2) Source Interrupt Definition
(1)
1 $000 RESET External Pin, Power-on Reset, Brown-out Reset,
Watchdog Reset, and JTAG AVR Reset
2 $002 INT0 External Interrupt Request 0
3 $004 INT1 External Interrupt Request 1
4 $006 INT2 External Interrupt Request 2
5 $008 TIMER2 COMP Timer/Counter2 Compare Match
6 $00A TIMER2 OVF Timer/Counter2 Overflow
7 $00C TIMER1 CAPT Timer/Counter1 Capture Event
8 $00E TIMER1 COMPA Timer/Counter1 Compare Match A
9 $010 TIMER1 COMPB Timer/Counter1 Compare Match B
10 $012 TIMER1 OVF Timer/Counter1 Overflow
11 $014 TIMER0 COMP Timer/Counter0 Compare Match
12 $016 TIMER0 OVF Timer/Counter0 Overflow
13 $018 SPI, STC Serial Transfer Complete
14 $01A USART, RXC USART, Rx Complete
15 $01C USART, UDRE USART Data Register Empty
16 $01E USART, TXC USART, Tx Complete
17 $020 ADC ADC Conversion Complete
18 $022 EE_RDY EEPROM Ready
19 $024 ANA_COMP Analog Comparator
20 $026 TWI Two-wire Serial Interface
21 $028 SPM_RDY Store Program Memory Ready
Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot
Loader Support – Read-While-Write Self-Programming” on page 243.
2. When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of the Boot Flash section. The
address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash
section.
Table 12-2 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL
settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while
the Interrupt Vectors are in the Boot section or vice versa.

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 ATmega32A

Table 12-2. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Reset address Interrupt Vectors Start Address
1 0 $0000 $0002
1 1 $0000 Boot Reset Address + $0002
0 0 Boot Reset Address $0002
0 1 Boot Reset Address Boot Reset Address + $0002
Note: 1. The Boot Reset Address is shown in Table 26-6 on page 253. For the BOOTRST Fuse “1” means unprogrammed
while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32A is:
Address Labels Code Comments
$000 jmp RESET ; Reset Handler
$002 jmp EXT_INT0 ; IRQ0 Handler
$004 jmp EXT_INT1 ; IRQ1 Handler
$006 jmp EXT_INT2 ; IRQ2 Handler
$008 jmp TIM2_COMP ; Timer2 Compare Handler
$00A jmp TIM2_OVF ; Timer2 Overflow Handler
$00C jmp TIM1_CAPT ; Timer1 Capture Handler
$00E jmp TIM1_COMPA ; Timer1 CompareA Handler
$010 jmp TIM1_COMPB ; Timer1 CompareB Handler
$012 jmp TIM1_OVF ; Timer1 Overflow Handler
$014 jmp TIM0_COMP ; Timer0 Compare Handler
$016 jmp TIM0_OVF ; Timer0 Overflow Handler
$018 jmp SPI_STC ; SPI Transfer Complete Handler
$01A jmp USART_RXC ; USART RX Complete Handler
$01C jmp USART_UDRE ; UDR Empty Handler
$01E jmp USART_TXC ; USART TX Complete Handler
$020 jmp ADC ; ADC Conversion Complete Handler
$022 jmp EE_RDY ; EEPROM Ready Handler
$024 jmp ANA_COMP ; Analog Comparator Handler
$026 jmp TWI ; Two-wire Serial Interface Handler
$028 jmp SPM_RDY ; Store Program Memory Ready Handler
;
$02A RESET: ldi r16,high(RAMEND); Main program start
$02B out SPH,r16 ; Set Stack Pointer to top of RAM
$02C ldi r16,low(RAMEND)
$02D out SPL,r16
$02E sei ; Enable interrupts
$02F <instr> xxx
:. :. :.

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 ATmega32A

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4Kbytes and the IVSEL bit in the GICR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
Address Labels Code Comments
$000 RESET: ldi r16,high(RAMEND); Main program start
$001 out SPH,r16 ; Set Stack Pointer to top of RAM
$002 ldi r16,low(RAMEND)
$003 out SPL,r16
$004 sei ; Enable interrupts
$005 <instr> xxx
;
.org $3802
$3802 jmp EXT_INT0 ; IRQ0 Handler
$3804 jmp EXT_INT1 ; IRQ1 Handler
:. :.. : ;
$3828 jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 4Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org $002
$002 jmp EXT_INT0 ; IRQ0 Handler
$004 jmp EXT_INT1 ; IRQ1 Handler
:. :.. : ;
$028 jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org $3800
$3800 RESET: ldi r16,high(RAMEND); Main program start
$3801 out SPH,r16 ; Set Stack Pointer to top of RAM
$3802 ldi r16,low(RAMEND)
$3803 out SPL,r16
$3804 sei ; Enable interrupts
$3805 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 4Kbytes and the IVSEL bit in the GICR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
Address Labels Code Comments
.org $3800
$3800 jmp RESET ; Reset handler
$3802 jmp EXT_INT0 ; IRQ0 Handler
$3804 jmp EXT_INT1 ; IRQ1 Handler
:. :.. : ;
$3828 jmp SPM_RDY ; Store Program Memory Ready Handler
;
$382A RESET: ldi r16,high(RAMEND); Main program start
$382B out SPH,r16 ; Set Stack Pointer to top of RAM
$382C ldi r16,low(RAMEND)
$382D out SPL,r16

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 ATmega32A

$382E sei ; Enable interrupts

$382F <instr> xxx

12.1.1 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

12.2 Register Description

12.2.1 GICR – General Interrupt Control Register

Bit 7 6 5 4 3 2 1 0
INT1 INT0 INT2 – – – IVSEL IVCE GICR
Read/Write R/W R/W R/W R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this
bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the Flash. The actual
address of the start of the Boot Flash section is determined by the BOOTSZ fuses. Refer to “Boot Loader Support
– Read-While-Write Self-Programming” on page 243 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE
is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, inter-
rupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are dis-
abled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot
Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to “Boot
Loader Support – Read-While-Write Self-Programming” on page 243 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four
cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the
IVSEL description above. See Code Example below.

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 ATmega32A

Assembly Code Example

Move_interrupts:
; Enable change of interrupt vectors
ldi r16, (1<<IVCE)
out GICR, r16
; Move interrupts to boot Flash section
ldi r16, (1<<IVSEL)
out GICR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of interrupt vectors */
GICR = (1<<IVCE);
/* Move interrupts to boot Flash section */
GICR = (1<<IVSEL);
}

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 ATmega32A

13. I/O Ports

13.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/dis-
abling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with
both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection
diodes to both VCC and Ground as indicated in Figure 13-1. Refer to “Electrical Characteristics” on page 286 for a
complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

R pu

Pxn Logic

C pin
See
"General Digital I/O" for
Details

All registers and bit references in this section are written in general form. A lower case “x” represents the number-
ing letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used, that is, PORTB3 for bit no. 3 in Port B, here documented gen-
erally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 70.
Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the
Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR
disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 57. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function inter-
feres with the port pin is described in “Alternate Port Functions” on page 61. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.

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 ATmega32A

13.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of
one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O(1)

PUD

Q D
DDxn

Q CLR

WDx
RESET

RDx

DATA BUS
Pxn Q D
PORTxn

Q CLR

WPx
RESET

SLEEP RRx

SYNCHRONIZER
RPx
D Q D Q
PINxn

L Q Q

clk I/O

WDx: WRITE DDRx

PUD: PULLUP DISABLE RDx: READ DDRx
SLEEP: SLEEP CONTROL WPx: WRITE PORTx
clkI/O: I/O CLOCK RRx: READ PORTx REGISTER
RPx: READ PORTx PIN

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common
to all ports.

13.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on
page 70, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and
the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch
the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The
port pins are tri-stated when a reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an inter-
mediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must
occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can
be set to disable all pull-ups in all ports.

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 ATmega32A

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-
state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 13-1 summarizes the control signals for the pin value.

Table 13-1. Port Pin Configurations

PUD
DDxn PORTxn (in SFIOR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)

13.2.2 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 13-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay. Figure 13-3 shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.

Figure 13-3. Synchronization when Reading an Externally Applied Pin Value

SYSTEM CLK

INSTRUCTIONS XXX XXX in r17, PINx

SYNC LATCH

PINxn

r17 0x00 0xFF

tpd, max

tpd, min

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on
the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4.
The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is one system clock period.

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 ATmega32A

Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16 0xFF

INSTRUCTIONS out PORTx, r16 nop in r17, PINx

SYNC LATCH

PINxn

r17 0x00 0xFF

tpd

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from
4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as pre-
viously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the
pins.

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 ATmega32A

Assembly Code Example(1)

:.
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in r16,PINB
:.
C Code Example(1)
unsigned char i;
:.
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
:.

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0,
1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong
high drivers.

13.2.3 Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The
signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode,
Standby mode, and Extended Standby mode to avoid high power consumption if some input signals are left float-
ing, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt Request is not
enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as
described in “Alternate Port Functions” on page 61.
If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or Any Logic Change on Pin” while the External Interrupt is not enabled, the corresponding
External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these
sleep modes produces the requested logic change.

13.2.4 Unconnected pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to

 2018 Microchip Technology Inc. Data Sheet Complete DS40002072A-page 60