micro3
micro3
micro3
Unit – 3
The power-down mode saves the register contents but freezes the oscillator, disabling all
other chip functions until the next interrupt or hardware reset.
In power-save mode, the asynchronous timer continues to run, allowing the user to maintain
a timer base while the rest of the device is sleeping.
The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions.
In standby mode, the crystal/resonator oscillator is running while the rest of the device is
sleeping. This allows very fast start-up
combined with low power consumption.
ATMEGA 328P – AVR Architecture
The main function of the CPU core is to ensure
correct program execution. The CPU must
therefore be able to access memories, perform
calculations, control peripherals, and handle
interrupts.
Figure shows the parallel instruction fetches and instruction executions enabled by the harvard
architecture and the fast-access register file concept. This is the basic pipelining concept to obtain
up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
ATMEGA 328P – Instruction Execution Timing
Figure shows the internal timing concept for the register file. In a single clock cycle an ALU operation
using two register operands is executed, and the result is stored back to the destination register.
The AVR® architecture has two main memory
AVR Memories spaces, the data memory and the program memory
space.
The five different addressing modes for the data memory cover: Direct, indirect with displacement,
indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26
to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The indirect with displacement mode reaches 63
address locations from the base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the
address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2048
bytes of internal data SRAM in the ATmega328P are all accessible through all these addressing modes.
Data Memory Access Times
Data Memory Access Times
EEPROM Data Memory
The Atmel® ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Preventing EEPROM Corruption
Data Memory Access Times
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation: Keep
the AVR RESET active (low) during periods of insufficient power supply voltage. This can be
done by enabling the internal brown-out detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low VCC reset protection circuit can
be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
Data Memory Access Times
I/O Memory
All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers
and the I/O space.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these
addresses.
The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
I/O Ports - ATMEGA 328P
All AVR® ports have true read-modify-write
functionality when used as general digital I/O ports.
Each output buffer has symmetrical drive characteristics I/O Pin Equivalent Schematic
with both high sink and source capability.
The physical I/O registers and bit locations. Three I/O memory address locations are allocated
for each port, one each for the data register – PORTx, data direction register – DDRx, and the
port input pins – PINx.
The port input pins I/O location is read only, while the data register and the data direction
register are read/write. However, writing a logic one to a bit in the PINx register, will result in a
toggle in the corresponding bit in the data register.
In addition, the pull-up disable – PUD bit in MCUCR disables the pull-up function for all pins
in all ports when set. Most port pins are multiplexed with alternate functions for the peripheral
features on the device. Note that enabling the alternate function of some of the port pins does
not affect the use of the other pins in the port as general digital I/O.
Ports – General Digital I/O- ATMEGA 328P
The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin.
If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one
when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up
resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin.
The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If
PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high
(one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is
driven low (zero).
Configuring Pin - ATMEGA 328P
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not
notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit
in the MCUCR register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must
use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} =
0b11) as an intermediate step.
Port Pin Configurations - ATMEGA 328P
The signal value is latched when the system clock goes low. It is clocked into the PINxn register
at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case,
the delay tpd through the synchronizer is 1 system clock period.
Synchronization when Reading a Software
Assigned Pin Value
Digital Input Enable and Sleep Modes
The digital input signal can be clamped to ground at the input of the Schmitt trigger.
The signal denoted SLEEP in the figure, is set by the MCU sleep controller in power-down
mode, power-save mode, and standby mode to avoid high power consumption if some input
signals are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“interrupt on rising edge, falling edge, or any logic change on pin” while the external interrupt
is not enabled, the corresponding external interrupt flag will be set when resuming from the
above mentioned sleep mode, as the clamping in these sleep mode produces the requested
logic change.
Unconnected Pins - ATMEGA 328P
If some pins are unused, it is recommended to ensure that these pins have a defined level.
Even though most of the digital inputs are disabled in the deep sleep modes as described above,
floating inputs should be avoided to reduce current consumption in all other modes where the
digital inputs are enabled (reset, active mode and idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset.
Connecting unused pins directly to VCC or GND is not recommended, since this may cause
excessive currents if the pin is accidentally configured as an output.
Alternate Port
Functions
Alternate Functions of Port B
Alternate Functions of Port C
Alternate Functions of Port D
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
DHT11 is a single wire digital humidity and temperature sensor, which
provides humidity and temperature values serially.
It can measure the relative humidity in percentage (20 to 90% RH) and
temperature in degree Celsius in the range of 0 to 50°C.
It has 4 pins of which 2 pins are used for supply, 1 is not used and the last one
is used for data.
The data is the only pin used for communication. Pulses of different TON and
TOFF are decoded as logic 1 or logic 0 or start pulse or end of the frame.
For more information about the DHT11 sensor and how to use it, refer to the
topic DHT11 sensor in the sensors and modules topic.
Interfacing With DHT 11- ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
DHT11 Code for ATmega16/32
•Send the start pulse to the DHT11 sensor, making low to high.
•After receiving the response, receive 40-bit data serially from the
DHT11 sensor.