micro3

Download as pdf or txt
Download as pdf or txt
You are on page 1of 85

ATMEGA 328P

Unit – 3

- Dr. R.Prasanna AP/ECE - SRMIST


ATMEGA 32 – PIN
Diagram
ATMEGA 32 –
Architecture
ATMEGA 32 – CPU
and Registers
ATMEGA 32 –Steps To Execution
•Program Counter fetches program instruction from memory
• The PC stores a program memory address that contains the location of the next instruction.
• The PC is initialized to 0x0 on reset/power up.
• When we placed the bootloader on the chip, we set a fuse that enables a reset vector to load the PC
with the address where the bootloader program starts.
• When the program begins, the PC must contain the address of the first instruction in the program.
• Program instructions are stored in consecutive program memory locations.
• The PC is automatically incremented after each instruction.
• Note: There are jump instructions that can modify the PC (e.g., the PC must change when calling or
returning from some other routine).

•Places instruction in Instruction Register.

•Instruction Decoder determines what the instruction is.

•Arithmetic Logic Unit executes the instruction.


ATMEGA 328P – Status Register (SREG)
ATMEGA 32 – Status Register (SREG)
• Is 8 bits wide.
• Contains information associated with the results of the most recent ALU operation.
• Carry flag (C) set if CY from most signficant bit (MSB).
• Often used when adding numbers that are larger than 8 bits. Here we need to use an add with carry
instruction (ADC) to add the next most significant byte.
• Zero flag (Z) set if result is zero.
• BREQ instruction says branch if zero flag is set.
• BRNE instruction says branch if zero flag is not set.
• Negative flag (N) set if MSB is one.
• Arithmetic instructions change the flags
• Data transfer instructions do not change the flag.
• The instruction set documentation identifies which flags each instruction may modify.
• Overflow flag (V) set if 2's complement overflow occurs.
• An overflow occurs if you get the wrong sign for your result, e.g., 6410 + 6410 = -12810 (010000002 +
010000002 = 100000002).
• Note: whenever the carry into the MSB and the carry out don't match, we have an overflow.
• Sign bit (S) s = N EXOR V.
• Half carry flag (H) is set when carry occurs from b3 to b4.
• Used with binary coded decimal (BCD) arithemtic.
ATMEGA 32 – Memory
ATMEGA 32 – Memory
•The address bus is 16 bits wide.
•The data bus is 8 bits wide.
•Program memory is stored on Flash from 0x0000 to 0x3FFF (F_END).
• Our boot loader is loaded in the last 1KiB of the Flash memory.
•SRAM is used for:
• 32 General Purpose registers from 0x00 to 0x1F.
• 64 I/O ports from 0x20 to 0x5F.
• User data from 0x60 to 0x85F (RAMEND).
• Note: the bootloader uses the last 32 bytes of data memory, we will
consider RAMEND-0x20 as the end of data RAM.
•ROM for user data is stored on EEPROM.
• ATmega32 has 1KiB of storage from 0x000 to 0x3FF (E_END).
ATMEGA 328P – Features
ATMEGA 328P – Features
ATMEGA 328P – PIN Diagram
ATMEGA 328P – Block Diagram
The Atmel® ATmega328P is a low-power CMOS 8-bit
microcontroller based on the AVR® enhanced RISC
architecture.

By executing powerful instructions in a single clock


cycle, the ATmega328P achieves throughputs
approaching 1MIPS per MHz allowing the system
designer to optimize power consumption versus
processing speed.

The AVR® core combines a rich instruction set with 32


general purpose working registers. All the 32 registers are
directly connected to the arithmetic logic unit (ALU),
allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The
resulting architecture is more code efficient while
achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
ATMEGA 328P – Block Diagram
The Atmel® ATmega328P provides the following features:
32K bytes of in-system programmable flash with read-while-write capabilities, 1K bytes
EEPROM,
2K bytes SRAM,
23 general purpose I/O lines,
32 general purpose working registers,
three flexible Timer/Counters with compare modes,
Internal and external interrupts,
Serial programmable USART,
Byteoriented 2-wire serial interface,
SPI serial port,
6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages),
programmable watchdog timer with internal oscillator,
five software selectable power saving modes.
ATMEGA 328P – Operating Modes
The idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire
serial interface, SPI port, and interrupt system to continue functioning.

The power-down mode saves the register contents but freezes the oscillator, disabling all
other chip functions until the next interrupt or hardware reset.

In power-save mode, the asynchronous timer continues to run, allowing the user to maintain
a timer base while the rest of the device is sleeping.

The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions.

In standby mode, the crystal/resonator oscillator is running while the rest of the device is
sleeping. This allows very fast start-up
combined with low power consumption.
ATMEGA 328P – AVR Architecture
The main function of the CPU core is to ensure
correct program execution. The CPU must
therefore be able to access memories, perform
calculations, control peripherals, and handle
interrupts.

In order to maximize performance and


parallelism, the AVR uses a harvard
architecture – with separate memories and buses
for program and data. Instructions in the
program memory are executed with a single
level pipelining. While one instruction is being
executed, the next instruction is pre-fetched
from the program memory. This concept
enables instructions to be executed in every
clock cycle.
ATMEGA 328P – Status Register

In order to achieve the required


performance and flexibility, the
following input/output schemes are
supported by the register file:

● One 8-bit output operand and one 8-bit


result input

● Two 8-bit output operands and one


8-bit result input

● Two 8-bit output operands and one


16-bit result input

● One 16-bit output operand and one


16-bit result input
X,Y,Z Register & Stack Pointer
ATMEGA 328P – Instruction Execution Timing

Figure shows the parallel instruction fetches and instruction executions enabled by the harvard
architecture and the fast-access register file concept. This is the basic pipelining concept to obtain
up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
ATMEGA 328P – Instruction Execution Timing

Figure shows the internal timing concept for the register file. In a single clock cycle an ALU operation
using two register operands is executed, and the result is stored back to the destination register.
The AVR® architecture has two main memory
AVR Memories spaces, the data memory and the program memory
space.

In addition, the ATmega328P features an EEPROM


memory for data storage. All three memory spaces
are linear and regular.

The ATmega328P contains 32Kbytes on-chip


in-system reprogrammable flash memory for
program storage.

Since all AVR instructions are 16 or 32 bits wide,


the flash is organized as 16K x 16. For software
security, the flash program memory space is divided
into two sections, boot loader section and
application program section in ATmega328P
AVR Memories

The ATmega328P is a complex microcontroller with


more peripheral units than can be supported within the 64
locations reserved in the opcode for the IN and OUT
instructions.

For the extended I/O space from 0x60 - 0xFF in SRAM,


only the ST/STS/STD and LD/LDS/LDD instructions can
be used.
AVR Memories
The lower 2303 data memory locations address both the register file, the I/O memory, extended I/O
memory, and the internal data SRAM. The first 32 locations address the register file, the next 64 location
the standard I/O memory, then 160 locations of extended I/O memory, and the next 2048 locations
address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, indirect with displacement,
indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26
to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The indirect with displacement mode reaches 63
address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the
address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2048
bytes of internal data SRAM in the ATmega328P are all accessible through all these addressing modes.
Data Memory Access Times
Data Memory Access Times
EEPROM Data Memory
The Atmel® ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles.

EEPROM Read/Write Access


The EEPROM access registers are accessible in the I/O space. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions that
write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely
to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a
voltage lower than specified as minimum for the clock frequency used.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Preventing EEPROM Corruption
Data Memory Access Times
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep
the AVR RESET active (low) during periods of insufficient power supply voltage. This can be
done by enabling the internal brown-out detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low VCC reset protection circuit can
be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
Data Memory Access Times
I/O Memory
All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers
and the I/O space.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.

When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these
addresses.

The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
Instruction set - ATMEGA 328P
I/O Ports - ATMEGA 328P
All AVR® ports have true read-modify-write
functionality when used as general digital I/O ports.

This means that the direction of one port pin can be


changed without unintentionally changing the direction
of any other pin with the SBI and CBI instructions.

The same applies when changing drive value (if


configured as output) or enabling/disabling of pull-up
resistors (if configured as input).

Each output buffer has symmetrical drive characteristics I/O Pin Equivalent Schematic
with both high sink and source capability.

The pin driver is strong enough to drive LED displays


directly. All port pins have individually selectable
pull-up resistors with a supply-voltage invariant
resistance.
I/O Ports - ATMEGA 328P
A lower case “x” represents the numbering letter for the port, and a lower case “n” represents
the bit number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in port B, here documented generally as
PORTxn.

The physical I/O registers and bit locations. Three I/O memory address locations are allocated
for each port, one each for the data register – PORTx, data direction register – DDRx, and the
port input pins – PINx.

The port input pins I/O location is read only, while the data register and the data direction
register are read/write. However, writing a logic one to a bit in the PINx register, will result in a
toggle in the corresponding bit in the data register.

In addition, the pull-up disable – PUD bit in MCUCR disables the pull-up function for all pins
in all ports when set. Most port pins are multiplexed with alternate functions for the peripheral
features on the device. Note that enabling the alternate function of some of the port pins does
not affect the use of the other pins in the port as general digital I/O.
Ports – General Digital I/O- ATMEGA 328P

The ports are bi-directional I/O ports


with optional internal pull-ups.

Figure 13-2 shows a functional


description of one I/O-port pin, here
generically called Pxn.

WRx, WPx, WDx, RRx, RPx, and RDx are


common to all pins within the same port.
clkI/O, SLEEP, and PUD are common to all
ports.
Configuring Pin - ATMEGA 328P
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. the DDxn bits are
accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn
bits at the PINx I/O address.

The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin.

If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one
when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up
resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin.

The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If
PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high
(one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is
driven low (zero).
Configuring Pin - ATMEGA 328P
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output


When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} =
0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low
({DDxn, PORTxn} = 0b10) must occur.

Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not
notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit
in the MCUCR register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must
use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} =
0b11) as an intermediate step.
Port Pin Configurations - ATMEGA 328P

Reading the Pin Value


Independent of the setting of data direction bit DDxn, the port pin can be read through the PINxn
register bit. This is needed to avoid metastability if the physical pin changes value near the edge of
the internal clock, but it also introduces a delay. The maximum and minimum propagation delays
are denoted tpd,max and tpd,min respectively.
Synchronization when Reading an
Externally Applied Pin Value
Synchronization when Reading an
Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal.

The signal value is latched when the system clock goes low. It is clocked into the PINxn register
at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.

The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case,
the delay tpd through the synchronizer is 1 system clock period.
Synchronization when Reading a Software
Assigned Pin Value
Digital Input Enable and Sleep Modes
The digital input signal can be clamped to ground at the input of the Schmitt trigger.

The signal denoted SLEEP in the figure, is set by the MCU sleep controller in power-down
mode, power-save mode, and standby mode to avoid high power consumption if some input
signals are left floating, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“interrupt on rising edge, falling edge, or any logic change on pin” while the external interrupt
is not enabled, the corresponding external interrupt flag will be set when resuming from the
above mentioned sleep mode, as the clamping in these sleep mode produces the requested
logic change.
Unconnected Pins - ATMEGA 328P
If some pins are unused, it is recommended to ensure that these pins have a defined level.

Even though most of the digital inputs are disabled in the deep sleep modes as described above,
floating inputs should be avoided to reduce current consumption in all other modes where the
digital inputs are enabled (reset, active mode and idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset.

If low power consumption during reset is important, it is recommended to use an external


pull-up or pull-down.

Connecting unused pins directly to VCC or GND is not recommended, since this may cause
excessive currents if the pin is accidentally configured as an output.
Alternate Port
Functions
Alternate Functions of Port B
Alternate Functions of Port C
Alternate Functions of Port D
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With LCD - ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
DHT11 is a single wire digital humidity and temperature sensor, which
provides humidity and temperature values serially.

It can measure the relative humidity in percentage (20 to 90% RH) and
temperature in degree Celsius in the range of 0 to 50°C.

It has 4 pins of which 2 pins are used for supply, 1 is not used and the last one
is used for data.

The data is the only pin used for communication. Pulses of different TON and
TOFF are decoded as logic 1 or logic 0 or start pulse or end of the frame.

For more information about the DHT11 sensor and how to use it, refer to the
topic DHT11 sensor in the sensors and modules topic.
Interfacing With DHT 11- ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
Interfacing With DHT 11- ATMEGA 328P
DHT11 Code for ATmega16/32

•First, initialize the LCD16x2_4bit library.

•Define pin no. to interface DHT11 sensor, in our program we define


PD6 (Pin no. 20).

•Send the start pulse to the DHT11 sensor, making low to high.

•Receive the response pulse from the DHT11 sensor.

•After receiving the response, receive 40-bit data serially from the
DHT11 sensor.

•Display this received data on LCD16x2 along with error indication.


Interfacing With HC-05 Bluetooth Module –
ATMEGA 328P
Interfacing With HC-05 Bluetooth Module –
ATMEGA 328P
Interfacing With HC-05 Bluetooth Module –
ATMEGA 328P
Interfacing With HC-05 Bluetooth Module –
ATMEGA 328P
Interfacing With HC-05 Bluetooth Module –
ATMEGA 328P c
Interfacing With GSM Module (SIM900A) –
ATMEGA 328P
Interfacing With GSM Module (SIM900A) –
ATMEGA 328P
Interfacing With GSM Module (SIM900A) –
ATMEGA 328P
Interfacing using Zigbee to Interface
Wireless Sensors -ATMEGA 328P
Interfacing using Zigbee to Interface
Wireless Sensors -ATMEGA 328P
Interfacing using Zigbee to Interface
Wireless Sensors -ATMEGA 328P
Interfacing using Zigbee to Interface
Wireless Sensors - ATMEGA 328P
Interfacing using I2C Protocol –
ATMEGA 328P
Interfacing using I2C Protocol –
ATMEGA 328P

You might also like