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Introduction
The MSP430 is a 16-bit microcontroller that has a number of special features not commonly
available with other microcontrollers:
Complete system on-a-chip — includes LCD control, ADC, I/O ports,ROM, RAM, basic
timer, watchdog timer, UART, etc.
Extremely low power consumption — only 4.2 nW per instruction, typical
High speed — 300 ns per instruction @ 3.3 MHz clock, in register and register addressing
mode
RISC structure — 27 core instructions
Orthogonal architecture (any instruction with any addressing mode)
Seven addressing modes for the source operand
Four addressing modes for the destination operand
Constant generator for the most often used constants (–1, 0, 1, 2, 4, 8)
Only one external crystal required — a frequency locked loop (FLL) oscillator derives all
internal clocks
Full real-time capability — stable, nominal system clock frequency is available after only six
clocks when the MSP430 is restored from low-power mode (LPM) 3; — no waiting for the
main crystal to begin oscillation and stabilize

The 27 core instructions combined with these special features make it easyto program the
MSP430 in assembler or in C, and provide exceptional flexibility and functionality.

The MSP430 MCU is designed specifically for ultra-low-power applications . Its flexible
clocking system, multiple low-power modes, instant wakeup and intelligent autonomous
peripherals enable true ultra-low-power optimization, dramatically extending battery life.

MSP430 MCUs are highly integrated and offer a wide range of high performance analog and
digital peripherals. Typical applications include embedded and sensor systems. Integrated
timers make the configurations ideal for industrial control applications such as ripple
counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier
enhances the performance and offers a broad code and hardware-compatible family solution.

Key Features:

Ultra-low-power (ULP) architecture and flexible clock system extend battery life
Low power consumption: 0.1 μ A for RAM data Retention, 0.8 μ A for RTC mode
operation,
250 μA /MIPS at active operation.
Low operation voltage (from 1.8 V to 3.6 V).
Four destination-address modes
Only 27 core instructions
Prioritized, nested interrupts
Large register file
Efficient table processing
Fast hex-to-decimal conversion.

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ARCHITECTURE
The MSP430 CPU has a 16-bit RISC architecture. The controller’s performance is directly
related to the 16-bit data bus, the 7 addressing modes and the reduced instructions set , which
allows a shorter, denser programming code for fast execution.
These MSP controller families share a 16-bit CPU core, RISC type, intelligent peripherals ,
and flexible clock system that interconnects using a Von Neumann common memory
address bus (MAB) and memory data bus (MDB) architecture.

The architecture of MSP430 Can be understood from the following diagram.

MSP430 CPU

The CPU of MSP 430 includes a 16-bit ALU and a set of 16 Registers R0 –R15.In these
registers four are special Purpose and 12 are general purpose registers. All the registers can be
addressed in the same way.

The special Purpose Registers are

PC (Program Counter), SP (Stack Pointer) , SR (Status Register) and CGx (Constant

Generator).

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MEMORY SPACE

All memory, including RAM, Flash/ROM, information memory, special function

registers (SFRs), and peripheral registers are mapped into a single, contiguous address
space

The CPU is capable of addressing data values either as bytes (8 bits) or words (16
bits). Words are always addressed at an even address, which contain the least
significant byte, followed by the next odd address, which contains the most significant
byte.

For 8-bit operations, the data can be accessed from either odd or even addresses, but for 16-
bit operations, the data values can only be accessed from even addresses.

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The interrupt vector table is mapped at the very end of memory space (upper 16 words of
Flash/ROM), in locations 0FFE0h through to 0FFFEh (see the device-specific datasheets).
The priority of the interrupt vector increases with the word address.

The start address of Flash/ROM depends on the amount of Flash/ROM present on the device.
The start address varies between01100h (60k devices) to 0F800h (2k devices) and always
runs to the end of the address space at location 0FFFFh.

Flash can be used for both code and data. Word or byte tables can also be stored andread by
the program from Flash/ROM. All code, tables, and hard-coded constants reside in this
memory Space.

The MSP430 flash devices contain an address space for information memory. It is like an
onboard EEPROM, where variables needed for the next power up can be stored during power
down. It can also be used as code memory.

The MSP430 flash devices contain an address space for boot memory, located between
addresses 0C00h through to 0FFFh. The“ bootstrap loader” is located in this memory space,
which is an External interface that can be used to program the flash memory in addition to the
JTAG. This memory region is not accessible by other applications, so it cannot be
overwritten accidentally.

RAM always starts at address 0200h. The end address of RAM depends on the amount of
RAM present on the device. RAM is used for both code and data.

Peripheral modules consist of all on-chip peripheral registers that are mapped into the address
space. These modules can be accessed with byte or word instructions, depending if the
peripheral module is 8-bit or 16-bit respectively. The 16-bit peripheral modules are located in
the address space from addresses 0100 through to 01FFh and the 8-bit peripheral modules are
mapped into memory from addresses 0010h through to 00FFh.

The Special Function Registers (SFRs) are located at memory addresses from 0000h to
000Fh. SFRs must be accessed using byte instructions only.

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Register Organisation

The CPU has a 16-bit ALU, four dedicated registers and twelve working registers, which
makes the MSP430 a high performance microcontroller suitable for low power applications.
The addition of twelve working general purpose registers saves CPU cycles by allowing the
storage of frequently used values and variables instead of using RAM.

Registers

The MSP430 CPU includes an arithmetic logic unit (ALU) that handles addition, subtraction,
comparison and logical (AND, OR, XOR) operations. ALU operations can affect the
overflow, zero, negative, and carry flags in the status register.

R0: Program Counter (PC)

• The 16-bit Program Counter (PC/R0) points to the next instruction to be read from
memory and executed by the CPU. The Program counter is implemented by the
number of bytes used by the instruction (2, 4, or 6 bytes, always even). It is important
to note that the PC is aligned at even addresses, because the instructions are 16 bits,
even though the individual memory addresses contain 8-bit values.

R1: Stack Pointer (SP)

• The Stack Pointer (SP/R1) is located in R1.

• Stack can be used by user to store data for later use(instructions: store by PUSH,
retrieve by POP)

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• Stack can be used by user or by compiler for subroutine parameters (PUSH, POP in
calling routine; addressed via offset calculation on stack pointer (SP) in called
subroutine)

• The Stack Pointer (SP/R1) is located in R1.

• Stack can be used by user to store data for later use(instructions: store by PUSH,
retrieve by POP)

• Stack can be used by user or by compiler for subroutine parameters (PUSH, POP in
calling routine; addressed via offset calculation on stack pointer (SP) in called
subroutine)

R2: Status Register (SR)

The Status Register (SR/R2) is a 16 bit register , and it stores the state and control bits. The
system flags are changed automatically by the CPU depending on the result of an operation in
a register. The reserved bits of the SR are used to support the constants generator

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MSP430 CPU block diagram

R2/R3:
Constant Generator
Registers (CG1/CG2)

• Depending of the source-register addressing modes (As) value, six commonly used
constants can be generated without a code word or code memory access to retrieve
them. This is a very powerful feature, which allows the implementation of emulated
instructions, for example, instead of implementing a core instruction for an increment,
the constant generator is used.

R4 - R15: General–Purpose Registers

• These general-purpose registers are used to store data values , address pointers, or
index values and can be accessed with byte or word instructions.

Addressing modes

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The MSP430 supports seven addressing modes for the source operand and four addressing
modes for the destination operand . They are

• Register mode

• Indexed mode

• Symbolic mode

• Absolute mode

• Indirect register mode

• Indirect auto increment mode

• Immediate mode

Immediate mode

• Immediate mode is used to assign constant values to registers or memory locations.

• MOV #E2h, R5

• Move the immediate constant E2h to the destination (register R5).

Register Mode

• Register mode operations work directly on the processor registers, R4 through R15, or
on special function registers, such as the program counter or status register. They are
very efficient in terms of both instruction speed and code space.

Ex : MOV R4, R5

Move (copy) the contents of source (register R4) to destination (register R5). Register R4
is not affected.

Indirect register mode

• The data word addressed is located in the memory location pointed to by Rn. Indirect
mode is not valid for destination operands, but can be emulated with the indexed
mode format 0( Rn). Here Rn is used as a pointer to the operand.

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• MOV @(R4), R5

• Move the contents of the source address (contents of R4) to the destination (register
R5). Register R4 is not modified

Indirect auto increment mode

• Similar to indirect register mode, but with indirect auto increment mode, the operand
is incremented as part of the instruction. The format for operands is @Rn+. This is
useful for working on blocks of data.

• Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for byte

instructions and by 2 for word instructions.

Ex: MOV @R4+, R5

Move the contents of the source address (contents of R4) to the destination (register R5),
then increment the value in register R4 to point to the next word.

Indexed mode

• The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn
is one of the CPU registers. The absolute memory location X+Rn is addressed.

• Indexed mode addressing is useful for applications such as lookup tables

Ex : MOV F000h(R5), R4

Move (copy) the contents at source address (F000h +R5) to destination (register R4)

Symbolic mode

• Symbolic mode allows the assignment of labels to fixed memory locations, so that
those locations can be addressed. This is useful for the development of embedded
programs.

• MOV XPT, YPT

• Move the content of source address XPT (x pointer) to the destination address YPT
(y pointer).

Absolute mode

Similar to Symbolic mode, with the difference that the label is preceded by “&”.

The word following the instruction contains the absolute address. X is stored in the next
word. Indexed mode X(SR) is used

MOV &XPT, &YPT

Move the content of source address XPT to the destination address YPT.

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Instruction set

• The MSP430 instruction set consists of 27 core instructions. Additionally, it supports

24 emulated instructions. The core instructions have unique op-codes decoded by the
CPU, while the emulated ones need assemblers and compilers to generate their
mnemonics.

• There are three core-instruction formats:

• Double operand

• Single operand

• Program flow control - Jump.

• The instruction set is orthogonal with few exceptions, meaning that all addressing
modes can be used with all instructions and registers.

Movement Instructions

• There is only the one ‘mov’ instruction to move data. It can address all of memory as
either source or destination, including both registers in the CPU and the whole
memory map.

• Ex : mov . w src , dst

Here . w denotes that the operations can use either bytes or words

Stack Operations

• These instructions either push data onto the stack or pop them off .

ex 1: push .w src ; push data onto stack

ex 2 : pop .w dst ; pop data off stack.

The pop operation is emulated using post-increment addressing but push requires a special
instruction because pre-decrement addressing is not available.

Arithmetic and Logic Instructions with Two Operands

• add.w src ,dst ; add

• addc.w src ,dst ; add with carry

• adc.w dst ; add carry bit

• sub.w src ,dst ; subtract

• subc.w src ,dst ; subtract with borrow

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• sbc.w dst ; subtract borrow bit

• cmp.w src ,dst ; compare , set flags only.

The compare operation cmp is the same as subtraction except that only the bits in SR are
affected ; the result is not written back to the destination.

Arithmetic Instructions with One Operand

• All these are instructions are emulated, which means that the operand is always a
destination.

• Ex: clr.w dst ; clear

• dec.w dst ; decrement

• decd.w dst ; double decrement

• inc.w dst ; increment

• incd.w dst ; double increment

• tst.w dst ; test (compare with 0)

Logic Instructions with Two Operands

• The MSP430 has the usual and and exclusive-OR xor instructions but not an explicit
inclusive-OR. The and bitwise test operations are identical except that bit is only a test
and does not change its destination.

• Ex : and.w src ,dst ; bitwise and .

• xor.w src ,dst ; bitwise exclusive or

• bit.w src ,dst ; bitwise test , set flags only

• bis.w src ,dst ; bit set

• bic.w src ,dst ; bit clear

Logic Instructions with One Operand

• There is only one instruction of this type . invert ‘inv’ instruction , also known as ones
complement ,which changes all 0 bits to 1 and 1s to 0.

• Ex : inv.w dst ; invert bits

Byte Manipulation

• These instructions do not need a suffix because the size of. the operands is fixed.

• Ex : Swpb src ; swap upper and lower bytes (word only)

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• Ex : sxt src ; extend sign of lower byte (word only)

• The swap bytes instruction ‘swpb’ swaps the two bytes in a word.

• The sign extend instruction sxt is used to convert a signed byte into a signed word.

Operations on Bits in Status Register

• There is a set of emulated instructions to set or clear the four lowest bits in the status
register and these can be masked using the constant generator.

• Ex: clrc ; clear carry bit.

• clrn ; clear negative bit.

• clrz ; clear zero bit.

• setc ; set carry bit.

• setn ; set negative bit.

• setz ; set zero bit.

• dint ; disable general interrupts.

• eint ; enable general interrupts.

Shift and Rotate Instructions

There are three types of shifts

(i) logical shift (ii) arithmetic shift (iii) rotation. They are explained below.

• Logical shift inserts zeroes for both right and left shifts.

• Arithmetic shift inserts zeroes for left shifts but the most significant bit, which carries
the sign, is replicated for right shifts.

• Rotation does not introduce or lose any bits; bits that are moved out of one end of the
register are passed around to the other.

• Ex : rla dst ; arithmetic shift left

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• rra src ; arithmetic shift right.

• rlc dst ; rotate left through carry.

• rrc src ; rotate right through carry

Flow of Control

• The most common elementary use of call is for a subroutine that begins at a particular
label.

• Ex: br src ; branch (go to).

• call src ; call subroutine.

• ret ; return from subroutine.

• reti ; return from interrupt.

• nop ; no operation (consumes single cycle)

Jumps (Unconditional and Conditional)

• jmp fits in a single word, including the offset, but its range is limited to about ±1KB
from the current location.

• jmp label ; unconditional jump.

• The conditional jumps are the “decision-making” instructions and test certain bits or
combinations in the status register.

• Ex : jc label ; jump if carry set

• jnc label ; jump if carry not set ,

• jn label ; jump if negative ,

• jz label ; jump if zero

• jnz label ; jump if nonzero.

• jge label ; jump if greater or equal ,

• jl(t) label ; jump if less than

TIMERS

• Normally we find two Timers Timer A and Timer B and one Watchdog Timer in
MSP430 microcontrollers.

• TIMER A: It typically has three channels and is much more versatile than the simpler
timers .

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• Timer A can handle external inputs and outputs directly to measure frequency, time-
stamp inputs, and drive outputs at precisely specified times, either once or
periodically. There are internal connections to other modules so that it can measure
the duration of a signal from the comparator and it can also generate interrupts

• Timer B : Is included in larger devices of all families. It is similar to Timer A with

some extensions that make it more suitable for driving outputs such as pulse-width
modulation. But , it lacks a feature of sampling inputs in Timer A that is useful in
communication.

Watchdog Timer

• The main purpose of the watchdog timer is to protect the system against failure of the
software, such as the program becoming trapped in an un-intended, infinite loop. Left
to itself, the watchdog counts up and resets the MSP430 when it reaches its limit.

• The operation of the watchdog is controlled by the 16-bit register WDTCTL. It is

guarded against accidental writes by requiring the password WDTPW = 0x5A in the
upper byte.

• A reset will occur if a value with an incorrect password is written to WDTCTL. This
can be done deliberately if you need to reset the chip from software. Reading
WDTCTL returns 0x69 in the upper byte, so reading WDTCTL and writing the value
back violates the password and causes a reset.

• The lower byte of WDTCTL contains the bits that control the operation of the
watchdog timer.

The watchdog is always active after the MSP430 has been reset. By default the clock is
SMCLK, which is in turn derived from the DCO at about 1 MHz. The default period of the
watchdog is the maximum value of 32,768 counts, which is therefore around 32 ms.

Low-Power Operation

The MSP430 MCU utilizes six different Low-Power Modes, which can disable unused
clocks and CPU. This allows the MSP430 to sleep, while its peripherals continue to work
without the need for an energy hungry processor. Additionally, the MSP430 is capable of
wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode
longer, minimizing its average current consumption.

• With the multiple low power modes, there is a notable difference in the amount of
power consumed between MSP430 and other microcontrollers.

• MSP430 uses up to 70% less power than the PIC24F16KA102 in active mode. In
standby mode, the PIC24F16KA102 consumes up to 41% and STM8L151G4
consumes up to 9 times more power than the MSP430.

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• Multiple low power modes, with flexible clocking system, instant wakeup, and
intelligent autonomous peripherals enable true ULP optimization, dramatically
extending battery life.

Flexible Clocking System

• The MSP430 MCU clock system has the ability to enable and disable various clocks
and oscillators which allow the device to enter various low-power modes (LPMs).
The flexible clocking system optimizes overall current consumption by only enabling
the required clocks when appropriate.

• Main Clock (MCLK) : CPU source that may be driven by the internal Digitally
Controlled Oscillator (DCO) up to 25 MHz or with external crystal.

• Auxiliary Clock (ACLK) : Source for individual peripheral modules driven by the
internal low-power oscillator or external crystal

• Sub-Main Clock (SMCLK) : Source for faster individual peripheral modules that may
be driven by the internal DCO up to 25 MHz or with external crystal

• Low Power Modes (LPMs) represents the ability to scale the microcontroller’s power
usage by shutting off parts of the MSP430. The CPU and several other modules such
as clocks are not always needed. Many applications which wait until a sensor detects
a certain event can benefit from turning off unused (but still running) parts of the
microcontroller to save energy, turning them back on quickly when needed.

• So , each subsequent LPM in the MSP430 turns off more and more modules or parts
of the microcontroller, the CPU, clocks etc..

Power modes

• Active Mode : Nothing is turned off (except maybe individual peripheral modules).
No power savings.

• LPM0 :CPU and MCLK are disabled while SMCLK and ACLK remain active.

• LPM1 : CPU and MCLK are disabled, and DCO and DC generator are disabled if the
DCO is not used for SMCLK. ACLK is active.

• LPM2 : CPU, MCLK, SMCLK, DCO are is enabled DC generator remains enabled.
ACLK is active

• LPM3 :CPU, MCLK, SMCLK, DCO are disabled, DC generator is disabled, ACLK is
active

• LPM4:CPU is disabled, ACLK is disabled, MCLK and SMCLK are disabled DCO’s
dc-generator is disabled Crystal oscillator is stopped

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• It is important to note that the parts of the microcontroller that are shut off, will not
operate until they are turned on again by interrupts.

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