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Module 2_ Floorplanning, Placement & Routing - Google Forms

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Module 2_ Floorplanning, Placement & Routing - Google Forms

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Sowmya Bhat ECE
8 views4 pages

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© © All Rights Reserved

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PDF, TXT or read online from Scribd

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Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
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8 views4 pages

Module 2_ Floorplanning, Placement & Routing - Google Forms

Uploaded by

Sowmya Bhat ECE

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
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1/3/25, 3:08 PM Module 2: Floorplanning, Placement & Routing

Module 2: Floorplanning, Placement &


Routing
This form contains 10 multiple-choice questions to assess your understanding of floor
planning, placement, and routing in VLSI design. Select the best answer for each
question.

* Indicates required question

1. Email *

2. Name *

3. USN *

4. What is the primary goal of floor planning in VLSI design?

Mark only one oval.

a) Minimizing power consumption

b) Defining the chip area and arranging blocks optimally

c) Maximizing the number of transistors

d) Increasing fabrication yield

https://docs.google.com/forms/d/1K0eWiY_krbJ_nVg-UV0sNb2xTbpJOOF9wF2sqmPxCNY/edit 1/5
1/3/25, 3:08 PM Module 2: Floorplanning, Placement & Routing

5. Which of the following factors is critical for measuring delay in floor planning?

Mark only one oval.

a) Wire resistance and capacitance

b) Clock skew

c) Heat dissipation

d) Transistor size

6. Floor planning tools are primarily used for:

Mark only one oval.

a) Circuit simulation

b) Logical synthesis

c) Block placement and area estimation

d) Power grid design

7. What is the purpose of I/O and power planning in floor planning?

Mark only one oval.

a) To increase the speed of the chip

b) To reduce power consumption and ensure signal integrity

c) To enhance the layout aesthetic

d) To optimize transistor-level design

8. Clock planning in VLSI design ensures:

Mark only one oval.

a) Minimized power dissipation in wires

b) Balanced clock skew and low clock latency

c) Optimized block area

d) Reduced transistor count

https://docs.google.com/forms/d/1K0eWiY_krbJ_nVg-UV0sNb2xTbpJOOF9wF2sqmPxCNY/edit 2/5
1/3/25, 3:08 PM Module 2: Floorplanning, Placement & Routing

9. The primary objective of placement in physical design is to:

Mark only one oval.

a) Optimize routing paths between components

b) Define the chip layout area

c) Reduce the number of vias

d) Maximize the number of transistors

10. Which algorithm is commonly used in placement for partitioning the


design?

Mark only one oval.

a) Breadth-first search

b) Min-cut placement algorithm

c) Dijkstra’s algorithm

d) Genetic algorithm

11. Time-driven placement methods are focused on:

Mark only one oval.

a) Reducing clock skew

b) Minimizing delay and meeting timing constraints

c) Reducing power consumption

d) Balancing the number of transistors per block

12. Global routing in VLSI design focuses on:

Mark only one oval.

a) Assigning exact wire paths

b) Assigning routing regions and minimizing congestion

c) Placing vias for connectivity

d) Determining transistor dimensions

https://docs.google.com/forms/d/1K0eWiY_krbJ_nVg-UV0sNb2xTbpJOOF9wF2sqmPxCNY/edit 3/5
1/3/25, 3:08 PM Module 2: Floorplanning, Placement & Routing

13. Which of the following methods is typically used for global routing
between blocks?

Mark only one oval.

a) Maze routing

b) Steiner tree algorithm

c) Rectilinear edge routing

d) A* search algorithm

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