Rev 3; 2/07

Real-Time Clock
General Description Features

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
The DS12885, DS12887, and DS12C887 real-time ♦ Drop-In Replacement for IBM AT Computer
clocks (RTCs) are designed to be direct replacements
Clock/Calendar
for the DS1285 and DS1287. The devices provide a
real-time clock/calendar, one time-of-day alarm, three ♦ RTC Counts Seconds, Minutes, Hours, Day, Date,
maskable interrupts with a common interrupt output, a Month, and Year with Leap Year Compensation
programmable square wave, and 114 bytes of battery-
Through 2099
backed static RAM (113 bytes in the DS12C887 and
DS12C887A). The DS12887 integrates a quartz crystal ♦ Binary or BCD Time Representation
and lithium energy source into a 24-pin encapsulated
DIP package. The DS12C887 adds a century byte at ♦ 12-Hour or 24-Hour Clock with AM and PM in
address 32h. For all devices, the date at the end of the 12-Hour Mode
month is automatically adjusted for months with fewer ♦ Daylight Saving Time Option
than 31 days, including correction for leap years. The
devices also operate in either 24-hour or ♦ Selectable Intel or Motorola Bus Timing
12-hour format with an AM/PM indicator. A precision
♦ Interfaced with Software as 128 RAM Locations
temperature-compensated circuit monitors the status of
VCC. If a primary power failure is detected, the device ♦ 14 Bytes of Clock and Control Registers
automatically switches to a backup supply. A lithium
♦ 114 Bytes of General-Purpose, Battery-Backed
coin-cell battery can be connected to the VBAT input
pin on the DS12885 to maintain time and date operation RAM (113 Bytes in the DS12C887 and
when primary power is absent. The device is accessed DS12C887A)
through a multiplexed byte-wide interface, which sup-
ports both Intel and Motorola modes. ♦ RAM Clear Function (DS12885, DS12887A, and
DS12C887A)
Applications
♦ Interrupt Output with Three Independently
Embedded Systems Maskable Interrupt Flags
Utility Meters
♦ Time-of-Day Alarm Once Per Second to Once
Security Systems Per Day
Network Hubs, Bridges, and Routers
♦ Periodic Rates from 122μs to 500ms
Typical Operating Circuit ♦ End-of-Clock Update Cycle Flag

CRYSTAL
♦ Programmable Square-Wave Output
VCC
♦ Automatic Power-Fail Detect and Switch Circuitry

X1 X2 VCC
♦ Optional 28-Pin PLCC Surface Mount Package or
AS RESET 32-Pin TQFP (DS12885)
R/W RCLR ♦ Optional Encapsulated DIP (EDIP) Package with
DS Integrated Crystal and Battery (DS12887,
DS83C520 DS12887A, DS12C887, DS12C887A)
CS DS12885
AD(0–7) SQW
♦ Optional Industrial Temperature Range Available
IRQ VBAT ♦ Underwriters Laboratory (UL) Recognized
MOT
GND

Pin Configurations and Ordering Information appear at end of data sheet.

______________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Storage Temperature Range .............................-55°C to +125°C
Operating Temperature Range ................................................... Soldering Temperature .......................................See IPC/JEDEC
Commercial (noncondensing) .............................0°C to +70°C J-STD-020 Specification (Note 1)
Operating Temperature Range ................................................... Soldering Temperature (leads, 10s) ................................+260°C
Industrial (noncondensing)...............................-40°C to +85°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(VCC = +4.5V to +5.5V, TA = over the operating range, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC (Note 3) 4.5 5.5 V
VBAT Input Voltage VBAT (Note 3) 2.5 4.0 V
VCC +
Input Logic 1 VIH (Note 3) 2.2 V
0.3
Input Logic 0 VIL (Note 3) -0.3 +0.8 V
VCC Power-Supply Current ICC1 (Note 4) 15 mA
VCC Standby Current ICCS (Note 5) mA
Input Leakage IIL -1.0 +1.0 µA
I/O Leakage IOL (Note 6) -1.0 +1.0 µA
Input Current IMOT (Note 7) -1.0 +500 µA
Output at 2.4V IOH (Note 3) -1.0 mA
Output at 0.4V IOL (Note 3) 4.0 mA
Power-Fail Voltage VPF (Note 3) 4.0 4.25 4.5 V
VRT Trip Point VRTTRIP 1.3 V

2 _____________________________________________________________________
 Real-Time Clock
DC ELECTRICAL CHARACTERISTICS

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
(VCC = 0V, VBAT = 3.0V, TA = over the operating range, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VBAT Current (OSC On);
IBAT (Note 8) 500 nA
TA = +25°C, VBACKUP = 3.0V
VBAT Current (Oscillator Off) IBATDR (Note 8) 100 nA

AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TA = over the operating range.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Cycle Time tCYC 385 DC ns
Pulse Width, DS Low or R/W High PWEL 150 ns
Pulse Width, DS High or R/W Low PWEH 125 ns
Input Rise and Fall t R , tF 30 ns
R/W Hold Time tRWH 10 ns
R/W Setup Time Before DS/E tRWS 50 ns
Chip-Select Setup Time Before
tCS 20 ns
DS or R/W
Chip-Select Hold Time tCH 0 ns
Read-Data Hold Time tDHR 10 80 ns
Write-Data Hold Time tDHW 0 ns
Address Valid Time to AS Fall tASL 30 ns
Address Hold Time to AS Fall tAHL 10 ns
Delay Time DS/E to AS Rise tASD 20 ns
Pulse Width AS High PWASH 60 ns
Delay Time, AS to DS/E Rise tASED 40 ns
Output Data Delay Time from DS
tDDR 20 120 ns
or R/W
Data Setup Time tDSW 100 ns
Reset Pulse Width tRWL 5 µs
IRQ Release from DS tIRDS 2 µs
IRQ Release from RESET tIRR 2 µs

_____________________________________________________________________ 3
 Real-Time Clock
Motorola Bus Read/Write Timing
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

PWASH
tASED
AS

tASD
tCYC

DS PWEL PWEH

tRWS tRWH

R/ W
tCH
tCS
CS

tDSW tDHW
AD0–AD7
WRITE
tASL tAHL tDHR
AD0–AD7
READ tDDR

Intel Bus Write Timing

tCYC
AS PWASH

tASD
DS

tASD tASED

R/W PWEL PWEH

tCH
tCS
CS
tASL tAHL tDSW tDHW
AD0–AD7
WRITE

4 _____________________________________________________________________
 Real-Time Clock
Intel Bus Read Timing

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
tCYC

AS PWASH

tASD
tASED
DS PWEL PWEH
tASD

R/W

tCH
tCS
CS

tASL tAHL tDDR tDHR

AD0–AD7

IRQ Release Delay Timing

DS
RESET tRWL

IRQ
tIRR
tIRDS

Power-Up/Power-Down Timing

VCC
VPF(MAX)
VPF(MIN)

tF tR

tRPU

tDR

INPUTS RECOGNIZED DON'T CARE RECOGNIZED

HIGH-Z
OUTPUTS VALID VALID

_____________________________________________________________________ 5
 Real-Time Clock
POWER-UP/POWER-DOWN CHARACTERISTICS
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

(TA = -40°C to +85°C) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Recovery at Power-Up tRPU 20 200 ms
VCC Fall Time; VPF(MAX) to
tF 300 µs
VPF(MIN)
VCC Rise Time; VPF(MIN) to
tR 0 µs
VPF(MAX)

DATA RETENTION
(TA = +25°C)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Expected Data Retention tDR 10 years

CAPACITANCE
(TA = +25°C) (Note 9)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Capacitance on All Input Pins
CIN 5 pF
Except X1 and X2
Capacitance on IRQ, SQW, and
CIO 7 pF
DQ Pins

AC TEST CONDITIONS
PARAMETER TEST CONDITIONS
Input Pulse Levels 0 to 3.0V
Output Load Including Scope and Jig 50pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels Input/Output: VIL maximum and VIH minimum
Input-Pulse Rise and Fall Times 5ns

WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.

Note 1: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: All outputs are open.
Note 5: Specified with CS = DS = R/W = RESET = VCC; MOT, AS, AD0–AD7 = 0; VBACKUP open.
Note 6: Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state.
Note 7: The MOT pin has an internal 20kΩ pulldown.
Note 8: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 9: Guaranteed by design. Not production tested.
Note 10: Measured with a 50pF capacitance load.

6 _____________________________________________________________________
 Real-Time Clock
Typical Operating Characteristics

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
(VCC = +5.0V, TA = +25°C, unless otherwise noted.)

IBAT1 vs. VBAT OSCILLATOR FREQUENCY

vs. TEMPERATURE vs. VCC

DS12885 toc01

DS12885 toc02
VCC = 0V +85°C 32768.70
300
32768.60

+25°C

FREQUENCY (Hz)
32768.50
IBAT (nA)

250
32768.40
0°C
+70°C 32768.30
200 +40°C
32768.20

-40°C 32768.10

150 32768.00
2.5 2.8 3.0 3.3 3.5 3.8 4.0 4.5 4.8 5.0 5.3 5.5
VBAT (V) VCC (V)

Functional Diagram

X1
DIVIDE DIVIDE DIVIDE
OSC BY 8 BY 64 BY 64
X2

VCC
16:1 MUX
GND
POWER SQUARE- SQW
CONTROL WAVE
GENERATOR
VBAT
IRQ IRQ
DS12885 GENERATOR
CS

R/W
REGISTERS A, B, C, D
DS

AS BUS CLOCK/CALENDAR
INTERFACE UPDATE LOGIC CLOCK/CALENDAR AND
MOT ALARM REGISTERS
RESET BUFFERED CLOCK/
AD0–AD7 CALENDAR AND ALARM
REGISTERS

USER RAM
RLCR
114 BYTES

_____________________________________________________________________ 7
 Real-Time Clock
Pin Description
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

PIN
SO, NAME FUNCTION
PDIP EDIP PLCC TQFP

Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to VCC, Motorola bus timing is selected. When connected to GND or
1 1 2 29 MOT
left disconnected, Intel bus timing is selected. The pin has an internal pulldown
resistor.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
2 — 3 30 X1
circuitry is designed for operation with a crystal having a 6pF specified load
capacitance (CL). Pin X1 is the input to the oscillator and can optionally be
3 — 4 31 X2 connected to an external 32.768kHz oscillator. The output of the internal oscillator,
pin X2, is floated if an external oscillator is connected to pin X1.

Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during

the first portion of the bus cycle and latched into the device by the falling edge of
AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising
1, 2, 3,
5–10, AD0– edge of R/W (Intel timing). In a read cycle, the device outputs data during the
4–11 4–11 5, 7, 8,
12, 14 AD7 latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for
9, 11
Intel timing). The read cycle is terminated and the bus returns to a high-
impedance state as DS transitions low in the case of Motorola timing or as DS
transitions high in the case of Intel timing.
12, 16 12 15, 20 12, 17 GND Ground
Active-Low Chip-Select Input. The chip-select signal must be asserted low for a
bus cycle in the device to be accessed. CS must be kept in the active state during
DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles
13 13 16 13 CS that take place without asserting CS will latch addresses, but no access occurs.
When VCC is below VPF volts, the device inhibits access by internally disabling the
CS input. This action protects the RTC data and the RAM data during power
outages.
Address Strobe Input. A positive-going address-strobe pulse serves to
demultiplex the bus. The falling edge of AS causes the address to be latched
within the device. The next rising edge that occurs on the AS bus clears the
14 14 17 14 AS address regardless of whether CS is asserted. An address strobe must
immediately precede each write or read access. If a write or read is performed
with CS deasserted, another address strobe must be performed prior to a read or
write access with CS asserted.
Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to VCC for Motorola timing, R/W is at a level that indicates whether the
current cycle is a read or write. A read cycle is indicated with a high level on R/W
15 15 19 16 R/W while DS is high. A write cycle is indicated when R/W is low during DS. When the
MOT pin is connected to GND for Intel timing, the R/W signal is an active-low
signal. In this mode, the R/W pin operates in a similar fashion as the write-enable
signal (WE) on generic RAMs. Data are latched on the rising edge of the signal.

8 _____________________________________________________________________
 Real-Time Clock
Pin Description (continued)

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
PIN
SO, NAME FUNCTION
PDIP EDIP PLCC TQFP

4, 6, 10,
2, 3, 1, 11,
15, 20, No Connection. This pin should remain unconnected. Pin 21 is RCLR for the
22 16, 20, 13, 18, N.C.
23, 25, DS12887A/DS12C887A. On the EDIP, these pins are missing by design.
21, 22 26
27, 32

Data Strobe or Read Input. The DS pin has two modes of operation depending on
the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus
timing is selected. In this mode, DS is a positive pulse during the latter portion of the
bus cycle and is called data strobe. During read cycles, DS signifies the time that the
17 17 21 18 DS device is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes
the device to latch the written data. When the MOT pin is connected to GND, Intel
bus timing is selected. DS identifies the time period when the device drives the bus
with read data. In this mode, the DS pin operates in a similar fashion as the output-
enable (OE) signal on a generic RAM.

Active-Low Reset Input. The RESET pin has no effect on the clock, calendar, or
RAM. On power-up, the RESET pin can be held low for a time to allow the power
supply to stabilize. The amount of time that RESET is held low is dependent on the
application. However, if RESET is used on power-up, the time RESET is low should
exceed 200ms to ensure that the internal timer that controls the device on power-
up has timed out. When RESET is low and VCC is above VPF, the following occurs:
A. Periodic interrupt-enable (PIE) bit is cleared to 0.
B. Alarm interrupt-enable (AIE) bit is cleared to 0.
C. Update-ended interrupt-enable (UIE) bit is cleared to 0.
18 18 22 19 RESET D. Periodic-interrupt flag (PF) bit is cleared to 0.
E. Alarm-interrupt flag (AF) bit is cleared to 0.
F. Update-ended interrupt flag (UF) bit is cleared to 0.
G. Interrupt-request status flag (IRQF) bit is cleared to 0.
H. IRQ pin is in the high-impedance state.
I. The device is not accessible until RESET is returned high.
J. Square-wave output-enable (SQWE) bit is cleared to 0.
In a typical application, RESET can be connected to VCC. This connection allows
the device to go in and out of power fail without affecting any of the control
registers.

_____________________________________________________________________ 9
 Real-Time Clock
Pin Description (continued)
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

PIN
SO, NAME FUNCTION
PDIP EDIP PLCC TQFP

Active-Low Interrupt Request Output. The IRQ pin is an active-low output of the
device that can be used as an interrupt input to a processor. The IRQ output
remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. The processor program normally
19 19 23 21 IRQ reads the C register to clear the IRQ pin. The RESET pin also clears pending
interrupts. When no interrupt conditions are present, the IRQ level is in the high-
impedance state. Multiple interrupting devices can be connected to an IRQ
bus, provided that they are all open drain. The IRQ pin is an open-drain output
and requires an external pullup resistor to VCC.
Connection for a Primary Battery. (DS12885 Only.) Battery voltage must be held
between the minimum and maximum limits for proper operation. If a backup
supply is not supplied, VBAT must be grounded. Connect the battery directly to
20 — 24 22 VBAT
the VBAT pin. Diodes in series between the VBAT pin and the battery may
prevent proper operation. UL recognized to ensure against reverse charging
when used with a lithium battery.
Active-Low RAM Clear. The RCLR pin is used to clear (set to logic 1) all the
general-purpose RAM, but does not affect the RAM associated with the RTC. To
21 clear the RAM, RCLR must be forced to an input logic 0 during battery-backup
21 (DS12887A/ 25 24 RCLR mode when VCC is not applied. The RCLR function is designed to be used
DS12C887A) through a human interface (shorting to ground manually or by a switch) and not
to be driven with external buffers. This pin is internally pulled up. Do not use an
external pullup resistor on this pin.
Square-Wave Output. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the
23 23 27 26 SQW SQW pin can be changed by programming Register A, as shown in Table 1.
The SQW signal can be turned on and off using the SQWE bit in Register B. The
SQW signal is not available when VCC is less than VPF.

DC Power Pin for Primary Power Supply. When VCC is applied within normal
24 24 28 28 VCC limits, the device is fully accessible and data can be written and read. When
VCC is below VPF reads and writes are inhibited.

10 ____________________________________________________________________
 Real-Time Clock
Detailed Description

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Table 1. Crystal Specifications*
The DS12885 family of RTCs provide 14 bytes of real- PARAMETER SYMBOL MIN TYP MAX UNITS
time clock/calendar, alarm, and control/status registers
and 114 bytes (113 bytes for DS12C887 and Nominal
fO 32.768 kHz
DS12C887A) of nonvolatile, battery-backed static RAM. Frequency
A time-of-day alarm, three maskable interrupts with a Series
common interrupt output, and a programmable square- ESR 50 kΩ
Resistance
wave output are available. The devices also operate in
either 24-hour or 12-hour format with an AM/PM indica- Load
CL 6 pF
tor. A precision temperature-compensated circuit moni- Capacitance
tors the status of VCC. If a primary power-supply failure *The crystal, traces, and crystal input pins should be isolated
is detected, the devices automatically switch to a back- from RF generating signals. Refer to Application Note 58:
up supply. The backup supply input supports a primary Crystal Considerations for Dallas Real-Time Clocks for
battery, such as lithium coin cell. The devices are additional specifications.
accessed through a multiplexed address/data bus that
supports Intel and Motorola modes.
Oscillator Circuit
The DS12885 uses an external 32.768kHz crystal. The
COUNTDOWN
oscillator circuit does not require any external resistors CHAIN
or capacitors to operate. Table 1 specifies several crys-
tal parameters for the external crystal. Figure 1 shows a
functional schematic of the oscillator circuit. An enable
bit in the control register controls the oscillator. CL1 CL2 RTC REGISTERS
Oscillator startup times are highly dependent upon
crystal characteristics, PC board leakage, and layout.
High ESR and excessive capacitive loads are the major
contributors to long startup times. A circuit using a DS12885
crystal with the recommended characteristics and X1 X2
proper layout usually starts within one second.
An external 32.768kHz oscillator can also drive the CRYSTAL
DS12885. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is floated. Figure 1. Oscillator Circuit Showing Internal Bias Network

____________________________________________________________________ 11
 Real-Time Clock
Clock Accuracy
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

LOCAL GROUND PLANE (TOP LAYER)

The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and X1
the capacitive load for which the crystal was trimmed.
CRYSTAL
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise cou- X2
pled into the oscillator circuit can result in the clock run-
ning fast. Figure 2 shows a typical PC board layout for
isolation of the crystal and oscillator from noise. Refer to NOTE: AVOID ROUTING SIGNAL LINES
Application Note 58: Crystal Considerations with Dallas IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
Real-Time Clocks for more detailed information. THE PACKAGE UNLESS THERE IS GND
A GROUND PLANE BETWEEN THE
Clock Accuracy for DS12887, DS12887A, SIGNAL LINE AND THE DEVICE PACKAGE.
DS12C887, DS12C887A Only
Figure 2. Layout Example
The encapsulated DIP modules are trimmed at the fac-
tory to an accuracy of ±1 minute per month at +25°C.
automatically adjusted for months with fewer than 31
Power-Down/Power-Up days, including correction for leap years.
Considerations Before writing the internal time, calendar, and alarm reg-
The real-time clock continues to operate, and the RAM, isters, the SET bit in Register B should be written to logic
time, calendar, and alarm memory locations remain 1 to prevent updates from occurring while access is
nonvolatile regardless of the VCC input level. VBAT must being attempted. In addition to writing the 10 time, calen-
remain within the minimum and maximum limits when dar, and alarm registers in a selected format (binary or
VCC is not applied. When VCC is applied and exceeds BCD), the data mode bit (DM) of Register B must be set
VPF (power-fail trip point), the device becomes accessi- to the appropriate logic level. All 10 time, calendar, and
ble after tREC—if the oscillator is running and the oscil- alarm bytes must use the same data mode. The SET bit
lator countdown chain is not in reset (Register A). This in Register B should be cleared after the data mode bit
time allows the system to stablize after power is has been written to allow the RTC to update the time and
applied. If the oscillator is not enabled, the oscillator- calendar bytes. Once initialized, the RTC makes all
enable bit is enabled on power-up, and the device updates in the selected mode. The data mode cannot be
becomes immediately accessible. changed without reinitializing the 10 data bytes. Tables
2A and 2B show the BCD and binary formats of the time,
Time, Calendar, and Alarm calendar, and alarm locations.
Locations The 24-12 bit cannot be changed without reinitializing the
The time and calendar information is obtained by read- hour locations. When the 12-hour format is selected, the
ing the appropriate register bytes. The time, calendar, higher-order bit of the hours byte represents PM when it
and alarm are set or initialized by writing the appropri- is logic 1. The time, calendar, and alarm bytes are always
ate register bytes. Invalid time or date entries result in accessible because they are double-buffered. Once per
undefined operation. The contents of the 10 time, cal- second the seven bytes are advanced by one second
endar, and alarm bytes can be either binary or binary- and checked for an alarm condition.
coded decimal (BCD) format. If a read of the time and calendar data occurs during
The day-of-week register increments at midnight, incre- an update, a problem exists where seconds, minutes,
menting from 1 through 7. The day-of-week register is hours, etc., may not correlate. The probability of read-
used by the daylight saving function, so the value 1 is ing incorrect time and calendar data is low. Several
defined as Sunday. The date at the end of the month is methods of avoiding any possible incorrect time and
calendar reads are covered later in this text.

12 ____________________________________________________________________
 Real-Time Clock
The three alarm bytes can be used in two ways. First, condition when at logic 1. An alarm is generated each

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
when the alarm time is written in the appropriate hours, hour when the don’t-care bits are set in the hours byte.
minutes, and seconds alarm locations, the alarm inter- Similarly, an alarm is generated every minute with
rupt is initiated at the specified time each day, if the don’t-care codes in the hours and minute alarm bytes.
alarm-enable bit is high. In this mode, the “0” bits in the The don’t-care codes in all three alarm bytes create an
alarm registers and the corresponding time registers interrupt every second.
must always be written to 0 (Table 2A and 2B). Writing All 128 bytes can be directly written or read, except for
the 0 bits in the alarm and/or time registers to 1 can the following:
result in undefined operation.
1) Registers C and D are read-only.
The second use condition is to insert a “don’t care”
state in one or more of the three alarm bytes. The don’t- 2) Bit 7 of register A is read-only.
care code is any hexadecimal value from C0 to FF. The 3) The MSB of the seconds byte is read-only.
two most significant bits of each byte set the don’t-care

Table 2A. Time, Calendar, and Alarm Data Modes—BCD Mode (DM = 0)
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00H 0 10 Seconds Seconds Seconds 00–59
01H 0 10 Seconds Seconds Seconds Alarm 00–59
02H 0 10 Minutes Minutes Minutes 00–59
03H 0 10 Minutes Minutes Minutes Alarm 00–59
AM/PM 0 10 Hours 1–12 +AM/PM
04H 0 Hours Hours
0 10 Hours 00–23
AM/PM 0 10 Hours 1–12 +AM/PM
05H 0 Hours Hours Alarm
0 10 Hours 00–23
06H 0 0 0 0 0 Day Day 01–07
07H 0 0 10 Date Date Date 01–31
08H 0 0 0 10 Months Month Month 01–12
09H 10 Years Year Year 00–99
0AH UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 Control —
0BH SET PIE AIE UIE SQWE DM 24/12 DSE Control —
0CH IRQF PF AF UF 0 0 0 0 Control —
0DH VRT 0 0 0 0 0 0 0 Control —
0EH-31H X X X X X X X X RAM —
32H 10 Century Century Century* 00–99
33H-7FH X X X X X X X X RAM —

X = Read/Write Bit.
*DS12C887, DS12C887A only. General-purpose RAM on DS12885, DS12887, and DS12887A.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds regis-
ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.

____________________________________________________________________ 13
 Real-Time Clock
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Table 2B. Time, Calendar, and Alarm Data Modes—Binary Mode (DM = 1)
ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
00H 0 0 Seconds Seconds 00–3B
01H 0 0 Seconds Seconds Alarm 00–3B
02H 0 0 Minutes Minutes 00–3B
03H 0 0 Minutes Minutes Alarm 00–3B
AM/PM 0 Hours 01–0C +AM/PM
04H 0 0 Hours
0 Hours 00–17

AM/PM 0 0 Hours 01–0C +AM/PM

05H 0 Hours Alarm
0 Hours 00–17

06H 0 0 0 0 0 Day Day 01–07

07H 0 0 0 Date Date 01–1F
08H 0 0 0 0 Month Month 01–0C
09H 0 Year Year 00–63
0AH UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 Control —
0BH SET PIE AIE UIE SQWE DM 24/12 DSE Control —
0CH IRQF PF AF UF 0 0 0 0 Control —
0DH VRT 0 0 0 0 0 0 0 Control —
0EH-31H X X X X X X X X RAM —
32H N/A N/A Century* —
33H-7FH X X X X X X X X RAM —
X = Read/Write Bit.
*DS12C887, DS12C887A only. General-purpose RAM on DS12885, DS12887, and DS12887A.
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds regis-
ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be
written to 0 except for alarm mask bits.

14 ____________________________________________________________________
 Real-Time Clock
Control Registers

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
The real-time clocks have four control registers that are
accessible at all times, even during the update cycle.

Control Register A
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

Bit 7: Update-In-Progress (UIP). This bit is a status Bits 3 to 0: Rate Selector (RS3, RS2, RS1, RS0).
flag that can be monitored. When the UIP bit is a 1, the These four rate-selection bits select one of the 13 taps
update transfer occurs soon. When UIP is a 0, the on the 15-stage divider or disable the divider output.
update transfer does not occur for at least 244µs. The The tap selected can be used to generate an output
time, calendar, and alarm information in RAM is fully square wave (SQW pin) and/or a periodic interrupt. The
available for access when the UIP bit is 0. The UIP bit is user can do one of the following:
read-only and is not affected by RESET. Writing the 1) Enable the interrupt with the PIE bit;
SET bit in Register B to a 1 inhibits any update transfer
and clears the UIP status bit. 2) Enable the SQW output pin with the SQWE bit;
Bits 6, 5, and 4: DV2, DV1, DV0. These three bits are 3) Enable both at the same time and the same rate;
used to turn the oscillator on or off and to reset the or
countdown chain. A pattern of 010 is the only combina- 4) Enable neither.
tion of bits that turn the oscillator on and allow the RTC Table 3 lists the periodic interrupt rates and the square-
to keep time. A pattern of 11x enables the oscillator but wave frequencies that can be chosen with the RS bits.
holds the countdown chain in reset. The next update These four read/write bits are not affected by RESET.
occurs at 500ms after a pattern of 010 is written to DV0,
DV1, and DV2.

____________________________________________________________________ 15
 Real-Time Clock
Control Register B
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SET PIE AIE UIE SQWE DM 24/12 DSE

Bit 7: SET. When the SET bit is 0, the update transfer Bit 3: Square-Wave Enable (SQWE). When this bit is
functions normally by advancing the counts once per set to 1, a square-wave signal at the frequency set by
second. When the SET bit is written to 1, any update the rate-selection bits RS3–RS0 is driven out on the SQW
transfer is inhibited, and the program can initialize the pin. When the SQWE bit is set to 0, the SQW pin is held
time and calendar bytes without an update occurring in low. SQWE is a read/write bit and is cleared by RESET.
the midst of initializing. Read cycles can be executed in SQWE is low if disabled, and is high impedance when
a similar manner. SET is a read/write bit and is not VCC is below VPF. SQWE is cleared to 0 on RESET.
affected by RESET or internal functions of the device. Bit 2: Data Mode (DM). This bit indicates whether time
Bit 6: Periodic Interrupt Enable (PIE). The PIE bit is a and calendar information is in binary or BCD format.
read/write bit that allows the periodic interrupt flag (PF) bit The DM bit is set by the program to the appropriate for-
in Register C to drive the IRQ pin low. When the PIE bit is mat and can be read as required. This bit is not modi-
set to 1, periodic interrupts are generated by driving the fied by internal functions or RESET. A 1 in DM signifies
IRQ pin low at a rate specified by the RS3–RS0 bits of binary data, while a 0 in DM specifies BCD data.
Register A. A 0 in the PIE bit blocks the IRQ output from Bit 1: 24/12. The 24/12 control bit establishes the for-
being driven by a periodic interrupt, but the PF bit is still mat of the hours byte. A 1 indicates the 24-hour mode
set at the periodic rate. PIE is not modified by any internal and a 0 indicates the 12-hour mode. This bit is
device functions, but is cleared to 0 on RESET. read/write and is not affected by internal functions or
Bit 5: Alarm Interrupt Enable (AIE). This bit is a RESET.
read/write bit that, when set to 1, permits the alarm flag Bit 0: Daylight Saving Enable (DSE). This bit is a
(AF) bit in Register C to assert IRQ. An alarm interrupt read/write bit that enables two daylight saving adjust-
occurs for each second that the three time bytes equal ments when DSE is set to 1. On the first Sunday in
the three alarm bytes, including a don’t-care alarm April, the time increments from 1:59:59 AM to 3:00:00
code of binary 11XXXXXX. The AF bit does not initiate AM. On the last Sunday in October when the time first
the IRQ signal when the AIE bit is set to 0. The internal reaches 1:59:59 AM, it changes to 1:00:00 AM. When
functions of the device do not affect the AIE bit, but is DSE is enabled, the internal logic test for the first/last
cleared to 0 on RESET. Sunday condition at midnight. If the DSE bit is not set
Bit 4: Update-Ended Interrupt Enable (UIE). This bit is when the test occurs, the daylight saving function does
a read/write bit that enables the update-end flag (UF) not operate correctly. These adjustments do not occur
bit in Register C to assert IRQ. The RESET pin going when the DSE bit is 0. This bit is not affected by internal
low or the SET bit going high clears the UIE bit. functions or RESET.
The internal functions of the device do not affect the
UIE bit, but is cleared to 0 on RESET.

16 ____________________________________________________________________
 Real-Time Clock
Control Register C

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IRQF PF AF UF 0 0 0 0

Bit 7: Interrupt Request Flag (IRQF). This bit is set to Bit 5: Alarm Interrupt Flag (AF). A 1 in the AF bit indi-
1 when any of the following are true: cates that the current time has matched the alarm time.
PF = PIE = 1 If the AIE bit is also 1, the IRQ pin goes low and a 1
appears in the IRQF bit. This bit can be cleared by
AF = AIE = 1 reading Register C or with a RESET.
UF = UIE = 1 Bit 5: Update-Ended Interrupt Flag (UF). This bit is
Any time the IRQF bit is 1, the IRQ pin is driven low. set after each update cycle. When the UIE bit is set to
This bit can be cleared by reading Register C or with a 1, the 1 in UF causes the IRQF bit to be a 1, which
RESET. asserts the IRQ pin. This bit can be cleared by reading
Bit 6: Periodic Interrupt Flag (PF). This bit is read- Register C or with a RESET.
only and is set to 1 when an edge is detected on the Bits 3 to 0: Unused. These bits are unused in Register
selected tap of the divider chain. The RS3 through RS0 C. These bits always read 0 and cannot be written.
bits establish the periodic rate. PF is set to 1 indepen-
dent of the state of the PIE bit. When both PF and PIE
are 1s, the IRQ signal is active and sets the IRQF bit.
This bit can be cleared by reading Register C or with a
RESET.

Control Register D
MSB LSB
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VRT 0 0 0 0 0 0 0

Bit 7: Valid RAM and Time (VRT). This bit indicates the RTC data and RAM data are questionable. This bit
the condition of the battery connected to the VBAT pin. is unaffected by RESET.
This bit is not writeable and should always be 1 when Bits 6 to 0: Unused. The remaining bits of Register D
read. If a 0 is ever present, an exhausted internal lithi- are not usable. They cannot be written and they always
um energy source is indicated and both the contents of read 0.

____________________________________________________________________ 17
 Real-Time Clock
Century Register when reading Register C. Each used flag bit should be
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

examined when Register C is read to ensure that no

(DS12C887/DS12C887A Only) interrupts are lost.
The century register at location 32h is a BCD register The second flag bit method is used with fully enabled
designed to automatically load the BCD value 20 as the interrupts. When an interrupt flag bit is set and the cor-
year register changes from 99 to 00. The MSB of this responding interrupt-enable bit is also set, the IRQ pin is
register is not affected when the load of 20 occurs, and asserted low. IRQ is asserted as long as at least one of
remains at the value written by the user. the three interrupt sources has its flag and enable bits
Nonvolatile RAM (NV RAM) set. The IRQF bit in Register C is a 1 whenever the IRQ
pin is driven low. Determination that the RTC initiated an
The general-purpose NV RAM bytes are not dedicated interrupt is accomplished by reading Register C. A logic
to any special function within the device. They can be 1 in bit 7 (IRQF bit) indicates that one or more interrupts
used by the processor program as battery-backed have been initiated by the device. The act of reading
memory and are fully available during the update cycle. Register C clears all active flag bits and the IRQF bit.
Interrupts Oscillator Control Bits
The RTC family includes three separate, fully automatic When the DS12887, DS12887A, DS12C887, and
sources of interrupt for a processor. The alarm interrupt DS12C887A are shipped from the factory, the internal
can be programmed to occur at rates from once per oscillator is turned off. This prevents the lithium energy
second to once per day. The periodic interrupt can be cell from being used until the device is installed in a
selected for rates from 500ms to 122µs. The update- system.
ended interrupt can be used to indicate to the program
that an update cycle is complete. Each of these inde- A pattern of 010 in bits 4 to 6 of Register A turns the
pendent interrupt conditions is described in greater oscillator on and enables the countdown chain. A pat-
detail in other sections of this text. tern of 11x (DV2 = 1, DV1 = 1, DV0 = X) turns the oscil-
lator on, but holds the countdown chain of the oscillator
The processor program can select which interrupts, if in reset. All other combinations of bits 4 to 6 keep the
any, are to be used. Three bits in Register B enable the oscillator off.
interrupts. Writing a logic 1 to an interrupt-enable bit
permits that interrupt to be initiated when the event Square-Wave Output Selection
occurs. A 0 in an interrupt-enable bit prohibits the IRQ Thirteen of the 15 divider taps are made available to a 1-
pin from being asserted from that interrupt condition. If of-16 multiplexer, as shown in the functional diagram.
an interrupt flag is already set when an interrupt is The square-wave and periodic-interrupt generators
enabled, IRQ is immediately set at an active level, share the output of the multiplexer. The RS0–RS3 bits in
although the interrupt initiating the event may have Register A establish the output frequency of the multi-
occurred earlier. As a result, there are cases where the plexer (see Table 1). Once the frequency is selected, the
program should clear such earlier initiated interrupts output of the SQW pin can be turned on and off under
before first enabling new interrupts. program control with the square-wave enable bit, SQWE.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde- Periodic Interrupt Selection
pendent of the state of the corresponding enable bit in The periodic interrupt causes the IRQ pin to go to an
Register B. The flag bit can be used in a polling mode active state from once every 500ms to once every 122µs.
without enabling the corresponding enable bits. The This function is separate from the alarm interrupt, which
interrupt flag bit is a status bit that software can interro- can be output from once per second to once per day.
gate as necessary. When a flag is set, an indication is The periodic interrupt rate is selected using the same
given to software that an interrupt event has occurred Register A bits that select the square-wave frequency
since the flag bit was last read; however, care should (Table 1). Changing the Register A bits affects the
be taken when using the flag bits as they are cleared square-wave frequency and the periodic-interrupt out-
each time Register C is read. Double latching is includ- put. However, each function has a separate enable bit in
ed with Register C so that bits that are set remain sta- Register B. The SQWE bit controls the square-wave out-
ble throughout the read cycle. All bits that are set (high) put. Similarly, the PIE bit in Register B enables the peri-
are cleared when read, and new interrupts that are odic interrupt. The periodic interrupt can be used with
pending during the read cycle are held until after the software counters to measure inputs, create output inter-
cycle is completed. One, two, or three bits can be set vals, or await the next needed software function.

18 ____________________________________________________________________
 Real-Time Clock
sponding time byte and issues an alarm if a match or if

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Table 3. Periodic Interrupt Rate and
Square-Wave Output Frequency a don’t-care code is present in all three positions.
There are three methods that can handle RTC access
SELECT BITS tPI PERIODIC
SQW OUTPUT that avoid any possibility of accessing inconsistent time
REGISTER A INTERRUPT
FREQUENCY and calendar data. The first method uses the update-
RS3 RS2 RS1 RS0 RATE ended interrupt. If enabled, an interrupt occurs after
0 0 0 0 None None every update cycle that indicates over 999ms is avail-
0 0 0 1 3.90625ms 256Hz
able to read valid time and date information. If this
interrupt is used, the IRQF bit in Register C should be
0 0 1 0 7.8125ms 128Hz cleared before leaving the interrupt routine.
0 0 1 1 122.070µs 8.192kHz
A second method uses the update-in-progress bit (UIP)
0 1 0 0 244.141µs 4.096kHz in Register A to determine if the update cycle is in
0 1 0 1 488.281µs 2.048kHz progress. The UIP bit pulses once per second. After
0 1 1 0 976.5625µs 1.024kHz the UIP bit goes high, the update transfer occurs 244µs
later. If a low is read on the UIP bit, the user has at least
0 1 1 1 1.953125ms 512Hz
244µs before the time/calendar data is changed.
1 0 0 0 3.90625ms 256Hz Therefore, the user should avoid interrupt service rou-
1 0 0 1 7.8125ms 128Hz tines that would cause the time needed to read valid
1 0 1 0 15.625ms 64Hz time/calendar data to exceed 244µs.
1 0 1 1 31.25ms 32Hz The third method uses a periodic interrupt to determine if
1 1 0 0 62.5ms 16Hz an update cycle is in progress. The UIP bit in Register A
is set high between the setting of the PF bit in Register C
1 1 0 1 125ms 8Hz
(Figure 3). Periodic interrupts that occur at a rate greater
1 1 1 0 250ms 4Hz than tBUC allow valid time and date information to be
1 1 1 1 500ms 2Hz reached at each occurrence of the periodic interrupt.
The reads should be complete within one (tPI/2 + tBUC)
Update Cycle to ensure that data is not read during the update cycle.
The device executes an update cycle once per second
regardless of the SET bit in Register B. When the SET Handling, PC Board Layout,
bit in Register B is set to 1, the user copy of the double- and Assembly
buffered time, calendar, and alarm bytes is frozen and The EDIP module can be successfully processed
does not update as the time increments. However, the through conventional wave-soldering techniques so long
time countdown chain continues to update the internal as temperature exposure to the lithium energy source
copy of the buffer. This feature allows time to maintain does not exceed +85°C. Post-solder cleaning with water-
accuracy independent of reading or writing the time, washing techniques is acceptable, provided that ultra-
calendar, and alarm buffers, and also guarantees that sonic vibration is not used. Such cleaning can damage
time and calendar information is consistent. The update the crystal.
cycle also compares each alarm byte with the corre-

1 SECOND

UIP
tBUC
UF

tP1/2 tP1/2
PF

t PI

tBUC = DELAY TIME BEFORE UPDATE

CYCLE = 244μs

Figure 3. UIP and Periodic Interrupt Timing

____________________________________________________________________ 19
 Real-Time Clock
Pin Configurations
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

TOP VIEW

MOT 1 24 VCC MOT 1 24 VCC

X1 2 23 SQW N.C. 2 23 SQW

X2 3 22 N.C. N.C. 3 22 N.C.

AD0 4 21 RCLR AD0 4 21 N.C.

(RCLR)
AD1 5 20 VBAT AD1 5 20 N.C.
DS12885 DS12887
AD2 6 19 IRQ AD2 6 19 IRQ
DS12885S DS12887A
AD3 7 18 RESET AD3 7 DS12C887 18 RESET
AD4 8 17 DS AD4 8 DS12C887A 17 DS

AD5 9 16 GND AD5 9 16 N.C.

AD6 10 15 R/W AD6 10 15 R/W

AD7 11 14 AS AD7 11 14 AS

GND 12 13 CS GND 12 13 CS

SO, PDIP EDIP

( ) FOR THE DS12887A/DS12C887A.
RESET
RCLR
VBAT

GND
R/W
IRQ

DS
22
25
24
23

21
20
19

N.C. 26 18 N.C.
SQW 27 17 AS
VCC 28 16 CS
N.C. 1 15 GND

MOT 2 DS12885Q 14 AD7

X1 3 13 N.C.
X2 4 12 AD6
11
AD5 10
5
6
7
8
9
AD0
AD1
AD2
AD3
AD4

N.C.

PLCC

NOTE: THE DS12887A AND DS12C887A CANNOT BE STORED OR SHIPPED IN CONDUCTIVE MATERIAL
THAT WILL GIVE A CONTINUITY PATH BETWEEN THE RAM CLEAR PIN AND GROUND.

20 ____________________________________________________________________
 Real-Time Clock
Pin Configurations (continued) Ordering Information

DS12885/DS12887/DS12887A/DS12C887/DS12C887A
PIN- TOP
TOP VIEW PART TEMP RANGE
PACKAGE MARK*
DS12885 0°C to +70°C 24 PDIP DS12885

SQW
MOT
N.C.

N.C.

N.C.
VCC
X2

X1

DS12885+ 0°C to +70°C 24 PDIP DS12885

32 31 30 29 28 27 26 25 DS12885N -40°C to +85°C 24 PDIP DS12885

AD0 1 24 RCLR
DS12885N+ -40°C to +85°C 24 PDIP DS12885
DS12885Q 0°C to +70°C 28 PLCC DS12885Q
AD1 2 23 N.C.
DS12885Q+ 0°C to +70°C 28 PLCC DS12885Q
AD2 3 22 VBAT
DS12885QN -40°C to +85°C 28 PLCC DS12885Q
N.C. 4 21 IRQ DS12885QN+ -40°C to +85°C 28 PLCC DS12885Q
DS12885T
AD3 5 20 N.C. DS12885Q/T&R 0°C to +70°C 28 PLCC DS12885Q
N.C. 6 19 RESET DS12885Q+T&R 0°C to +70°C 28 PLCC DS12885Q

AD4 7 18 DS DS12885QN/T&R -40°C to +85°C 28 PLCC DS12885Q

DS12885QN+T&R -40°C to +85°C 28 PLCC DS12885Q
AD5 8 17 GND
24 SO
DS12885S 0°C to +70°C DS12885S
9 10 11 12 13 14 15 16
(300 mils)
24 SO
AD6

N.C.

AD7

GND

CS

AS

N.C.

R/W

DS12885S+ 0°C to +70°C DS12885S

(300 mils)
TQFP 24 SO
DS12885SN -40°C to +85°C DS12885S
(300 mils)
24 SO
Thermal Information DS12885SN+ -40°C to +85°C DS12885S
(300 mils)

PACKAGE THETA-JA (°C/W) THETA-JC (°C/W) 24 SO

DS12885S/T&R 0°C to +70°C DS12885S
(300 mils)
PDIP 75 30
SO 105 22 24 SO
DS12885S+T&R 0°C to +70°C DS12885S
(300 mils)
PLCC 95 25
DS12885T 0°C to +70°C 32 TQFP DS12885
DS12885T+ 0°C to +70°C 32 TQFP DS12885
Package Information
DS12885TN -40°C to +85°C 32 TQFP DS12885
PIN-PACKAGE DOCUMENT NO. DS12885TN+ -40°C to +85°C 32 TQFP DS12885
24 SO (300 mils) 56-G4009-001 DS12885T/T&R 0°C to +70°C 32 TQFP DS12885
24 PDIP 56-G5000-003 DS12887 0°C to +70°C 24 EDIP DS12887
24 EDIP 56-G0001-001 DS12887+ 0°C to +70°C 24 EDIP DS12887
28 PLCC 56-G4001-001 DS12887A 0°C to +70°C 24 EDIP DS12887A
32 TQFP 56-G4004-001 DS12887A+ 0°C to +70°C 24 EDIP DS12887A
DS12C887 0°C to +70°C 24 EDIP DS12C887

Chip Information DS12C887+ 0°C to +70°C 24 EDIP DS12C887

DS12C887A 0°C to +70°C 24 EDIP DS12C887A
TRANSISTOR COUNT: 17,000
DS12C887A+ 0°C to +70°C 24 EDIP DS12C887A
PROCESS: CMOS
+Denotes a lead-free/RoHS-compliant device.
SUBSTRATE CONNECTED TO GROUND
T&R = Tape-and-reel.
*A “+” anywhere on the top mark indicates a lead-free device,
and an “N” indicates an industrial temperature range device.
____________________________________________________________________ 21
 Real-Time Clock
Revision History
DS12885/DS12887/DS12887A/DS12C887/DS12C887A

Rev 0; 6/05: Initial release of combined data sheet.

Rev 1; 4/06: Corrected Intel Bus Write Timing diagram (page 4), Intel Bus Read Timing, IRQ Release Delay
Timing, and Power-Up/Down Timing diagrams (page 5), and Functional Diagram (page 7). Added
Handling, PC Board Layout, and Assembly section (page 20).
Rev 2; 5/06: Corrected Intel Bus Write Timing diagram (page 4); added PLCC pin description information
(pages 8, 9, and 10); changed pin 16 from N.C. to GND for the SO, PDIP packages (pages 8, 9,
and 20).
Rev 3; 2/07: Corrected Intel Bus Write Timing diagram (page 4); updated Ordering Information (page 20);
added Package Information table (page 20); removed package drawings (pages 22 to 27).

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.

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