EC822-Logic_family

LOW POWER VLSI DESIGN
EC822-EVENT-2
Topic: Logic Family
This Photo by Unknown author is licensed under CC BY-SA

INTRODUCTION
Today, digital logic design is performed by using standard cell libraries and place
and route computer aided design (CAD) tools.
However, many different logic styles have been and continue to be proposed for
general-purpose and specialized standard cell libraries.
Low power is even more important than speed and silicon area.
But it is increasingly difficult to achieve in very deep submicron technologies as

well as for specialized libraries for self-timed or cryptographic applications.
To achieve a very low dynamic power, a large number of logic families have
been proposed and used in various designs.
LOGIC FAMILY
• Static CMOS Logic.

• Ratioed Logic.
• DCVSL Logic.
• Pass Transistor logic.
• Differential Pass Transistor Logic.
• Transmission Gate( TG).
• Dynamic CMOS Design.
COMPLEMENTA
RY DESIGN
• PMOS “Pull-Up” Network

(PUN)
• NMOS “Pull-Down” Network

(PDN)
WHY DIVISION?
• NMOS
# When Vg= 1 --> NMOS ON--> VGS >
Vth
#Vg – Vs > Vth (0.7)
# Vdd – (Vdd- Vth) >+ Vth (0.7)
# Vth = Vth
#Vout = 1 ( Hence it Passes bad Logic
"1").
• PMOS:
# When Vg= 0 -> PMOS ON--> VGS < Vth

#Vg – Vs < Vth (0.7)
# 0 - Vth < Vth (0.7)
# - Vdd < Vth
# Vout = 0 ( Hence it passes bad logic
WHY DIVISION?
• PMOS:
# When Vg=0 --> PMOS ON--> VGS <
Vth
#Vg – Vs < Vth (0.7)
# 0 - Vdd < Vth (0.7)
# - Vdd < Vth
# Vout =1 ( Hence it passes good logic
"1")
• NMOS
# When Vg= 1 --> PMOS ON--> VGS >
Vth
#Vg – Vs > Vth (0.7)
# Vdd – 0 > Vth (0.7)
THRESHOLD VOLTAGE
PROS:
• Full rail-to-rail swing; high noise margins.
• Logic levels not dependent upon relative device sizes.
• Always a path to Vdd or Gnd in steady state; low output impedance.
• Extremely high input resistance; nearly zero steady-state input current.
• No direct path steady state between power and ground; no static power
dissipation.
CONS:
• N inputs => 2N transistors in design
STATIC CMOS LOGIC
• A static CMOS gate is a combination
of two networks, called the pull-up
network (PUN) and the pull-down
network(PDN).
• The figure shows a generic N input
logic gate where all inputs are
distributed to both the pull-up and
pull-down networks.
• Except during switching, output
connected to either VDD or GND via
a low resistance path.
CMOS NAND
Truth Table:
CMOS NOR
Truth Table:
COMPLEX CMOS LOGIC
Full Adder:
-> Three inputs (A, B, Cin)
-> Two outputs (Sum,
Carry)
Sum = A ^ B ^ Cin
Carry = AB + Cin ( A +
B)
PROPERTIES OF COMPLEMENTARY CMOS GATES
1) High noise margins : V OH and V OL are at V DD and GND, respectively.
2) No static power consumption : There never exists a direct path between VDD
and VSS (GND) in steady-state mode.
3) Comparable rise and fall times: (under the appropriate scaling conditions).
4) For symmetrical response (dc, ac).
5) Better performance.
Advantages of static CMOS
– Low static power
– Robust
– Supported by most synthesis & back-end tools
Disadvantage of static CMOS

– For N inputs, requires (at least) 2N transistors.
– PUN can be area consuming.
RATIOED LOGIC
• Ratioed logic is an attempt to reduce the number of
transistors required to implement a given logic function,
at the cost of reduced robustness and extra power
dissipation.
• The purpose of the PUN in complementary CMOS is to
provide a conditional path between VDD and the output
when the PDN is turned off.
• In ratioed logic, the entire PUN is replaced with a single
load device that pulls up the output when the PDN is
turned off.
DIFFERENT LOGIC DESIGN
• Goal: Reduce # of transistors over CMOS

• Ratioed = functionality depends on ratios!
ADVANTAGES
• Reduced number of transistors (N+1 vs. 2N for complementary
CMOS).
• The nominal high output voltage (VOH) for this gate is VDD since the pull-
down devices is turned off when the output is pulled high.
• Reduces Static Power Dissipation.
• The voltage swing on the output and overall functionality of the gate is
dependent on the device size, the circuit is called ratioed.
DISADVANTAGES:
• Pseudo-NMOS gates is static power that happens when the output is low,
because a direct current path exists between VDD and GND
through the load and driver devices.
PSEUDO-NMOS NOR AND NAND GATES.
DIFFERENTIAL CASCADE VOLTAGE SWITCH LOGIC
• It is possible to create a ratioed logic style that

allows us to completely eliminate static
currents and provide rail-to-rail swing.
• This requires the use of feedback concepts.
• In this particular style of logic, complementary

inputs are fed into the gate and the gates provide
complementary outputs.
• The feedback mechanism ensures that the load

device is turned off when not needed.
WORKING:
• PDN1 and PDN2 are mutually exclusive
– If PDN1 conducts PDN2 is off

– And vice versa
• DCVSL details
• DCVSL has full rail-to-rail swing
• No static power consumption
• Provides complementary signal
• Gate is still ratioed!
DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC (DCVSL)
Advantages of (DCVSL) over static CMOS
– Complementary outputs immediately available.
– May reduce the number of transistors up to 2x.
– Keeps values (similar to latches).
• Disadvantages
– Doubles number of wires (affects density).
– Often higher dynamic power dissipation.

PASS TRANSISTOR
• A popular and widely-used alternative to
complementary CMOS is pass-transistor logic.
• Which attempts to reduce the number of
transistors required to implement logic by
allowing the primary inputs to drive gate
terminals as well as source/drain terminals.
• This is in contrast to logic families that we have
AND Gate using Pass
transistor studied so far, which only allow primary inputs
to drive the gate terminals of MOSFETS.
AND GATE WITH PASS TRANSISTORS
• Requires 4 logic gates (needs an inverter)

• CMOS logic would require 6 logic gates
• The gate can be static
• No rail-to-rail swing
Logic Diagram of AND gate Truth Table of AND

gate
ADVANTAGES:  Gate is static – a low-impedance path
exists to both supply rails under all
circumstances.
 N transistors instead of 2N.
 No static power consumption.
 Ratioless.
 Bidirectional (versus unidirectional).
 Non-inverting logic
DISADVANTAGES:
 Pure PT logic is not regenerative.(The
signal gradually degrades).
CASCADING PASS TRANSISTORS
DIFFERENTIAL
PASS TRANSISTOR
LOGIC:
• For high performance

design, a differential pass-
transistor logic family,
called CPL or DPL, is
commonly used.
• The basic idea is to accept
true and complementary
inputs and produce true
and complementary
outputs.
DIFFERENTIAL PT LOGIC (CPL)
Differential so complementary data inputs and outputs are always available (so don’t need extra
inverters).
Still static, since the output defining nodes are always tied to VDD or GND through a low
resistance path
Design is modular; all gates use the same topology, only the inputs are permuted.
Simple XOR makes it attractive for structures like adders.
Fast (assuming number of transistors in series is small).
Additional routing overhead for complementary signals.
Still have static power dissipation problems.

CPL/DPL EFFICIENT FOR XOR ETC.
Pros Cons
• Additional routing overhead (2x)
• – No need for extra inverters (theoretically)
• Static power dissipation
• – Static and modular (same topology)
problems
• – Simple XOR (good for adders)
• Bidirectional
CPL/DPL-BASED FULL ADDER
 20+4*2 = 28 transistors (=static CMOS)

 Not Good for Designing Adders.
TRANSMISSION GATE
LOGIC
• NMOS and PMOS connected in parallel.
• NMOS good pull-down; PMOS good pull-up.
• Allows full rail transition – Ratioless logic.
• Equivalent resistance relatively constant during
transition.
• Complementary signals required for gates.
• Some gates can be efficiently implemented using
transmission gate logic (XOR in particular).
EQUIVALENT TG RESISTANCE
•For a rising transition at the output (step input) .

•– NMOS sat, PMOS sat until output reaches |VTP|.
•– NMOS sat, PMOS lin until output reaches VDD-VTN.
•– NMOS off, PMOS lin for the final VDD – VTN to VDD voltage
swing.
APPLICATION
S:
• Useful for multiplexers (select
between multiple inputs) and
XORs.
Input Output-F
~S A
S B
DYNAMIC CMOS DESIGN
• Dynamic circuit class, which relies on temporary
storage of signal values on the capacitance of
high-impedance circuit nodes.
• In this section, an alternate logic style called

dynamic logic is presented that obtains a similar
result, while avoiding static power consumption.
• With the addition of a clock input, it uses a

sequence of pre charge and conditional evaluation
phases.
• The basic construction of an (n-type) dynamic logic gate is shown in Figure.
• The PDN (pull-down network) is constructed exactly as in complementary CMOS.
• The operation of this circuit is divided into two major phases:
• Pre charge and evaluation, with the mode of operation determined by the clock signal CLK.
DISADVANTAGES:
• Problem with cascading such as a circuit:-

• When Ø is low, both P1 and P2 are pre charged to a high voltage. However when Ø is
high, delay through on the output P1 may erroneously discharge P2.

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LOW POWER VLSI DESIGN

Topic: Logic Family

This Photo by Unknown author is licensed under CC BY-SA

But it is increasingly difficult to achieve in very deep submicron technologies as

• Static CMOS Logic.

• PMOS “Pull-Up” Network

• NMOS “Pull-Down” Network

# When Vg= 0 -> PMOS ON--> VGS < Vth

4) For symmetrical response (dc, ac).

Disadvantage of static CMOS

• Goal: Reduce # of transistors over CMOS

• It is possible to create a ratioed logic style that

• This requires the use of feedback concepts.

• In this particular style of logic, complementary

• The feedback mechanism ensures that the load

• PDN1 and PDN2 are mutually exclusive

– If PDN1 conducts PDN2 is off

Advantages of (DCVSL) over static CMOS

– Complementary outputs immediately available.

– May reduce the number of transistors up to 2x.

– Keeps values (similar to latches).

– Doubles number of wires (affects density).

– Often higher dynamic power dissipation.

• Requires 4 logic gates (needs an inverter)

Logic Diagram of AND gate Truth Table of AND

• For high performance

Simple XOR makes it attractive for structures like adders.

Fast (assuming number of transistors in series is small).

Additional routing overhead for complementary signals.

Still have static power dissipation problems.

 20+4*2 = 28 transistors (=static CMOS)

•For a rising transition at the output (step input) .

• In this section, an alternate logic style called

• With the addition of a clock input, it uses a

• Problem with cascading such as a circuit:-

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