Microprocessor & Assembly

Language
Abrham Debasu (Assistant professor)

Bahir Dar University, BiT, Computing faculty

 Basics of Microprocessor

What is Microprocessor ?

• Is an integrated circuit that contains all the functions in a single chip

 Evolution of Microprocessors

Intel 4004/4040
Intel 4004/4040
Early microprocessors
Intel 4004/4040
Intel 4004/4040

Intel 8086/8088
Intel 80286
Advanced microprocessors
Intel 80386
Intel 80486
Pentium, i3, i5, i7…
Why do we study 8086?

This is the base for all microprocessor family

that it supports Pipelining
 8086 Microprocessor

 8086 Microprocessor is an enhanced version of 8085

 It has 20 bit address bus and can access up to 2^20 memory locations (1 MB)
 It can support up to 64K I/O ports
 It uses two stages of pipelining, i.e. fetch Stage and Execute Stage, which
improves performance.

 Read about the difference between 8085 and 8086

 Register organization of 8086

 GPRs

 Pointer and index registers

 Segment registers

 Flags ( status/conditional and control flags)

General purpose Registers (GPRs):

 Can be used for arithmetic and logic operations and data movement

 Each of them is further divided into two subparts of 8-

bit length each: one high, which stores the higher-order
bits and another low which stores the lower order bits

 GPRs can be used together (as register pair) to store 16-bit data
 Pointers and Index Registers:

 These registers contain the offset of data and instructions.

Instruction Pointer (IP)

 The instruction pointer (IP or program counter) usually
stores the address of the next instruction that is to be
executed.
Stack Pointer (SP)

 The Stack Pointer points at the current top value of the Stack

Source Index (SI)

 It stores the offset address of the source
Destination Index (DI)
 It stores the offset address of the Destination
Segment Registers:
 The process of dividing the entire memory
 It has four 16-bit segment registers
CS, DS, ES, and SS
Why do we need segmentation in 8086?
 Segmentation helps addressing
 Also build relocatable code with help of segments
 It provides a powerful memory management mechanism.
 Segment Registers:
 It has 20 bit address bus
 It can address 1MB =2^20
FFFFFH
 Curently the physical memory is divided in to a number of segment
 but in 8086MP can work with only 64KB =2^16 Extra Segment
 Allows only four active segments at a time
Data Segment

64KB Stak Segment

4 x 64KB= 256KB (without overlapping)

Code Segment
We can create 4x 256 segment if required

00000H
Segment Registers:
Code Segment (CS) Register: Containing address of all
executable instructions. The user cannot modify the content of
these registers.
Data Segment (DS) Register: Containing address of base location
for variables. The user can modify the content of the data
segment.
Stack Segment (SS) Registers: The SS is used to store the
information about the memory segment. The operations of the SS
are mainly Push and Pop.
Extra Segment (ES) Register: If there is less space in that
segment, then ES is used. ES is also used for copying purpose
 Generation of 20-bit Address
 SEG x 10 + OFFSET

Example

The contents of the following registers are:

CS=1111H, DS=1678H, ES= 1298H, SS=6289H, IP=6721H, BX= 7865H, DI=1235H, BP 7821H
Calculate the corosponding physical and logical address in CS,DS,ES & SS
The contents of the following registers are:
CS=1111H, DS=1678H, ES= 1298H, SS=6289H, IP=6721H, BX= 7865H, DI=1235H, BP 7821H
Calculate the corosponding physical and logical address in CS,DS,ES & SS

 SEG x 10 + OFFSET
P.A of CS = CS x 10 + Offset
1111H x 10 = 11110H + 6721H
17831H
L.A = CS:IP
1111H:6721H
 Flag Register

There are total 9 flags in 8086 and the flag register is divided into
two types:
A. Status Flags
B. Control Flags
 Flag Register
Overflow Flag (OF)
 Overflow Flag is set to 1 when there is a signed overflow. For example, when you
add bytes 100 + 50 (result is not in range -128…127).

Sign Flag (SF)

 Sign Flag is set to 1 when result is negative. When result is positive it is set
to 0.
Zero Flag (ZF)
 Zero Flag (ZF) is set to 1 when result is zero. For non-zero result this flag is set to 0.

Auxiliary Flag (AF)

 Auxiliary Flag is set to 1 when there is an overflow for low nibble (4 bits)

Parity Flag (PF)

 Parity Flag is set to 1 when there is even number of one bits in result
Carry Flag (CF)
 Carry Flag is set to 1 when there is carry
Architecture of 8086 Microprocessor
How does Intel 8086 work?

 Logicaly separated as EU and BIU

 Why is divided into BIU and EU?
Can work simultaneously to increase system speed
/ pipelining
 How does EU work internally?
 The EU receives instructions from the instruction queue
 Operands from any of GPR (AX is default)

 Then via system bus reached in to ALU

 Before sending back to any of GPR, ALU will consult

BIU to know the current status of execution
How does Intel 8086 work?

 How does BIU work?

 Receives request from EU in such a way that SEG:OFFSET

 Then the adder generates physical address

 Then via segment register passes through system bus

 Why IP is located in BIU? and what will

happen if it is located in EU?
 Your ans?
BIU
 Used to interface to the to the outside world.

 The BIU is responsible for performing all external bus

operations, such as instruction fetching, reading and
writing of data operands for memory, and inputting or
outputting data.
 It is responsible for instruction queuing

 To implement these functions, the BIU contains

the segment registers, the instruction pointer
BIU
 The Bus Interface Unit (BIU) of an 8086
microprocessor starts fetching a new instruction when
the following three conditions are met:

• The Execution Unit (EU) is requesting

• The BIU's instruction stream queue is not full
• Whenever queue has two byte free space
EU

 Tells BIU where to fetch instructions or data from

 Decodes instructions
 Executes instructions
 Individual Assignment

 Draw the detailed architecture of Pentium 4 and Core2 and core i3

microprocessors:
 Explain the working principle
 Register organization, MEMORY PAGING and Paging Registers
Addressing mode
 What is addressing mode?

 The way in which the operand of instruction can be accessed

 The operands could be in register,memory or an immediate value

Why addressing modes are required in microprocessor ?

 Addressing modes are required in a microprocessor to specify the location of data or

instructions in memory. They provide flexibility and efficiency in accessing and
manipulating data.
Types of addressing mode
Register Addressing moder
 The operands are contained in a register
 Both the source and destination operand should be a register
 Syntax MOV Destination, Source
 Example
MOV AX, AX
BX BX

AL BL

This instruction copies from BX into AX

Rule for Register Addressing mode

 Both can’t be segment registers

 IP can’t be a destination
 Moving from GPR to CS not allowed
 An Immediate Addressing mode

 The addressing mode in which the data operand is a part of instruction

Example
MOV AX, 1234H

Rule
An immediate value can’t be a destination
Direct addressing mode

 The offset value of the given data is a part of the instructions

MOV AX, [1234H]
Register indirect addressing mode

 The offset value of the given data will be in a register

 The registers could be
 Base registers (BX, BP)
 Index register (SI, DI)
MOV AX, [BX]
MOV CX, [SI]
Base plus index addressing mode

 The offset value of the given data will be both base and index register
MOV AX, [BX + SI]
MOV CX, [BP + DI]
Example
MOV AX, [BX + SI]
BX= 0001H
BX= 0001H
SI= 12ABH
SI= 12ABH 12AC *10+1111H
DS= 1111H
Register relative addressing mode

 The displacement value and a register is apart of the given instruction

 MOV AX, Displacment [BX]
MOV CX, 5000[BP ]
Base relative plus index Register addressing
mode
 The displacement value and a Base plus index register is apart of the given
instruction
 MOV AX, Displacment [BX+SI]
MOV CX, 5000[BP+DI ]

Reading Assignment
 Exercise

Consider AX = 1212h; BX= 1B1Bh; CX=2323h; DX=2C2Ch; SI= 0050h; DI = 0110h; SP= 23h; BP= 0100h;
DS=1010h
Calculate the effective address of the following instructions

(i) MOV AX, [2000h]

(ii) MOV AX, 20h [BP]
(iii) MOV AX, 40h [BX][DI]
(iv) MOV AX, 500h
Instruction set
Instruction set of 8086

What is an instruction?
 An instruction is a binary patern designed inside a
microprocessor to perform a specific function
 The entire group of instruction that a microprocessor
supprts is Instruction set

 8086 has more than 20,000 instruction

Instruction format of 8086

The Instruction format vary from 1 to 6 bytes in length

Classification of instruction set

 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 Program Exacution TransferInstructions
 String Instructions
 Processor Control Instructions
 Data Transfer Instructions

 Are used to transfer data from source to destination operands

 The operand can be:
 A constant/Immediate value,
 memory location,
 register or I/O port address
Data Transfer Instructions
Data Transfer Instructions
Data Transfer Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
Arithmetic Instructions
 Exercise
For the figure below
 What is the result of executing the following instruction?
ADD AX , [ DI + BX +2H]

 Assume that AX and BX registers contain 1100H and 0ABCH,

respectively. What is the result of executing the instruction
ADD AX, BX
MOV [BX], AX
Bit Manipulation Instruction
Bit Manipulation Instruction
Bit Manipulation Instruction
Bit Manipulation Instruction
Bit Manipulation Instruction