UNIT 3 Instruction set

Architecture and Assembly

language programming
Self study
What is RISC processor
What is CISC processor
What is difference and applications.
Von Neuman and Harvard Architecture
Addressing Modes:
Purpose of addressing modes:

Phases of Instruction cycle:

1. Opcode Fetch
2. Decode instruction
3. Execution
 Implied mode:
• In this mode, the operand is explicitly mentioned
in opcode, e.g. complement accumulator,
• Also called as zero address instruction ( no
address field required,)
• Length of instruction is only one word

1. Implied Addressing Mode …

1. Implied Addressing Modes …
 Immediate Addressing Mode:
• The operand is provided immediately after opcode.
• Operand is in instruction only
• Useful for initializing the registers with constant value.

2. Immediate Addressing Mode …

2. Immediate Addressing Modes …
 Register Addressing Mode:
• This addressing mode is used to transfer data from a
source register to a destination register.

3. Register Addressing Mode …

2. Immediate Addressing Modes …
 Register Indirect Addressing Mode:
• In this the instruction specifies a CPU register where
operand address is found.
• CPU register contains address of operand.

4. Register Indirect Addressing Mode …

 Direct Addressing mode:
• In this mode, address of operand is in instruction
along with opcode.

5. Direct Addressing Mode …

2. Immediate Addressing Modes …
6. Indirect
Addressing
Mode …

• The effective address of operand is at location pointed by content

of memory location pointed by address field of instruction.
6. Indirect
Addressing
Mode …
 7. Auto
Increment - Auto
decrement
addressing:

Pointing register
is automatically
incremented or
decremented
after each use
8. Auto Increment - Auto
decrement addressing:

• Pointing register is
automatically incremented
or decremented after each
use
8. Base Register Addressing:
EA=base register + Address field
9. Relative addressing:
EA=PC+ Address field of instruction
8085 Microprocessor
Introduction
 8085
Microprocessor

Introduction
 8085
Microprocessor

PIN Diagram
8085
microprocessor:

8 bit data bus,

16 bit address
bus
 8085
microprocesso
r:

Power Supply
and
CLK-frequency
 8085
microprocesso
r:

X1 and X2 pins
 8085
microprocessor:

RESET IN and
RESET Out
 8085
microprocessor
:

RESET IN' and R

ESET Out
 8085
microprocessor:

RESET Out
 8085
microprocessor:

SID and SOD

pins
 8085
microprocessor:

SID and SOD

pins
 8085
microprocessor:

SOD and
Maskable
Interrupt
 8085
microprocessor:

SOD and Non-

Maskable
Interrupt
 8085
microprocessor:

Vectored
Interrupt
 8085
microprocessor:

Vectored
Interrupt
 8085
microprocessor:

Non-Vectored
Interrupt
 8085
microprocessor:

Priority of
Interrupts
 8085
microprocessor:

TRAP
Interrupt pin
 8085
microprocessor:

RST 7.5 Interrupt

pin
 8085
microprocessor:

RST 6.5 Interrupt

pin
 8085
microprocessor:

RST 5.5 Interrupt

pin
 8085
microprocessor:

INTR Interrupt
pin
 8085
microprocessor:

INTA' Interrupt
pin
 8085
microprocessor:

Address and
Data
pins
 8085
microprocessor:

AD0 - AD7 pins

 8085
microprocessor:

A8 - A15 pins
 8085
microprocessor:

A8 - A15 pins
 8085
microprocessor:

ALE pin
 8085
microprocessor:

S0 and S1 pin
 8085
microprocessor:

IO/M' pin
 8085
microprocessor:

Operation
identification
 8085
microprocessor:

RD' pin
 8085
microprocessor:

WR' pin
 8085
microprocessor:

READY pin
 8085
microprocessor:

HOLD pin
8085
microprocessor
:

HDLA pin
8085 Microprocessor
De-multiplexing of address and data lines
8085 Microprocessor
De-multiplexing of address and data lines
8085 Microprocessor
De-multiplexing of address and data lines
8085 Microprocessor
De-multiplexing of address and data lines
8085 Microprocessor
Functional block diagram
Functional Block Diagram
8085 Microprocessor
Instruction Set
 8085
microprocessor:

All types
 8085
microprocessor:

Introduction
 8085
microprocessor:

Types
8085
microprocessor:
Data Transfer
Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085 Microprocessor
Data Transfer Instructions
8085
microprocessor:

Arithmetic
Instructions
8085 Microprocessor
Arithmetic Instructions: ADD
8085 Microprocessor
Arithmetic Instructions: SUB
8085 Microprocessor
Arithmetic Instructions: INR/DCR
8085 Microprocessor
Arithmetic Instructions: ADD
8085 Microprocessor
Arithmetic Instructions: ADC
8085 Microprocessor
Arithmetic Instructions: ADI
8085 Microprocessor
Arithmetic Instructions: ACI
8085 Microprocessor
Arithmetic Instructions: DAD
8085 Microprocessor
Arithmetic Instructions: SUB
8085 Microprocessor
Arithmetic Instructions: SBB
8085 Microprocessor
Arithmetic Instructions: SUI
8085 Microprocessor
Arithmetic Instructions: SBI
8085 Microprocessor
Arithmetic Instructions: INR
8085 Microprocessor
Arithmetic Instructions: INX
8085 Microprocessor
Arithmetic Instructions: DCR
8085 Microprocessor
Arithmetic Instructions: DCX
8085
microprocessor
:

Logical
Instructions
8085 Microprocessor
Logical Instructions:
8085 Microprocessor
Logical Instructions:
8085 Microprocessor
Logical Instructions:
8085 Microprocessor
Logical Instructions: CMP
8085 Microprocessor
Logical Instructions: CMP
8085 Microprocessor
Logical Instructions: CMI
8085 Microprocessor
Logical Instructions: CMI
8085 Microprocessor
Logical Instructions: ANA
8085 Microprocessor
Logical Instructions: ANI
8085 Microprocessor
Logical Instructions: XRA
8085 Microprocessor
Logical Instructions: ORA
8085 Microprocessor
Logical Instructions: ORI
8085 Microprocessor
Logical Instructions: XRA
8085 Microprocessor
Logical Instructions: XRI
8085 Microprocessor
Logical Instructions: RLC
8085 Microprocessor
Logical Instructions: RRC
8085 Microprocessor
Logical Instructions: RAL
8085 Microprocessor
Logical Instructions: RAR
8085 Microprocessor
Logical Instructions: CMA
8085 Microprocessor
Logical Instructions: CMC
8085 Microprocessor
Logical Instructions: STC
8085
microprocessor:

Branching
Instructions
8085 Microprocessor
Logical Instructions: JMP
8085 Microprocessor
Logical Instructions: JX
8085 Microprocessor
Logical Instructions: JX
8085 Microprocessor
Logical Instructions: CALL
8085 Microprocessor
Logical Instructions: CX
8085 Microprocessor
Logical Instructions: CX
8085 Microprocessor
Logical Instructions: RET
8085 Microprocessor
Logical Instructions: RX
8085 Microprocessor
Logical Instructions: RX
8085 Microprocessor
Logical Instructions: RST
8085 Microprocessor
Logical Instructions: RST
8085
microprocessor:

Control
Instructions
8085 Microprocessor
Logical Instructions: NOP
8085 Microprocessor
Logical Instructions: HLT
8085 Microprocessor
Logical Instructions: DI
8085 Microprocessor
Logical Instructions: EI
8085 Microprocessor
Logical Instructions: RIM
8085 Microprocessor
Logical Instructions: RIM
8085 Microprocessor
Logical Instructions: SIM
8085 Microprocessor
Logical Instructions: RIM
8085
microprocessor:

Assembly
Language
Programming
8085
microprocessor:

Memory,
Subroutine and
Interrupts
 Stack Pointer

LXI SP, 8000H LXI H, 8000H

LXI H, 1234H SPHL
PUSH H LXI H, 1234H
PUSH H
POP D POP D
HLT HLT
We can Push the content of PSW (Program
Status Word—Accumulator + status register) on
to the stack.
We can pop the content of stack into PSW
we can set the flags as per our requirement
Precaution of using push and pop
1. Push and pop should be used in
opposite order to retain the value
2. There should as many PUSH as POP
(otherwise RET may result in wrong
otcome)
e.g.
PUSH B
PUSH D
---
----
POP D
POP B
Here it is FILO.
Program to clear ALL flags:

LXI SP 5000H
MVI L, 00H
PUSH H
POP PSW /// clear flags
PUSH PSW
POP H
MOV A, L
Out 41H// display at port no 41 (display device connected)
HLT
Subroutine:
A small program written separately from the main program
to perform a particular task.
The task may be repeatedly required in the main program.
Used to avoid the repetition of smaller programs.
Subroutines are written separately and are stored in a
memory location that is different from the main program.
You can call a subroutine multiple times from the main
program using a simple CALL instruction.
Similar to function call of high level language.
CALL address // used to call a subroutine. It is done by
pushing the return address (content of PC) onto stack
RET // used to return from subroutine by POPing the
Stack Pointer into PC
It is advisable to initialise SP before using CALL
RET Instruction:
Implementing Call by Value and Call
by reference
Write a program to display FF and 11 repeatedly on seven segment
display. Write a delay subroutine and call it.

LXI SP FFFFH
Start: MVI A FFH
OUT 00H
CALL Delay
MVI A, 11
OUT 00H
CALL Delay
JUMP Start

Delay: MVI B FFH // subroutine starts here, B is outer loop counter

Outer: MVI C FF// set inner loop counter
Inner: DCR C
JNZ Inner
DCR B
JNZ outer // total count of 256*256 is done?
RET // return to calling function (main program)
Interrupt of 8085

https://www.slideshare.net/grambabu77/8085
-interrupts-50457972
E E’
Basic IO interfacing

For peripheral:
IO/M’=1

For memory:
IO/M’=0

Including
IO/M’and
WR’and RD’
total 4 control
signals can be
generated.
Interrupts in 8085