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Verilog Code for AND Gate - All modeling styles

The document outlines the design of an AND logic gate using three modeling styles: Gate Level, Dataflow, and Behavioral modeling in Verilog. It provides detailed explanations, code examples, and truth tables for each modeling approach, highlighting the differences in complexity and abstraction levels. Additionally, it includes a testbench and simulation waveform to demonstrate the functionality of the AND gate.

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thambigan
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32 views

Verilog Code for AND Gate - All modeling styles

The document outlines the design of an AND logic gate using three modeling styles: Gate Level, Dataflow, and Behavioral modeling in Verilog. It provides detailed explanations, code examples, and truth tables for each modeling approach, highlighting the differences in complexity and abstraction levels. Additionally, it includes a testbench and simulation waveform to demonstrate the functionality of the AND gate.

Uploaded by

thambigan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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In this post, we will design the AND logic gate using all the three modeling styles in

Level, Dataflow, and Behavioral modeling. Notice the different approaches in the dif
end result (an AND gate). Let’s dive right in.

Contents
Gate Level modeling
Logic Circuit of the AND gate
Verilog code for AND gate using gate-level modeling
Data flow modeling
Equation of the AND gate
Verilog code for AND gate using data-flow modeling
Behavioral Modelling
AND gate’s truth table
Verilog code for AND gate using behavioral modeling
RTL schematic of the AND gate
Testbench of the AND gate using Verilog
Simulation Waveform

Gate Level modeling


We can design a logic circuit using basic logic gates with Gate level modeling. Verilo
using basic logic gates as predefined primitives. These primitives are instantiated lik
are predefined in Verilog and do not need a module definition.
module AND_2(output Y, input A, B);

We start by declaring the module. module, a basic building block in Verilog HDL is a
the module’s name. The module command tells the compiler that we are creating so
inputs and outputs. AND_2 is the identifier. Identifiers are how we name the module
the port list containing input and output ports (You can read more about module dec
write:

and(Y, A, B);
endmodule;
module AND_2(output Y, input A, B);
and(Y, A, B);
endmodule

Data flow modeling


Compared to gate-level modeling, dataflow modeling in Verilog is a higher level of a
is, you don’t really need to know the circuit design. That’s really helpful because gat
very complicated for a complex circuit.

Hence dataflow modeling is a very important way of implementing the design. All yo
boolean logic equation of the output of the circuit in terms of its inputs. We use cont
dataflow modeling in most of the designs. The continuous assignments are made us
Y ’ll h it k i bit
module AND_2_data_flow (output Y, input A, B);

Then we use assignment statements in data flow modeling. Using

assign Y = A & B;
endmodule

Just like the and operation, the & logical operator performs a binary multiplication of
Then endmodule is used to terminate the module.

Behavioral Modelling
Behavioral modeling is the highest level of abstraction in the Verilog HDL. All that a
algorithm of the design, which is the basic information for any design. This level sim
circuits; the details are not specified. That’s helpful because the designer does not h
complicated circuitry or equations. Just a simple truth table would suffice.

AND gate’s truth table


A B Y(A and B)

0 0 0

0 1 0

1 0 0

1 1 1

Equation from the truth table

Simply by minimization, (or you may arrive by k-maps), we can state that:

Y = A.B or say Y = A & B.

V il d f AND t i b h i l d l
Using the always statement, a procedural statement in Verilog, we run the program
known as the sensitivity list or the trigger list. The sensitivity list includes all input sig
the always block. It controls when the statements in the always block are to be eva
syntax, used before the sensitivity list. In Verilog, begin embarks and end conclude
more than one statement in it.

Note that the always statement always @(Y, A) could be written as always @ *.
itself has to decide on the input signals of the sensitivity list. Now, we have,

always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end

The condition for AND gate is that if both the inputs are high, then the output is also
condition that has to be low.

if (A == 1'b1 & B == 1'b1) states that if both A and B are 1, then Y has to be 1,

Here is the full code:

module AND_2_behavioral (output reg Y, input A, B);


always @ (A or B) begin
if (A == 1'b1 & B == 1'b1) begin
Y = 1'b1;
end
else
Y = 1'b0;
end
endmodule
`include "AND_2_behavioral.v"
module AND_2_behavioral_tb;
reg A, B;
wire Y;
AND_2_behavioral Indtance0 (Y, A, B);
initial begin
A = 0; B = 0;
#1 A = 0; B = 1;
#1 A = 1; B = 0;
#1 A = 1; B = 1;
end
initial begin
$monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

Simulation Waveform

Correctly depicting that whenever both the inputs are high, the output is also high el

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