HDL Lecture5

Hardware Description
Languages
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2014 Synopsys, Inc. All rights reserved.
Hardware Description Languages
Lecture - 5
1 Developed By: Vazgen Melikyan
Course Overview
 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

Lecture - 5
Developed By: Vazgen Melikyan
2
VHDL

Lecture - 5
3 Developed By: Vazgen Melikyan
Reasons for Using VHDL
 VHDL is an international IEEE standard specification

language (IEEE 1076-1993) for describing digital
hardware used by industry worldwide.
 VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit)
Hardware Description Language.
 VHDL enables hardware modeling from the gate to
system level.
 VHDL provides a mechanism for digital design and
reusable design documentation.

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History of VHDL
 Very High Speed Integrated Circuit (VHSIC) Program

 Launched in 1980
 Aggressive effort to advance state of the art
 Object was to achieve significant gains in VLSI technology
 Need for common descriptive language
 $17 Million for direct VHDL development
 $16 Million for VHDL design tools
 Woods Hole Workshop
 Held in June 1981 in Massachusetts
 Discussion of VHSIC goals
 Comprised of members of industry, government, and academia
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5
History of VHDL (2)
 In July 1983, a team of Intermetrics, IBM and Texas

Instruments were awarded a contract to develop VHDL.
 In August 1985, the final version of the language under
government contract was released: VHDL Version 7.2.
 In December 1987, VHDL became IEEE Standard 1076-
1987 and in 1988 an ANSI standard.
 In September 1993, VHDL was restandardized to clarify
and enhance the language.
 VHDL has been accepted as a Draft International
Standard by the IEC.
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Gajski and Kuhn’s Y Chart
Architectural Structural
Behavioral
Algorithmic
Processor
Systems Functional Block
Hardware Modules
Algorithms Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transfer Functions Transistors
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Physical/Geometry
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Additional Benefits of VHDL
 Allows various design methodologies

 Provides technology independence
 Describes a wide variety of digital hardware
 Eases communication through standard language
 Allows for better design management
 Provides a flexible design language
 Has given rise to derivative standards
 WAVES, VITAL, Analog VHDL

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VHDL Design Example
 Problem: Design a single bit half adder with

carry and enable
 Specifications
 Inputs and outputs are each one bit
 When enable is high, result gets x plus y
 When enable is high, carry gets any carry of x plus y
 Outputs are zero when enable input is low
x
carry
y Half Adder
result
enable
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VHDL Design Example: Entity
Declaration
 As a first step, the entity declaration
describes the interface of the component
 Input and output ports are declared
ENTITY half_adder IS
PORT( x, y, enable: IN BIT;

carry, result: OUT BIT);
END half_adder;
x
Half carry
y
Adder result
enable
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10
Specifications
 Behavioral
 Data Flow
 Structural

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11
VHDL Design Example: Behavioral
Specification
 A high level description can be used to describe the function of the
adder
ARCHITECTURE half_adder_a OF half_adder IS
ARCHITECTURE half_adder_a OF half_adder IS
BEGIN
BEGIN
PROCESS (x, y, enable)
PROCESS (x, y, enable)
BEGIN
BEGIN
IF enable = ‘1’ THEN
IF enable = ‘1’ THEN
result <= x XOR y;
result <= x XOR y;
carry <= x AND y;
carry <= x AND y;
ELSE
ELSE
carry <= ‘0’;
carry <= ‘0’;
result <= ‘0’;
result <= ‘0’;
END IF;
END IF;
END PROCESS;
END PROCESS;
END half_adder_a;
END half_adder_a;
 The model can then be simulated to verify correct functionality of the

component
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12
VHDL Design Example: Data Flow
Specification
 A second method is to use logic equations to
develop a data flow description
ARCHITECTURE
ARCHITECTURE half_adder_b
half_adder_b OF OF half_adder
half_adder IS IS
BEGIN
BEGIN
carry
carry <=
<= enable
enable AND
AND (x
(x AND
AND y);
y);
result
result <=
<= enable
enable AND
AND (x
(x XOR
XOR y);
y);
END half_adder_b;
END half_adder_b;
 Again, the model can be simulated at this

level to confirm the logic equations
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13
VHDL Design Example: Structural
Specification
 As a third method, a structural description can be created from
predescribed components
x
y carry
enable
result
 These gates can be pulled from a library of parts

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14
Specification (2)
ARCHITECTURE half_adder_c OF half_adder IS
ARCHITECTURE half_adder_c OF half_adder IS
COMPONENT and2
COMPONENT and2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
out0 : OUT BIT);
END COMPONENT;
END COMPONENT;
COMPONENT and3
COMPONENT and3
PORT (in0, in1, in2 : IN BIT;
PORT (in0, in1, in2 : IN BIT;
out0 : OUT BIT);
out0 : OUT BIT);
END COMPONENT;
END COMPONENT;
COMPONENT xor2
COMPONENT xor2
out0 : OUT BIT);
out0 : OUT BIT);
END COMPONENT;
END COMPONENT;
FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
-- description is continued on next slide
-- description is continued on next slide

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15
Specification (3)
--
-- continuing
continuing half_adder_c
half_adder_c description
description
SIGNAL
SIGNAL xor_res
xor_res :: BIT;
BIT; --
-- internal
internal signal
signal
--
-- Note
Note that
that other
other signals
signals are
are already
already declared
declared inin entity
entity
BEGIN
BEGIN
A0
A0 :: and2
and2 PORT
PORT MAP
MAP (enable,
(enable, xor_res,
xor_res, result);
result);
A1 : and3 PORT MAP (x, y, enable,
A1 : and3 PORT MAP (x, y, enable, carry);carry);
X0
X0 :: xor2
xor2 PORT
PORT MAP
MAP (x,
(x, y,
y, xor_res);
xor_res);
END
END half_adder_c;
half_adder_c;

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VHDL Model Components
 Entity
 Defines a component’s interface
 Architecture
 Defines a component’s function
 Alternative architectures

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VHDL Component Descriptions
 Structural
 Behavioral
 Timing and delay

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VHDL Model Component Behavior
Description
 Process - fundamental unit for component behavior
description
 Processes may be explicitly or implicitly defined and are
packaged in architectures
 Signal - primary communication mechanism
 Process executions result in new values being assigned to
signals which are then accessible to other processes
 Similarly, a signal may be accessed by a process in another
architecture by connecting the signal to ports in the entities
associated with the two architectures
Output
Output <=
<= My_id
My_id ++ 10;
10;
Example signal assignment statement :
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Entity Declarations
 The primary purpose of the entity is to declare the signals in the

component’s interface
 The interface signals are listed in the PORT clause
 In this respect, the entity is akin to the schematic symbol for the component
x
Half carry
y result
Adder
enable
ENTITY
ENTITY half_adder
half_adder IS
IS
GENERIC(prop_delay
GENERIC(prop_delay :: TIME
TIME :=
:= 10
10 ns);
ns);
PORT(
PORT( x,
x, y, enable
enable:::OUT
y,result IN
IN BIT;
BIT;
carry,
carry, result : OUT BIT);
BIT);
END
END half_adder;
half_adder;

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Entity Declarations: Port Clause
 PORT clause declares the interface signals of the object

to the outside world
 Three parts of the PORT clause
 Name
 Mode PORT
PORT (signal_name
(signal_name :: mode
mode data_type);
data_type);
 Data type
 Example PORT clause:
PORT
PORT (( input
input :: IN
IN BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0);
0);
ready,
ready, output
output :: OUT
OUT BIT
BIT );
);
 Port signals (i.e. ‘ports’) of the same mode and type or subtype may be
declared on the same line

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Entity Declarations: Port Clause (2)
 The port mode of the interface describes the direction in which data
travels with respect to the component
 Port modes
 In
 Data comes in this port and can only be read
 Out
 Data travels out this port
 Buffer
 Data may travel in either direction, but only one signal driver may be on at any one time
 Inout
 Data may travel in either direction with any number of active drivers allowed; requires a
Bus Resolution Function
 Linkage
 Direction of data flow is unknown

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Entity Declarations: Generic Clause
 Generics may be used for readability, maintenance and

configuration
 Generic clause syntax:
GENERIC
GENERIC (generic_name
(generic_name :: type
type [:=
[:=
default_value/]);
default_value/]);
 If optional default_value is missing in generic clause declaration, it must be
present when component is to be used (i.e. instantiated)
 Generic clause example:
GENERIC
GENERIC (My_ID
(My_ID :: INTEGER
INTEGER :=
:= 37);
37);
 The generic My_ID, with a default value of 37, can be referenced by any
architecture of the entity with this generic clause
 The default can be overridden at component instantiation

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Architecture Bodies
 Describe the operation of the component

 Consist of two parts:
 Declarative part - includes necessary declarations
 For example, type declarations, signal declarations, component declarations,
subprogram declarations
 Statement part - includes statements that describe organization and/or functional
operation of component
 For example, concurrent signal assignment statements, process statements, component
instantiation statements
ARCHITECTURE half_adder_d OF half_adder IS

ARCHITECTURE half_adder_d OF half_adder IS
SIGNAL xor_res : BIT; -- architecture declarative part
SIGNAL xor_res : BIT; -- architecture declarative part
BEGIN -- begins architecture statement part
BEGIN -- begins architecture statement part
carry <= enable AND (x AND y);
carry <= enable AND (x AND y);
result <= enable AND xor_res;
result <= enable AND xor_res;
xor_res <= x XOR y;
xor_res <= x XOR y;
END half_adder_d;
END half_adder_d;
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Structural Descriptions
 Pre-defined VHDL components are instantiated and

connected together
 Structural descriptions may connect simple gates or
complex, abstract components
 VHDL provides mechanisms to support hierarchical
description
 VHDL provides mechanisms to describe highly repetitive
structures easily
Input Behavioral Output
Entity

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Behavioral Descriptions
 VHDL provides two styles of describing component

behavior
 Data Flow: concurrent signal assignment statements
 Behavioral: processes used to describe complex behavior by
means of high-level language constructs
 Variables, loops, if-then-else statements
 A behavioral model may bear little resemblance to
system implementation
 Structure not necessarily implied
Input Behavioral Output
Description

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Timing Model
 VHDL uses the following simulation cycle to model the

stimulus and response nature of digital hardware
Start
StartSimulation
Simulation
Delay
Update
UpdateSignals
Signals Execute
ExecuteProcesses
Processes
End
EndSimulation
Simulation
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Delay Types
 All VHDL signal assignment statements prescribe an amount of time

that must transpire before the signal assumes its new value
 Delay forms
 Transport
 Prescribes propagation delay only
 Inertial
 Prescribes propagation delay and minimum input pulse width
 Delta
 The default if no delay time is explicitly specified
Input Output
delay

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Transport Delay
 Transport delay must be explicitly specified

 I.e. keyword “TRANSPORT” must be used
 Signal assumes its new value after specified delay
--
-- TRANSPORT
TRANSPORT delay
delay example
example
Output
Output <= TRANSPORT NOT
<= TRANSPORT NOT Input
Input AFTER
AFTER 10
10 ns;
ns;
Input Output
Input
Output
0 5 10 15 20 25 30 35
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29
Inertial Delay
 Provides specification propagation delay and input pulse width, i.e.

‘inertia’ of output:
target
target <=
<= [REJECT
[REJECT time_expression]
time_expression] INERTIAL
INERTIAL waveform;
waveform;
 Inertial delay is default and REJECT is optional:
Output
Output <=
<= NOT
NOT Input
Input AFTER
AFTER 10
10 ns;
ns;
--
-- Propagation delay and minimum pulse
Propagation delay and minimum pulse width
width are
are 10ns
10ns
Input
Input Output
Output
0 5 10 15 20 25 30 35
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30
Inertial Delay (2)
 Example of gate with ‘inertia’ smaller than propagation delay

 Inverter with propagation delay of 10ns which suppresses pulses shorter
than 5ns
Output
Output <=
<= REJECT
REJECT 5ns
5ns INERTIAL
INERTIAL NOT
NOT Input
Input AFTER
AFTER 10ns;
10ns;
Input
Output
0 5 10 15 20 25 30 35
 The REJECT feature is new to VHDL 1076-1993
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31
Delta Delay
 Default signal assignment propagation delay if no delay

is explicitly prescribed
 VHDL signal assignments do not take place immediately
 Delta is an infinite simulation time unit so that all signal
assignments can result in signals assuming their values at a
future time
 E.g. Output
Output <=<= NOT
NOT Input;
Input;
--
-- Output
Output assumes
assumes new
new value
value in
in one
one delta
delta cycle
cycle
 Supports a model of concurrent VHDL process execution

 Order in which processes are executed by simulator does not
affect simulation output
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Delta Delay: An Example without
Delta Delay
 The behavior of C
A
IN: 1->0
C
B
1
NAND AND
ANDgate
gateevaluated
evaluatedfirst:
NANDgate
gateevaluated
evaluatedfirst:
first: first:
IN: IN: 1->0
IN:1->0
1->0 IN: 1->0
A: A:
A: 0->1
A: 0->1
0->1 0->1
B: C:C: 0->1
B: 1->0
1->0 0->1
C: B:
B: 1->0
C: 0->0
0->0 1->0
C:
C: 1->0
1->0

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Delta Delay: An Example without
Delta Delay (2)
IN: 1->0 A
 The behavior of C C
B
1
Using delta delay scheduling
Time Delta Event
0 ns 1 IN: 1->0
eval INVERTER
2 A: 0->1
eval NAND, AND

B: 1->0
3
C: 0->1
eval AND
4 C: 1->0
1 ns

Lecture - 5
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Data Types
 All declarations of VHDL ports, signals, and variables must specify

their corresponding type or subtype
 Types
 Access
 Scalar
 Integer
 Real
 Enumerated
 Physical
 Composite
 Array
 Record

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VHDL Data Types: Scalar Types
 Integer
 Minimum range for any implementation as defined by standard:
- 2,147,483,647 to 2,147,483,647
 Example assignments to a variable of type integer:
ARCHITECTURE
ARCHITECTURE test_int
test_int OFOF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)(X)
VARIABLE
VARIABLE a:a: INTEGER;
INTEGER;
BEGIN
BEGIN
aa :=
:= 1;
1; --
-- OK
OK
aa :=
:= -1; -- OK
-1; -- OK
aa :=
:= 1.0;
1.0; ---- illegal
illegal
END PROCESS;
END PROCESS;
END test_int;
END test_int;
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VHDL Data Types: Scalar Types (2)
 Real
 Minimum range for any implementation as defined by standard: -1.0E38
to 1.0E38
 Example assignments to a variable of type real :
ARCHITECTURE
ARCHITECTURE test_real
test_real OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a: a: REAL;
REAL;
BEGIN
BEGIN
aa :=
:= 1.3;
1.3; ---- OKOK
aa :=
:= -7.5; -- OK
-7.5; -- OK
aa := 1; -- illegal
:= 1; -- illegal
aa :=
:= 1.7E13;
1.7E13; -- -- OK
OK
aa := 5.3 ns; -- illegal
:= 5.3 ns; -- illegal
END PROCESS;
END PROCESS;
END test_real;
END test_real;

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 Enumerated
 User specifies list of possible values
 Example declaration and usage of enumerated data type:
TYPE
TYPE binary
binary IS IS (( ON,
ON, OFF
OFF );
);
... some statements
... some statements ... ...
ARCHITECTURE
ARCHITECTURE test_enum
test_enum OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)(X)
VARIABLE
VARIABLE a: a: binary;
binary;
BEGIN
BEGIN
aa :=
:= ON;
ON; -- -- OK
OK
...
... more statements ...
more statements ...
aa := OFF; --
:= OFF; -- OK OK
...
... more
more statements
statements ......
END PROCESS;
END PROCESS;
END test_enum;
END test_enum;

Lecture - 5
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 Physical
 Requires associated units
 Range must be specified
 Example of physical type declaration:
TYPE
TYPE resistance
resistance IS
IS RANGE
RANGE 00 TO
TO 10000000
10000000
UNITS
UNITS
ohm;
ohm; ---- ohm
ohm
Kohm
Kohm = 1000 ohm;
= 1000 ohm; --
-- i.e.
i.e. 11 K
K
Mohm
Mohm == 1000
1000 kohm;
kohm; --
-- i.e.
i.e. 11 M
M
END UNITS;
END UNITS;
Time is the only physical type predefined in VHDL standard

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VHDL Data Types: Composite Types
 Array
 Used to group elements of the same type into a single VHDL object
 Range may be unconstrained in declaration
 Range would then be constrained when array is used
 Example declaration for 1D array (vector):
TYPE
TYPE data_bus
data_bus IS
IS ARRAY(0
ARRAY(0 TO
TO 31)
31) OF
OF BIT;
BIT;
0 ...element indices... 31
0 ...array values... 1
VARIABLE
VARIABLE XX :: data_bus;
data_bus;
VARIABLE Y : BIT;
VARIABLE Y : BIT;
YY :=
:= X(12);
X(12); --
-- YY gets
gets value
value of
of element
element at
at index
index 12
12

Lecture - 5
40
VHDL Data Types: Composite Types (2)
 Example of 1D array using DOWNTO :

TYPE
TYPE reg_type
reg_type IS
IS ARRAY(15
ARRAY(15 DOWNTO
DOWNTO 0)
0) OF
OF BIT;
BIT;
15 0
...element indices...
0 1
...array values...
VARIABLE
VARIABLE XX :: reg_type;
reg_type;
VARIABLE
VARIABLE YY :: BIT;
BIT;
YY :=
:= X(4);
X(4); --
-- YY gets
gets value
value of
of element
element at
at index
index 44
 DOWNTO keyword must be used if leftmost index is greater than rightmost index
 e.g. ‘Big-Endian’ bit ordering

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VHDL Data Types: Composite Types (3)
 Records
 Used to group elements of possibly different types into a single VHDL object
 Elements are indexed via field names
 Examples of record declaration and usage :
TYPE
TYPE binary
binary IS
IS (( ON,
ON, OFF
OFF );
);
TYPE switch_info
TYPE switch_info IS IS
RECORD
RECORD
status
status :: BINARY;
BINARY;
IDnumber
IDnumber :: INTEGER;
INTEGER;
END
END RECORD;
RECORD;
VARIABLE
VARIABLE switch
switch :: switch_info;
switch_info;
switch.status
switch.status := ON; --
:= ON; -- status
status of
of the
the switch
switch
switch.IDnumber
switch.IDnumber :=:= 30;
30; --
-- e.g.
e.g. number
number ofof the
the switch
switch

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VHDL Data Types: Access Type
 Access
 Analogous to pointers in other languages
 Allows dynamic allocation of storage
 Useful for implementing queues, fifos, etc.

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VHDL Data Types: Subtypes
 Subtype
 Allows user defined constraints on a data type
 e.g. a subtype based on an unconstrained VHDL type
 May include entire range of base type
 Assignments that are out of the subtype range are illegal
 Range violation detected at run time rather than compile time
because only base type is checked at compile time
 Subtype declaration syntax:
SUBTYPE
SUBTYPE name
name IS
IS base_type
base_type RANGE
RANGE <user
<user range>;
range>;
 Subtype example:
SUBTYPE
SUBTYPE first_ten
first_ten IS
IS INTEGER
INTEGER RANGE
RANGE 00 TO
TO 9;
9;

Lecture - 5
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VHDL Data Types: Summary
 All declarations of VHDL ports, signals, and variables

must include their associated type or subtype
 Three forms of VHDL data types
 Access - pointers for dynamic storage allocation
 Scalar - includes Integer, Real, Enumerated, and Physical
 Composite - includes Array, and Record
 A set of built-in data types are defined in VHDL standard
 User can also define own data types and subtypes

Lecture - 5
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VHDL Objects
 Object types
 Constants
 Variables
 Signals
 Files

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46
VHDL Objects (2)
 The scope of an object

 Objects declared in a package are available to all
VHDL descriptions that use that package
 Objects declared in an entity are available to all
architectures associated with that entity
 Objects declared in an architecture are available to all
statements in that architecture
 Objects declared in a process are available only within
that process

Lecture - 5
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VHDL Objects: Constants
 Name assigned to a specific value of a type

 Allow easy update and readability
 Declaration of constant may omit value so that the value
assignment may be deferred
 Facilitates reconfiguration
 Declaration syntax:
CONSTANT
CONSTANT constant_name
constant_name :: type_name
type_name [:=
[:= value];
value];
 Declaration examples:
CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT SPEED : INTEGER;
CONSTANT SPEED : INTEGER;

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48
VHDL Objects: Variables
 Provide convenient mechanism for local storage

 e.g. loop counters, intermediate values
 Scope is the process in which they are declared
 VHDL ‘93 provides global variables
 All variable assignments take place immediately
 No delta or user specified delay is incurred
VARIABLE
VARIABLE variable_name
variable_name :: type_name
type_name [:=
[:= value];
value];
 Declaration examples:
VARIABLE
VARIABLE opcode
opcode :: BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0)
0) :=
:= "0000";
"0000";
VARIABLE freq : INTEGER;
VARIABLE freq : INTEGER;

Lecture - 5
49
VHDL Objects: Signals
 Used for communication between VHDL components

 Real, physical signals in system often mapped to VHDL
signals
 ALL VHDL signal assignments require either delta cycle
or user-specified delay before new value is assumed
SIGNAL
SIGNAL signal_name
signal_name :: type_name
type_name [:=
[:= value];
value];
 Declaration and assignment examples:
SIGNAL
SIGNAL brdy
brdy :: BIT;
BIT;
brdy
brdy <= ‘0’ AFTER 5ns,
<= ‘0’ AFTER 5ns, ‘1’
‘1’ AFTER
AFTER 10ns;
10ns;
Lecture - 5
50
Signals and Variables
 This example highlights the difference between

signals and variables
ARCHITECTURE
ARCHITECTURE test1
test1 OFOF mux
mux IS
IS ARCHITECTURE
ARCHITECTURE test2
test2 OF
OF mux
mux IS
IS
SIGNAL x : BIT :=
SIGNAL x : BIT := '1'; '1'; SIGNAL y : BIT :=
SIGNAL y : BIT := '0';'0';
SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0'; BEGIN
BEGIN
BEGIN
BEGIN PROCESS
PROCESS (in_sig,
(in_sig, y)
y)
PROCESS
PROCESS (in_sig,
(in_sig, x,x, y)
y) VARIABLE
VARIABLE x : BIT :=
x : BIT := '1';
'1';
BEGIN
BEGIN BEGIN
BEGIN
xx <=
<= in_sig
in_sig XOR
XOR y;
y; xx :=
:= in_sig
in_sig XOR
XOR y;
y;
yy <= in_sig XOR
<= in_sig XOR x; x; yy <= in_sig XOR
<= in_sig XOR x;x;
END
END PROCESS;
PROCESS; END
END PROCESS;
PROCESS;
END test1;
END test1; END test2;
END test2;

Lecture - 5
51
VHDL Objects: Signals vs. Variables
 A key difference between variables and signals is the assignment

delay
ARCHITECTURE
ARCHITECTURE sig_ex
sig_ex OFOF test
test IS
IS
PROCESS (a, b, c, out_1)
PROCESS (a, b, c, out_1)
BEGIN
BEGIN
out_1
out_1 <=
<= aa NAND
NAND b;
b;
out_2
out_2 <= out_1 XOR c;
<= out_1 XOR c;
END PROCESS;
END PROCESS;
END sig_ex;
END sig_ex;
Time a b c out_1 out_2
0 0 1 1 1 0
1 1 1 1 1 0
1+d 1 1 1 0 0
1+2d 1 1 1 0 1

Lecture - 5
52
VHDL Objects: Signals vs. Variables (2)
ARCHITECTURE
ARCHITECTURE var_ex
var_ex OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (a,
(a, b,b, c)
c)
VARIABLE
VARIABLE out_3
out_3 :: BIT;
BIT;
BEGIN
BEGIN
out_3
out_3 :=
:= aa NAND
NAND b;b;
out_4
out_4 <=
<= out_3
out_3 XOR
XOR c;c;
END
END PROCESS;
PROCESS;
END
END var_ex;
var_ex;
Time a b c out_3 out_4
0 0 1 1 1 0
1 1 1 1 0 0
1+d 1 1 1 0 1

Lecture - 5
53
VHDL Objects: Files
 Files provide a way for a VHDL design to communicate with the host
environment
 File declarations make a file available for use to a design
 Files can be opened for reading and writing
 In VHDL87, files are opened and closed when their associated objects
come into and out of scope
 In VHDL93 explicit FILE_OPEN() and FILE_CLOSE() procedures were
added
 The package STANDARD defines basic file I/O routines for VHDL
types
 The package TEXTIO defines more powerful routines handling I/O
of text files

Lecture - 5
54
Simulation Cycle Revisited:
Sequential vs. Concurrent Statements
 VHDL is inherently a concurrent language
 All VHDL processes execute concurrently
 Concurrent signal assignment statements are actually one-line
processes
 VHDL statements execute sequentially within a process
 Concurrent processes with sequential execution within a
process offers maximum flexibility
 Supports various levels of abstraction
 Supports modeling of concurrent and sequential events as
observed in real systems

Lecture - 5
55
Concurrent Statements
 Basic granularity of concurrency is the process

 Processes are executed concurrently
 Concurrent signal assignment statements are one-line processes
 Mechanism to achieve concurrency
 Processes communicate with each other via signals
 Signal assignments require delay before new value is assumed
 Simulation time advances when all active processes complete
 Effect is concurrent processing
 i.e. order in which processes are actually executed by simulator does not
affect behavior
 Concurrent VHDL statements
 Block, process, assert, signal assignment, procedure call, component
instantiation
Lecture - 5
56
Sequential Statements
 Statements inside a process are executed sequentially

ARCHITECTURE
ARCHITECTURE sequential
sequential OF
OF test_mux
test_mux IS
IS
BEGIN
BEGIN
select_proc
select_proc :: PROCESS
PROCESS (x,y)
(x,y)
BEGIN
BEGIN
IF
IF (select_sig
(select_sig == '0')
'0') THEN
THEN
zz <= x;
<= x;
ELSIF
ELSIF (select_sig == '1')
(select_sig '1') THEN
THEN
zz <= y;
<= y;
ELSE
ELSE
zz <=
<= "XXXX";
"XXXX";
END IF;
END IF;
END
END PROCESS
PROCESS select_proc;
select_proc;
END sequential;
END sequential;

Lecture - 5
57
Packages and Libraries
 User defined constructs declared inside architectures

and entities are not visible to other VHDL components
 Scope of subprograms, user defined data types, constants, and
signals is limited to the VHDL components in which they are
declared
 Packages and libraries provide the ability to reuse
constructs in multiple entities and architectures
 Items declared in packages can be used (i.e. included) in other
VHDL components

Lecture - 5
58
Packages
 Packages consist of two parts

 Package declaration - declarations of objects defined in the package
 Package body - necessary definitions for certain objects in package declaration
 e.g. subprogram descriptions
 Examples of VHDL items included in packages
 Basic declarations
 Types, subtypes
 Constants
 Subprograms
 Use clause
 Signal declarations
 Attribute declarations
 Component declarations

Lecture - 5
59
Packages: Declaration
 An example of a package declaration

PACKAGE
PACKAGE my_stuff
my_stuff ISIS
TYPE
TYPE binary IS (( ON,
binary IS ON, OFF
OFF );
);
CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT My_ID : INTEGER;
CONSTANT My_ID : INTEGER;
PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,
b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result, temp_carry : OUT
temp_result, temp_carry : OUT BIT);
BIT);
END my_stuff;
END my_stuff;
 Some items only require declaration while others need further detail
provided in subsequent package body
 For type and subtype definitions, declaration is sufficient
 Ssubprograms require declarations and descriptions

Lecture - 5
60
Packages: Package Body
 The package body includes the necessary functional

descriptions needed for objects declared in the package
declaration
 e.g. subprogram descriptions, assignments to constants
PACKAGE
PACKAGE BODY
BODY my_stuff
my_stuff IS
IS
CONSTANT
CONSTANT My_ID
My_ID :: INTEGER
INTEGER :=
:= 2;
2;
PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result, temp_carry : OUT BIT)
temp_result, temp_carry : OUT BIT) IS
IS
BEGIN
BEGIN -- this function can return a
-- this function can return a carry carry
temp_result
temp_result <=
<= (a
(a XOR
XOR b)
b) AND
AND en;
en;
temp_carry <= a AND b AND
temp_carry <= a AND b AND en; en;
END add_bits3;
END add_bits3;
END my_stuff;
END my_stuff;
Lecture - 5
61
Packages: Use Clause
 Packages must be made visible before their contents can be used

 The USE clause makes packages visible to entities, architectures, and
other packages
-- use only the binary and add_bits3
declarations
USE my_stuff.binary, my_stuff.add_bits3;
... ENTITY declaration...

... ARCHITECTURE declaration ...
-- use all of the declarations in package

my_stuff
USE my_stuff.ALL;
... ENTITY declaration...

... ARCHITECTURE declaration ...

Lecture - 5
62
Libraries
 Analogous to directories of files

 VHDL libraries contain analyzed (i.e. compiled) VHDL entities,
architectures, and packages
 Facilitate administration of configuration and revision
control
 Libraries of previous designs
 Libraries accessed via an assigned logical name
 Current design unit is compiled into the Work library
 Both work and STD libraries are always available
 Many other libraries usually supplied by VHDL simulator vendor
 Proprietary libraries and IEEE standard libraries
Lecture - 5
63
Attributes
 Attributes provide information about certain items in VHDL

 Types, subtypes, procedures, functions, signals, variables, constants,
entities, architectures, configurations, packages, components
 General form of attribute use:
name'attribute_identifier
name'attribute_identifier --
-- read
read as
as “tick”
“tick”
 VHDL has several predefined attributes:
 X'EVENT - TRUE when there is an event on signal X
 X'LAST_VALUE - returns the previous value of signal X
 Y'HIGH - returns the highest value in the range of Y
 X'STABLE(t) - TRUE when no event has occurred on signal X in the past
‘t’ time

Lecture - 5
64
Attributes: Register Example
 The following example shows how attributes can be used to make an 8-bit
register
 Specifications
 Triggers on rising clock edge
 Latches only on enable high
 Has a data setup time of x_setup
 Has propagation delay of prop_delay
ENTITY 8_bit_reg IS
GENERIC (x_setup, prop_delay : TIME);
PORT(enable, clk : IN qsim_state;
a : IN qsim_state_vector(7 DOWNTO 0);
b : OUT qsim_state_vector(7 DOWNTO 0));
END 8_bit_reg;
 qsim_state type is being used - includes logic values 0, 1, X, and Z
Lecture - 5
65
Attributes: Register Example (2)
 The following architecture is a first attempt at the register

 The use of 'STABLE is used to detect setup violations in
the data input
ARCHITECTURE first_attempt OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable = '1') AND a'STABLE(x_setup) AND
(clk = '1') THEN
b <= a AFTER prop_delay;
END IF;
END PROCESS;
END first_attempt;

Lecture - 5
66
Attributes: Register Example (3)
 The following architecture is a second and more robust attempt

 The use of 'LAST_VALUE ensures the clock is rising from a value of ‘0’
ARCHITECTURE
ARCHITECTURE behavior
behavior OFOF 8_bit_reg
8_bit_reg IS IS
BEGIN
BEGIN
PROCESS
PROCESS (clk)
(clk)
BEGIN
BEGIN
IF
IF (enable
(enable == '1')
'1') AND
AND a'STABLE(x_setup)
a'STABLE(x_setup) AND AND
(clk
(clk == '1')
'1') AND
AND (clk'LAST_VALUE
(clk'LAST_VALUE == '0')
'0') THEN
THEN
bb <=
<= aa AFTER
AFTER delay;
delay;
END
END IF;
IF;
END
END PROCESS;
PROCESS;
END
END behavior;
behavior;
 An ELSE clause could be added to define the behavior when the requirements are
not met

Lecture - 5
67
Operators
 Operators can be chained to form complex expressions:

res
res <=
<= aa AND
AND NOT(B)
NOT(B) OR
OR NOT(a)
NOT(a) AND
AND b;b;
 Can use parentheses for readability and control the association of
operators and operands

 Defined precedence levels in decreasing order:
 Miscellaneous operators -- **, abs, not
 Multiplication operators -- *, /, mod, rem
 Sign operator -- +, -
 Addition operators -- +, -, &
 Shift operators -- sll, srl, sla, sra, rol, ror
 Relational operators -- =, /=, <, <=, >, >=
 Logical operators -- AND, OR, NAND, NOR, XOR, XNOR
Lecture - 5
68
Operators: Examples
 The concatenation operator &

VARIABLE
VARIABLE shifted,
shifted, shiftin
shiftin :: BIT_VECTOR(0
BIT_VECTOR(0 TO
TO 3);
3);
...
...
shifted
shifted :=
:= shiftin(1
shiftin(1 TO
TO 3)
3) && '0‘;
'0‘;
0 1 2 3
SHIFTIN 1 0 0 1
SHIFTED 0 0 1 0
 The exponentiation operator **
x := 5**5 -- 5^5, OK
x := 5**5 -- 5^5, OK
y := 0.5**3 -- 0.5^3, OK
y := 0.5**3 -- 0.5^3, OK
x := 4**0.5 -- 4^0.5, Illegal
x := 4**0.5 -- 4^0.5, Illegal
y := 0.5**(-2) -- 0.5^(-2), OK
y := 0.5**(-2) -- 0.5^(-2), OK
Lecture - 5
69
Examples
 Design a library of logic gates

 AND, OR, NAND, NOR, INV, etc.
 Include sequential elements
 DFF, Register, etc.
 Include tri-state devices
 Use 4-valued logic
 ‘X’, ‘0’, ‘1’, ‘Z’
 Encapsulate global declarations in a package
Lecture - 5
70
Global Package
PACKAGE
PACKAGE resources
resources IS
IS
TYPE
TYPE level
level IS
IS ('X',
('X', '0',
'0', '1',
'1', 'Z');
'Z'); --
-- enumerated
enumerated type
type
TYPE
TYPE level_vector
level_vector IS
IS ARRAY
ARRAY (NATURAL
(NATURAL RANGE
RANGE <>)
<>) OF
OF level;
level;
--
-- type
type for
for vectors
vectors (buses)
(buses)
SUBTYPE
SUBTYPE delay
delay IS
IS TIME;
TIME; --
-- subtype
subtype for
for gate
gate delays
delays
--
-- Function
Function and
and procedure
procedure declarations
declarations go
go here
here
END
END resources;
resources;

Lecture - 5
71
Two Input AND Gate Example
USE
USE work.resources.all;
work.resources.all; ARCHITECTURE
ARCHITECTURE behav
behav OF
OF and2
and2 IS
IS
ENTITY BEGIN
ENTITY and2
and2 IS
IS BEGIN
GENERIC(trise one
one :: PROCESS
PROCESS (a,b)
(a,b)
GENERIC(trise :: delay
delay :=
:= 10
10 ns;
ns;
tfall : delay := 8
tfall : delay := 8 ns);ns);
BEGIN
BEGIN
IF
IF (a
(a == '1'
'1' AND
AND bb == '1')
'1') THEN
THEN
PORT(a,
PORT(a, bb :: IN
IN level;
level; cc <= '1' AFTER trise;
<= '1' AFTER trise;
cc :: OUT
OUT level); ELSIF
level); ELSIF (a(a == '0'
'0' OR
OR bb == '0')
'0') THEN
THEN
END and2;
END and2; cc <= '0' AFTER tfall;
<= '0' AFTER tfall;
ELSE
ELSE
c<=
c<= 'X'
'X' AFTER
AFTER (trise+tfall)/2;
(trise+tfall)/2;
END IF;
END IF;
END
END PROCESS
PROCESS one;
one;
END
END behav;
behav;

Lecture - 5
72
Tri-State Buffer Example
ARCHITECTURE behav OF tri_state IS

ARCHITECTURE behav OF tri_state IS
USE
USE work.resources.all;
work.resources.all; BEGIN
BEGIN
ENTITY one : PROCESS (a,e)

ENTITY tri_state
tri_state IS
IS one : PROCESS (a,e)
BEGIN
GENERIC(trise BEGIN
GENERIC(trise :: delay
delay :=
:= 66 ns;
ns; IF (e = '1' AND a = '1') THEN
IF (e = '1' AND a = '1') THEN
tfall : delay := 5
tfall : delay := 5 ns;ns; -- enabled and valid data
-- enabled and valid data
thiz b <= '1' AFTER trise;
thiz :: delay
delay :=
:= 88 ns);
ns); b <= '1' AFTER trise;
ELSIF (e = '1' AND a = '0') THEN
ELSIF (e = '1' AND a = '0') THEN
b <= '0' AFTER tfall;
b <= '0' AFTER tfall;
PORT(a
PORT(a :: IN
IN level;
level; ELSIF (e = '0') THEN -- disabled
ELSIF (e = '0') THEN -- disabled
ee :: IN level; b <= 'Z' AFTER thiz;
IN level; b <= 'Z' AFTER thiz;
ELSE -- invalid data or enable
bb :: OUT ELSE -- invalid data or enable
OUT level);
level); b <= 'X' AFTER (trise+tfall)/2;
b <= 'X' AFTER (trise+tfall)/2;
END IF;
END IF;
END
END tri_state;
tri_state; END PROCESS one;
END PROCESS one;
END behav;
END behav;

Lecture - 5
73
D Flip Flop Example
USE work.resources.all; ARCHITECTURE behav OF dff IS
USE work.resources.all; ARCHITECTURE behav OF dff IS
BEGIN
BEGIN
ENTITY dff IS one : PROCESS (clk)
ENTITY dff IS one : PROCESS (clk)
BEGIN
BEGIN
-- check for rising clock edge
GENERIC(tprop : delay := 8 ns; -- check for rising clock edge
GENERIC(tprop : delay := 8 ns; IF ((clk = '1' AND clk'LAST_VALUE = '0')
IF ((clk = '1' AND clk'LAST_VALUE = '0')
tsu : delay := 2 ns); AND enable = '1') THEN -- ff enabled
tsu : delay := 2 ns); AND enable = '1') THEN -- ff enabled
-- first, check setup time requirement
-- first, check setup time requirement
IF (d'STABLE(tsu)) THEN
PORT(d : IN level; IF (d'STABLE(tsu)) THEN
PORT(d : IN level; -- check valid input data
clk : IN level; -- check valid input data
clk : IN level; IF (d = '0') THEN
enable : IN level; IF (d = '0') THEN
enable : IN level; q <= '0' AFTER tprop;
q <= '0' AFTER tprop;
q : OUT level; qn <= '1' AFTER tprop;
q : OUT level; qn <= '1' AFTER tprop;
qn : OUT level); ELSIF (d = '1') THEN
qn : OUT level); ELSIF (d = '1') THEN
qn <= '0' AFTER tprop;
END dff; qn <= '0' AFTER tprop;
END dff; ELSE -- else invalid data
ELSE -- else invalid data
q <= 'X';
q <= 'X';
qn <= 'X';
qn <= 'X';
END IF;
END IF;
ELSE -- else violated setup time requirement
ELSE -- else violated setup time requirement
q <= 'X';
q <= 'X';
qn <= 'X';
qn <= 'X';
END IF;
END IF;
END IF;
END IF;
END PROCESS one;
END PROCESS one;
END behav;
END behav;

Lecture - 5
74
Summary
 VHDL is a worldwide standard for the description and

modeling of digital hardware
 VHDL gives the designer many different ways to
describe hardware
 Familiar programming tools are available for complex
and simple problems
 Sequential and concurrent modes of execution meet a
large variety of design needs
 Packages and libraries support design management and
component reuse
Lecture - 5
75
Putting It All Together
Package
Generics Entity Ports
Architecture Architecture Architecture
Concurrent Process
Concurrent
Statements
Statements
Sequential Statements

Lecture - 5
76
Lecture - 5
77

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Hardware Description

Professor: Sci.D., Professor

Synopsys University Courseware

 The Role and Classification of HDLs

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 VHDL is an international IEEE standard specification

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 Very High Speed Integrated Circuit (VHSIC) Program

 In July 1983, a team of Intermetrics, IBM and Texas

Cell, Module Plans

 Allows various design methodologies

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 Problem: Design a single bit half adder with

PORT( x, y, enable: IN BIT;

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 The model can then be simulated to verify correct functionality of the

 Again, the model can be simulated at this

 These gates can be pulled from a library of parts

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 The primary purpose of the entity is to declare the signals in the

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 PORT clause declares the interface signals of the object

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 Generics may be used for readability, maintenance and

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 Describe the operation of the component

ARCHITECTURE half_adder_d OF half_adder IS

 Pre-defined VHDL components are instantiated and

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 VHDL provides two styles of describing component

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 VHDL uses the following simulation cycle to model the

 All VHDL signal assignment statements prescribe an amount of time

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 Transport delay must be explicitly specified

 Provides specification propagation delay and input pulse width, i.e.

 Example of gate with ‘inertia’ smaller than propagation delay

 Default signal assignment propagation delay if no delay

 Supports a model of concurrent VHDL process execution

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eval NAND, AND

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 All declarations of VHDL ports, signals, and variables must specify

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 Example of 1D array using DOWNTO :

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