IIIHHHHHHHHHHHIII US00521.

4575A
United States Patent (19) 11 Patent Number: 5,214,575
Sugishima et al. 45) Date of Patent: May 25, 1993
54 GROUND FAULT DETECTOR FOR AN Attorney, Agent, or Firm-Sughrue, Mion, Zinn,
NVERTER AND A METHOD THEREFOR Macpeak & Seas
75) Inventors: Eiichi Sugishima; Taro Ando, both of 57 ABSTRACT
Aichi, Japan An apparatus and method for detecting a ground fault
73 Assignee: Mitsubishi Denki Kabushiki Kaisha, occurring on an outputside of an inverter circuit, which
Tokyo, Japan includes a converter circuit for rectifying an alternating
(21) Appl. No.: 807,514. current into a direct current, a capacitor for smoothing
the direct current, an inverter circuit for converting the
(22) Filed: Dec. 16, 1991 smoothed direct current into a predetermined fre
(30) Foreign Application Priority Data quency and voltage through the on/off operation of
switching elements connected in parallel with diodes,
Dec. 14, 1990 (JP) Japan .................................. 2-402215 and a PWM signal generator for controlling the on/off
51 Int. Cl........................ H02M 5/458; HO2H 7/12 of the switching elements. The ground fault detector
52 U.S. C. ........................................ 363/37; 361/42; includes current detectors for detecting current flowing
363/56; 363/98 in the switching elements, a device for detecting an
58) Field of Search ....................... 363/37, 50, 56,58, overcurrent flowing from one of the switching elements
363/98; 361/42, 47 and for outputting an overcurrent signal when the out
put of any of the current detectors exceeds a predeter
56) References Cited mined value, a device for detecting a zero vector signal
U.S. PATENT DOCUMENTS transmitted by the PWM signal generator, and a ground
fault detector circuit for detecting a ground fault condi
4,370,702 1/1983 Shuey ........ ... 363/98 tion in accordance with the overcurrent signal and the
4,870,527 9/1989 Zaleski .......... ... 361/44 zero vector detection signal.
4,893,479 1/1990 Gillett et al. .......................... 62/213
Primary Examiner-William H. Beha, Jr. 14 Claims, 7 Drawing Sheets

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24c
U.S. Patent May 25, 1993 Sheet 1 of 7 5,214,575

FIG.
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20 2c 5C
AN AN MTV MY AN AV

- 2d 2e 2f 4d
O) 7\ ZV AN ZN AN AY

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is as a as as
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U.S. Patent May 25, 1993 Sheet 2 of 7 5,214,575

FIG. 2

2G 5c
N A AN AN AN AY

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(C) 2d
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2e 2f

|| ||

22e
U.S. Patent May 25, 1993 Sheet 3 of 7 5,214,575

FIG 3
4p

2G 2c 5c
AA AN AA

S 3 W

O Av AN AY AN ATA ?y

O) O) 2f
-ty.
U.S. Patent May 25, 1993 Sheet 4 of 7 5,214,575

FG. 4

20
AN fN
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AY
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5c

S W

(C) .. s s AV MY

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22n

24n
U.S. Patent May 25, 1993 Sheet 5 of 7 5,214,575

PWM
SIGNAL
GENERATOR O)4c

aT isthi
No a SS
U.S. Patent May 25, 1993 Sheet 6 of 7 5,214,575

S 73 S74
TREATMENT OF GROUND TREATMENT OF
FAULT ONERCURRENT

TOMAIN
PROGRAM
U.S. Patent May 25, 1993 Sheet 7 of 7 5,214,575

FG. 9
PRIOR ART
 5,214,575
1. 2
tors V0 to V7 of the load 9 represented by (000), (001),
GROUND FAULT DETECTOR FOR AN INVERTER (010), (011), (100), (101), (110), and (111). The phase
AND A METHOD THEREFOR voltage vectors V0 and V7 (also referred to herein as
zero vectors) are voltage vectors available when the
BACKGROUND OF THE INVENTION load 9 is disconnected from the inverter and the termi
The present invention relates to an apparatus and nals are short circuited by the inverter. A signal is trans
method for detecting a ground fault occurring on the mitted by the PWM signal generator to the gate of each
output side of an inverter circuit. switching element 4g to 4l to output any one of the eight
Referring to FIG. 9, there is shown a three-phase voltage vectors V0 to V7.
alternating current power supply 1 grounded at a neu O The output frequency adjustment and output voltage
tral point, a converter circuit, an inverter circuit, a load control can be controlled by controlling the sequence
9, U-, V., and W-phase current detectors, and a ground and time of outputting the voltage vectors V0 to V7
fault detection circuit. The three-phase alternating cur according to a variety of processes which have already
rent power supply 1 supplies current to the converter been presented and which are known in the art. Ac
circuit, that is, the inputs of the bridged diodes 2a to 2f, 5 cordingly, such processes will not be described herein.
which are coupled to a smoothing capacitor 3. The The operation of the ground fault detector circuit
inverter circuit, which includes a series of switching will now be described.
elements 4g to 4l (e.g., IGBTs or Insulated Gate Bipolar Provided that the load 9 is a three-phase balanced
Transistors) respectively arranged in parallel with di load, the sum of currents Iu, v and Iw flowing in the
odes. 5a to 5g, is coupled to the output of the converter 20 U-, V., and W-phase and respectively detected by the
circuit and capacitor 3. The diodes 5g to 5l are intended U-phase current detector 6, the V-phase current detec
to cause a reactive current to flow in the load 9. tor 7, and the W-phase current detector 8, is zero. The
The output of the inverter circuit is connected to load U-phase current detection signal 6a, V-phase current
9 via a U-phase current detector 6, a V-phase current detection signal 7a, and the W-phase current detection
detector 7, and a W-phase current detector 8, which 25
respectively output and apply a U-phase current detec signal 8a are applied to the adder 10 such that if the load
tion signal 6a, a V-phase current detection signal 7a, and 9 is balanced the output of the adder 10 is zero. How
a W-phase current detection signal 8a to an adder 10. ever, if the load is not kept balanced due to a ground
The output of the adder 10 is coupled to a comparator fault occurring in the load, the output of the adder 10
11, which compares the output of the adder with a 30 becomes other than zero and its level is compared with
ground fault determination reference signal 12 and out the level of the ground fault determination reference
puts a ground fault signal 13, accordingly. signal 12 by the comparator 11. The comparator 11 will
The converter circuit is a three-phase full-wave recti output a ground fault signal 13 if the compared level is
fier including an R-phase composed of the diodes 2a greater than that of the ground fault determination
and 2d, S-phase composed of the diodes 2b and 2e, and 35 reference signal 12. The adder 10 also serves as an abso
a T-phase composed of the diodes 2c and 2f Likewise, lute value amplifier.
the inverter circuit is a three-phase device, namely a The inverter circuit described above requires high
U-phase including the switching elements 4g and 4j. priced current detector DCCTs, resulting in a cost
V-phase including the switching elements 4h and 4k, increase. In addition, the current detector DCCTs are
and a W-phase including the switching elements 4i and of such a large-size that it is not practical to incorporate
4l. them into power ICs, which have become recently
The current detector used with each phase is a so available on the market, and contain drive or protective
called DCCT, which is a current detector employing a circuits together with switching elements and diodes in
Hall element to detect a direct or an alternating current. the same package.
The operation of the thus constructed circuit will 45 SUMMARY OF THE INVENTION
now be described.
An alternating current supplied by the three-phase Accordingly, it is a general object of the present
alternating current power supply 1 is rectified by the invention to overcome the disadvantages in the prior art
three-phase full-wave rectifier converter circuit (i.e., by providing an apparatus and method for detecting a
the bridged diodes 2a to 2f) and is smoothed into a 50 ground fault for an inverter circuit while avoiding the
direct current by the capacitor 3. The smoothed direct use of high-cost current detectors.
current is applied to the switching elements 4g to 4l, In accordance with the above and other objects, the
which are switched ON/OFF by a gate signal from a present invention provides a ground fault detector for
PWM (Pulse Width Modulated) signal generator (not an inverter, which includes a converter circuit for recti
shown) to supply the load 9 with an alternating-current 55 fying an alternating current into a direct current, a
voltage of an arbitrary frequency and voltage. The capacitor for smoothing the direct current, an inverter
PWM signal generator (e.g., a microprocessor) gener circuit for converting the smoothed direct current into
ates eight types of voltage vectors V0 to V7 described a predetermined frequency and voltage through the
below. on/off operation of switching elements connected in
One of the positive- and negative-arm switching ele parallel with diodes, and a PWM signal generator for
ments in each phase U, V, and W is assumed to be al controlling the on/off of the switching elements, and
ways on. For convenience of explanation, the positive the ground fault detector includes a current detector for
switching elements in each phase when ON are indi detecting current flowing in corresponding ones of the
cated as '1', and the negative switching elements when switching elements, overcurrent determining means for
ON are indicated as "0". Accordingly, the ON/OFF 65 outputting an overcurrent signal when the output of
states of the switching elements for the U-, V-, and any of the current detectors exceeds a predetermined
W-phases are represented by a notation such as (100), value, zero vector determining means for outputting a
(101), etc. There are eight states or phase voltage vec zero vector detection signal when a voltage vector
 5,214,575
3 4
signal transmitted by the PWM signal generator is a photocoupler 17a is designated by reference numeral
zero vector signal, and a ground fault detector circuit 24a. The output of the photocoupler 17a is pulled down
for judging a ground fault in accordance with the over by a resistor 18a and applied to a first input of an OR
current signal and the zero vector detection signal. circuit 19. The output of the OR circuit 19 is coupled to
Further in accordance with the above and other ob an AND circuit 21, whose second input is coupled to a
jects, the present invention provides a method for de zero vector signal 20. The output 13 of the AND circuit
tecting a ground fault of an inverter, which includes a 21 represents a ground fault signal.
converter circuit for rectifying an alternating current The switching elements 4b to 4fare constructed in
into a direct current, a capacitor for smoothing the the same manner as the switching element 4a, and each
direct current, an inverter circuit for converting the 10 output thereof is respectively coupled to a circuit 24b to
smoothed direct current into a predetermined fre 24f each having an output coupled to an input of the
quency and voltage through the on/off operation of OR circuit 19. The circuits 24b to 24fare constructed
switching elements connected in parallel with diodes, identically to the circuit 24a, that is, each circuit 24b to
and a PWM signal generator for controlling the on/off 24f includes a comparator 15, resistor 16, and photocou
of the switching elements, wherein the method includes 15 pler 17.
the steps of detecting current flowing in any of the FIG. 5 illustrates the gate signal generator, which
switching elements, generating an overcurrent signal includes a PWM signal generator 30 for generating the
when the detected current exceeds a predetermined voltage vectors V0 to V7, AND circuits 26, 27, and 29a
amount, generating a zero vector signal when a voltage to 29f, and an OR circuit 28.
vector signal transmitted by the PWM signal generator 20 The operation of the embodiment illustrated in FIGS.
is a zero vector signal, and generating a ground fault 1 and 5 will now be described.
signal in accordance with the overcurrent signal and the The operation of the main circuit (i.e., the converter)
zero vector signal. is identical to that of the prior art. There are a total of
BRIEF DESCRIPTION OF THE DRAWINGS 25 six switching elements 4a to 4f two in each phase. Since
each phase operates identically, the positive switching
FIG. 1 is a circuit diagram illustrating a first embodi element in the U-phase only will be described.
ment of the present invention. The amount of current flowing through the sense
FIG. 2 is a circuit diagram illustrating a second em emitter and the resistor 14a, which is a portion of the
bodiment of the present invention. main current flowing through the switching element
FIG. 3 is a circuit diagram illustrating a third embodi 30 14a including the emitter, is determined by the compar
ment of the present invention. ator 15a by comparing the voltage generated across the
FIG. 4 is a circuit diagram illustrating a fourth em resistor 14a with the overcurrent determination signal
bodiment of the present invention. 22a. The overcurrent determination signal 22a is set so
FIG. 5 provides a circuit example for illustrating the that the switching element 4a is not damaged by an
receipt of zero vectors and the gate control of switching 35 overcurrent. If an overcurrent flows in the switching
elements. element 4a, the voltage of the resistor 14a rises above
FIG. 6 illustrate current flow in each phase of the that of the overcurrent determination signal 22a, gener
inverter. ating an output of the comparator 15a to cause the
FIG. 7 illustrate a ground fault occurring in the in photocoupler 17 to conduct, thereby applying a
Vetter. "HIGH" signal to the input of the OR circuit 19. The
FIG. 8 is a flow chart showing the judgment of a five remaining positive and negative switching elements
ground fault made on a software basis. operate in the same way: if an overcurrent occurs in any
FIG. 9 is a circuit diagram of the inverter known in of the switching elements 4b to 4f, a "HIGH' signal is
the present art. applied to the OR circuit 19.
DESCRIPTION OF THE PREFERRED
45 The output 23 of the OR circuit 19 is inverted by an
EMBODMENTS inverter 31 and applied to a first input of the AND
circuit 29a and a switching element 4a gate circuit ON/-
FIG. 1 is a circuit diagram illustrating a first embodi OFF signal transmitted by the PWM signal generator
ment of the present invention, wherein the numerals 1, 30 is applied to the second input of the AND circuit
2a to 2f, 3, 5a to 5f, and 9 represent identical compo 50 29a, thereby controlling the switching element gate
nents as those illustrated in FIG. 9. The switching ele circuit. When an overcurrent is generated in the switch
ments 4g to 4l shown in FIG. 9 have been replaced by ing element 4a, the output 23 of the OR circuit 19 transi
switching elements 4a to 4f such as IGBTs, each hav tions to "HIGH' thus causing the output of the AND
ing its sense emitter coupled to a resistor 14a to 14f circuit 29a to transition to OFF (i.e., "LOW'), thereby
(such switching elements are referred to as "sense 55 switching the switching element 4a to OFF.
IGBTs”). The output of the OR circuit 19 is also coupled to the
One end of the resistor 14a is coupled to both the AND circuit 21. When the zero vector signal 20 is
emitter of the switching element 4a and to a first input asserted, the AND circuit 21 generates the ground fault
of a comparator 15a, An overcurrent determination signal 13 corresponding to the output of the OR circuit
signal 22a, which is used as a threshold vis-a-vis the 19. The zero vector signal 20 output by the PWM signal
current flowing from the emitter-resistor 14a node, is generator 30 is switched "HIGH' when a zero vector
applied to a second input of the comparator 15a. The V0 and V7 is generated. Accordingly, the AND circuit
output of the comparator 15a is connected to a primary 21 outputs the ground fault signal 13 when the "HIGH'
input of a photocoupler 17a via a resistor 16a. The zero vector signal is output by the PWM signal genera
output of the comparator 15a is received by the 65 tor 30 and the "HIGH' signal is output by the OR
photocoupler 17a to provide isolation and transfer a circuit 19 at the time of overcurrent.
signal between circuits different in potential. A circuit The AND circuits shown in FIG. 5 detect the occur
including the comparator 15a, resistor 16a, and rence of the zero vectors V0 (000) and V7 (111). In
 5,214,575
5 6
FIG. 5, the phase voltage vectors V0 to V7 are gener signal 22e. The outputs of the comparators 15d, 15e, and
ated by the PWM signal generator 30. When the phase 15fare connected together and coupled to one end of a
voltage vector is V0 (000), the AND circuit 26 outputs resistor 16e. The other end of the resistor 16e is coupled
a "HIGH" signal, and when the phase voltage vector is to a single photocoupler 17e, whose output is pulled
V7 (111), the AND circuit 27 outputs a "high' signal. 5 down by the resistor 18e and is coupled to an input of
The OR circuit 28 generates asserts the zero vector the OR circuit 19.
signal 20 when either of the AND circuits 26 and 27 The circuit of FIG. 2 is somewhat of a compromise
generate a "HIGH' output. between the FIG. 1 arrangement and those described
The manner in which a ground fault is detected will above, in which detection for one or the other of the
now be described in detail. 10 positive and negative sides is simply eliminated, in that
With respect to FIG. 6, there is shown only the in separate photocouplers are not used for one of the posi
verter circuit, which has been extracted from the over tive and negative sides, yet sense levels are taken from
all circuit diagram. The converter circuit is shown as a resistors provided at each of the switching elements.
direct current power supply 25. Assuming that the It should be appreciated that the present invention is
switching elements 4a, 4e, and 4f are ON, (i.e., the in 15 not limited to sense IGBTs, which have been employed
verter state is vector V4), the direct current power as the switching elements in the FIG. 1 embodiment,
supply 25 causes current to flow into the load. There but other electrical valves such as transistors and MOS
fore, if the load is a motor comprising resistors and FETs can be used. Naturally, IGBTs of the type not
inductances, the current will increase gradually. When employing separate sense emitters can be employed as
the inverter transitions to the vector V0 state (i.e., 20 well. It should be further appreciated that the resistors
where the switching element 4a is OFF) and the switch provided for the emitters of the switching elements may
ing element 4d is ON, the current traverses the path either be installed inside or outside the switching ele
through the diode 5d and the switching elements 4e and ment packages.
4f as shown by dotted line in FIG. 6. Simultaneously, FIG. 3 is a circuit diagram illustrating a further em
the current will decrease gradually because energy 25 bodiment of the present invention, wherein the refer
accumulated in the inductances of the load during vec ence numerals. 1, 2a to 2f, 3, 4g to 4l, 5a to 5f, and 9
tor V4 is dissipated by the resistors. Hence, an actual designate identical components to those of the conven
overcurrent will occur only when in a vector state tional device shown in FIG. 9. Resistors 14p and 14n
other than the vector V0 and V7 states. When a ground detect current flowing from the converter circuit to the
fault occurs at vector V0 state as shown in FIG. 7, a 30 inverter circuit. The voltage drop across the resistors
ground fault current flows, for example, as indicated by 14p and 14n is respectively applied to the comparators
an arrow which may vary because of the phase. The 15p and 15n. From these areas onward, the operation is
current flowing in the resistor 14d, which is coupled to identical to that described in the first embodiment.
the sense emitter of the switching element 4d, increases If a ground fault current occurs in the circuit of the
and the comparator 15d, the photocoupler 16d are con 35 second embodiment, it will flow in one of the resistor
ditioned such that the OR circuit 19 generates the over 14p and 14n provided between the converter circuit and
current signal 23. Since an overcurrent signal cannot be the inverter circuit, thereby allowing the ground fault
generated in this state, a ground fault can be determined to be detected in the same way as in the first embodi
appropriately by the AND circuit 21 by logically ment, though requiring less resistors to be used overall.
ANDing the zero vector signal 20 and the output of the In FIG. 3, the resistor 14 may be only provided on
OR circuit 19. one side instead of both sides of the line connecting the
The resistors 14a to 14f coupled to the sense emitters converter circuit and the inverter circuit of the inverter.
of the six switching elements in the embodiment are not FIG. 4 illustrates yet another embodiment of the
limited to that as shown in FIG. 1 but resistors may be present invention, wherein the reference numerals 1, 2a
installed at only the upper-arm switching elements 4a, 45 to 2f, 3, 4g to 4l, 5g to 5l. and 9 indicate identical compo
4b and 4c. Accordingly, only comparators 15a, 15b, and nents to those of the conventional device shown in FIG.
15c need to provided. 9. Resistors 14p and 14n detect the current flowing from
Alternatively, resistors may only be installed at the the positive input of the switching elements and the
lower-arm switching elements 4d, 4e, and 4f and thus positive output of the diodes, which are connected in
only the comparators 15d, 15e and 15f would need to be 50 parallel with the switching elements. As described in
employed to provide a much lower-cost inverter. In this the first and second embodiments, only one resistor
case, for example, if the resistors are only installed at the must necessarily be provided.
lower arms, a ground fault occurring at vector V7 can It will be recognized that the determination of a
not be detected when the ground fault current flows ground fault employing the combination of the AND
through the switching element 4a, but a ground fault 55 and OR circuits in the three embodiments may also be
can be detected when the power supply phase changes made on a software basis using a microprocessor. FIG.
and the switching element 4d is turned ON. Therefore, 8 illustrates a flowchart which represents the software
the overcurrent resistance must be carefully selected for process as will now be described.
the switching element 4a so that it may not be damaged The occurrence (i.e., detection) of an overcurrent
during that period. generates an interrupt in which the software will per
FIG. 2, which illustrates a second embodiment of the form an interrupt service routine beginning with step
present invention, is identical to the FIG. 1 embodiment S70. In step S71, it is judged whether the inverter state
except for the circuits 24a to 24f. That is, in the second is the phase voltage vector V0. If the current inverter
embodiment, the sense emitters of the switching ele state is phase voltage vector V0 then a ground fault has
ments 4d, 4e, and 4fare respectively coupled to first 65 occurred and appropriate action is taken in step S73. On
inputs of comparators 15d, 15e, and 15f The second the other hand, if the current inverter state is not the
inputs of the comparators 15d, 15e, and 15fare all cou phase voltage vector V0, then it is judged, in step S72,
pled to a single overcurrent determination reference whether the current inverter state is phase voltage vec
 5,214,575
7 8
tor V7. If yes, then an overcurrent condition has oc 4. The ground fault detector as recited in claim 1,
curred, and such is treated in step S74 accordingly prior wherein said current detectors comprise current detect
to returning to the main software program. ing resistors provided between a positive side of said
It will be apparent that the invention as described switching elements and a positive side of said diodes
herein provides a ground fault detector for an inverter which are connected in parallel with said switching
circuit that does not require high-cost overcurrent de elements.
tectors, such as DCCTs and allows current detecting 5. The ground fault detector as recited in claim 1,
resistors to be installed inside switching element pack wherein said switching elements comprise an element
ages, that is, resistors which are provided in the emitters selected from the group consisting of IGBTs, field ef
of switching elements, between the converter circuit O fect transistors, thyristors, and transistors.
and inverter circuit of the inverter, or between the 6. The ground fault detector as recited in claim 1,
positive side of the switching elements and the positive wherein said overcurrent determining means comprises:
side of diodes, to allow an overcurrent flowing in any a comparator coupled to an output of said current
switching element to be detected and a ground fault to detector and an overcurrent threshold signal;
be detected by logically ANDing the overcurrent de 15 a resistor having one end coupled to an output of said
tection signal and a zero vector signal among voltage comparator; and
vectors transmitted by a PWM signal generator. Fur a photocoupler coupled to a second end of said resis
ther, the present invention achieves an inverter which tor, so that when said output of said current detec
can compactly integrate parts therein if the current tor exceeds said overcurrent threshold signal said
detecting resistors are installed outside the switching 20 photocoupler outputs an overcurrent detection
elements, between the converter circuit and inverter signal.
circuit, or between the positive side of the switching 7. The ground fault detector as recited in claim 6,
elements and the positive side of the diodes. wherein said overcurrent determining means further
There has thus been shown and described a novel 25 comprises:
apparatus and method for detecting a ground fault in an an OR circuit having an input coupled to each output
inverter circuit which fulfills all the objects and advan of each overcurrent determining means such that
tages sought therefor. Many changes, modifications, said OR circuit outputs a signal when any one of
variations and other uses and applications of the subject said overcurrent determining means outputs said
invention will, however, become apparent to those overcurrent detection signal.
skilled in the art after considering the specification and
30 8. The ground fault detector as recited in claim 1,
the accompanying drawings which disclose preferred wherein said ground fault detector circuit comprises an
AND circuit.
embodiments thereof. All such changes, modifications, 9. The ground fault detector as recited in claim 1,
variations and other uses and applications which do not wherein said PWM signal generator transmits voltage
depart from the spirit and scope of the invention are 35 vector signals according to a predetermined pattern.
deemed to be covered by the invention which is limited 10. The ground fault detector as recited in claim 9,
only by the claims which follow. wherein said predetermined pattern comprises the volt
What is claimed is: age vector signals of 000, 001, 010, 011, 100, 101, 110,
1. A ground fault detector for an inverter comprising 111.
a converter circuit for rectifying an alternating current 11. The ground fault detector as recited in claim 10,
into a direct current, a capacitor for smoothing said wherein said zero vector signal comprises the voltage
direct current, an inverter circuit for converting said vector signals of 000 and 111.
smoothed direct current into a predetermined fre 12. The ground fault detector as recited in claim 1,
quency and voltage through the on/off operation of wherein said inverter circuit has three phases each hav
switching elements connected in parallel with diodes, 45 ing a positive and a negative switching element, and
and a PWM signal generator for controlling the on/off wherein said overcurrent determining means comprises
of said switching elements, said ground fault detector a means for detecting an overcurrent in at least each of
comprising: one of said positive and said negative switching arms for
current detectors for detecting current flowing in each of said three phases.
corresponding one of said switching elements; 50 13. The ground fault detector as recited in claim 1,
overcurrent determining means for outputting an wherein said inverter circuit has three phases each hav
overcurrent signal when the output of any of said ing a positive and a negative switching element, and
current detectors exceeds a predetermined value; wherein said overcurrent determining means comprises
zero vector determining means for outputting a zero a means for detecting an overcurrent in each of said
vector detection signal when a voltage vector sig 55 positive switching arms for each of said three phases
nal transmitted by said PWM signal generator is a and a means for detecting an overcurrent in any one of
Zero vector signal; and said negative switching arms for each of said three
a ground fault detector circuit for judging a ground phases.
fault in accordance with said overcurrent signal 14. A method for detecting a ground fault of an in
and said zero vector detection signal. verter comprising a converter circuit for rectifying an
2. The ground fault detector as recited in claim 1, alternating current into a direct current, a capacitor for
wherein said current detector comprises a current de smoothing said direct current, an inverter circuit for
tecting resistor provided at a sense emitter of each converting said smoothed direct current into a predeter
switching element. mined frequency and voltage through the on/off opera
3. The ground fault detector as recited in claim 1, 65 tion of switching elements connected in parallel with
wherein said current detector comprises current detect diodes, and a PWM signal generator for controlling the
ing resistors provided between said converter circuit on/off of said switching elements, said method compris
and said inverter circuit. ing the steps of:
 5,214,575
9 10
detecting current flowing in any of said switching signal transmitted by said PWM signal generator is
elements; a zero vector signal; and
generating an overcurrent signal when said detected generating a ground fault signal in accordance with
current exceeds a predetermined amount; said overcurrent signal and said zero vector signal.
generating a zero vector signal when a voltage vector 5 k . . . .

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