1

A Survey on FEC Codes for 100G and Beyond

Optical Networks
G. Tzimpragos, C. Kachris, I. B. Djordjevic, M. Cvijetic, D. Soudris, and I. Tomkos

Abstract—Due to the rapid increase of network traffic in the and combat additional optical impairments, such as non-linear
last few years, many telecommunication operators have started effects, uncompensated chromatic dispersion and polarization
transitions to 100 Gb/s optical networks and beyond. However, mode dispersion [1]. Moreover, along with the growth of
high speed optical networks need more efficient Forward Error
Correction (FEC) codes to deal with the optical-impairments, optical networks, economics imposed the development of
such as uncompensated chromatic dispersion (CD), polarization powerful electronic end-to-end processing mechanisms, which
mode dispersion (PMD) and non-linear effects, and keep the bit- are primarily based on strong FECs, in order to enhance
error-rate (BER) at long distances sufficiently low. To address optical-transparency [2]. Hence, FEC systems with different
these issues, new FEC codes, called 3rd generation codes, have transmission overhead, implementation complexity, coding-
been proposed. The majority of these codes are based on
soft-decision decoders and can provide higher coding gain as gain, BER-performance, burst-error correction ability and error
compared to their predecessors. This paper presents a thorough floor (phenomenon, where there is a point after which FEC’s
survey of 3rd generation FEC codes, suitable for 100G and performance flattens suddenly) are available in today’s market.
beyond optical networks. Furthermore, the paper discusses the Thus, the most recent 3rd generation FEC codes are developed
main advantages and drawbacks of each scheme and provides aiming to provide a Net Coding Gain, greater than 9.6dB at
a qualitative categorization and comparison of the proposed
schemes based on their main features, such as net coding gain post-FEC BER of 10−12 , in order to achieve the same quality
(NCG) and BER. Information about the complexity of each for 100G networks as that of 40G systems using a Reed-
scheme is given, as well. Solomon (255,239) code [3], [4].
Index Terms—Error Control Coding (ECC), Forward error Our goal in this paper is to provide an overview of the
correction(FEC), 3rd Generation, Optical Networks, 100G, Sur- characteristics of FEC codes, analyze the key parameters and
vey. advantages/drawbacks related to analyzed coding schemes,
as well as the key challenges and directions in their future
I. I NTRODUCTION employment. Hence, we outline key references used in our
analysis as well as ones that will help the reader to follow

T HE RISE of emerging applications like cloud computing,

streaming video and social networks in the last few years
has increased the Internet traffic significantly. To cope with
up this topic in references providing detailed treatment of
advanced topics in optical communications , such as [5]. Addi-
tionally, this paper aims at going beyond existing bibliography,
this rise, many telecom operators had to increase the data such as [1], [2] and [4], by presenting current state-of-the-
rates of their optical networks considerably. However, the fact art advanced FEC schemes (including solutions both from
that the optical networks are often limited by several forms of industry and academia), providing a qualitative categorization
noises, boosts the development and use of advanced Forward and comparison between them and pointing out the challenges
Error Correction techniques in modern Dense Wavelength and possible directions with their implementation.
Division Multiplexing (DWDM) communication systems. In
more detail, FEC codes were initially used in optical networks The paper is organized as follows: Section II, provides the
to mitigate amplified spontaneous emission (ASE), a form reader with information about all the principal aspects of Error
of noise native in optical amplifiers, where the bit errors Control Coding (ECC) and Forward Error Correction. Section
occur randomly. However, as transmission rates gradually up- III presents the evolution of FEC codes and briefly discusses
scaled, FECs had to perform under burst error conditions the main features of each generation. Section IV describes the
main state-of-the art codes that have been proposed recently
G. Tzimpragos is with the Department of Electrical and Computer En- both by academia and industry. Section V depicts the tax-
gineering, National Technical University of Athens and Athens Information onomy of these codes and provides a qualitative comparison
Technology, Greece. E-mail: getzim@microlab.ntua.gr, getzim@ait.edu.gr
C. Kachris and I. Tomkos are with Athens Information Technology, Greece.
based on the benefits and drawbacks of each scheme. Finally,
E-mail: {kachris, itom}@ait.edu.gr concluding remarks are given in Section VI. Overall, the main
I. B. Djordjevic and M. Cvijetic are with the Department of Electrical and contributions of this paper are the following:
Computer Engineering of the University of Arizona, Tucson, AZ, USA. Email:
{ivan,milorad }@ece.arizona.edu • A review of the key features of the 3rd Generation FEC
D. Soudris is with the Department of Electrical and Computer Engi-
neering of the National Technical University of Athens, Greece. E-mail: codes for next generation optical networks,
dsoudris@microlab.ntua.gr • a taxonomy and categorization of the most recent pro-
The research leading to these results is partially supported by the ASTRON posed schemes both by academia and industry, and
project (Adaptive Software-defined Terabit Transceiver for flexible Optical
Networks) with funding from the European Community’s Seventh Framework • a qualitative comparison of the proposed schemes based
Programme [FP7/2007-2013] under grant agreement n. 318714. on their main features.
 2

We should mention that the advanced FEC methods can be code-symbols fall into the same codeword, until a decision is
combined with the advanced modulation formats to perform made to switch to the next codeword. Therefore, the resulting
these functions simultaneously in so-called coded-modulation codewords may have unequal lengths [7].
schemes. However, the purpose of this survey is to analyze Another distinction of FEC codes is between Hard-Decision
and compare the features of the FEC schemes, while coded (HD) and Soft-Decision (SD). The difference between Hard-
modulation methods will be analyzed separately. Decision and Soft-Decision lies in the number of input bits
per symbol required for decoding. HD decoding is performed
II. BACKGROUND with the use of a single quantization level for the bit sampling,
whereas for the SD detection 2N −1 decision thresholds are set
Error control coding (ECC), is a discipline of Information (N is the number of quantization bit). These intermediate levels
Theory, introduced by Claude Elwood Shannon in 1948 [6]. In between ”0“ and ”1“ indicate the reliability of a decision and
his landmark paper, Shannon showed that channel noise limits provide a sign of how far the signal is from the threshold
the transmission rate, not the error probability. Hence, it is crossing (Figure 2). In others words, even with as few as
possible to design an error-free communication system using 8 evenly distributed quantization levels, the latter approach
error control coding, where there is a maximum rate at which exhibits roughly a 1-2 dB coding-gain advantage over the
data can be transmitted over a noisy communication channel of hard-decisions (Table II). Nonetheless, soft-decision receivers
a specified bandwidth without errors. ECC aims at developing are not commonplace in optical communications, because of
methods for coding to achieve the detection of errors and the technological complications related to the very high transmis-
reconstruction of the original error-free data. Figure 1 shows sion rates of these networks, the high processing complexity
the block diagram of a data transmission system, where the of soft-decision codes and the cost of the required Analog-to-
channel encoder and decoder blocks are responsible for the Digital (A/D) converters.
encoding and decoding of the transmitted and received data
sequence, respectively. Shannon’s contribution was to prove
3 High confidence
the existence of such codes and therefore it was the starting
point of the study of error control coding. Since then much Moderate
'1'
'1'
2

research has been devoted to the optimization of encoding and 1 Low

decoding methods for error control in noisy environments.
Threshold0

−1 Low
'0'
'0' −2 Moderate

−3 High confidence
−4 −3 −2 −1 0 1 2 3 4

Fig. 2. Hard-Decision vs Soft-Decision decoding. A bipolar signal constel-

lation is assumed. The number of quantization levels refers to the sampling
of the received filtered signal and affects the code’s correcting performance.

The performance of a digital lightwave system is charac-

Fig. 1. Block diagram of a data transmission system. terized through the bit-error-rate (BER). Although the BER
can be defined as the number of errors made per second,
One of the most widely used error control methods is such a definition makes the BER bit-rate dependent. It is
Forward Error Correction. Just like most of the error control a customary to define the BER as the average probability
methods, the main idea behind FEC is to add some redundancy of incorrect bit identification. Therefore, a BER of 10−6
to the original message, which receivers can use to check corresponds to on an average one error per million bits [8].
the consistency of the delivered message and to recover the Additionally, the performance of a data-transmission code used
corrupted data. In that way though, a part of the effective on an additive white Gaussian-noise channel is expressed in
transmission bit-rate is limited. Thus, a key metric for these terms of the probability of channel symbol error as a function
codes is the “Code Rate“ R, which expresses the ratio of bit of Eb /N0 of the channel waveform. Convention requires that
rate without FEC to bit rate with FEC (R = k/n, for every k Eb is the average energy per data bit, whereas N0 denotes
bits of information, n bits of data will be sent, of which n − k the noise power spectral density (Eb /N0 is independent of
are redundant). data rate and bandwidth). It is common to judge the code,
In general, FEC can be categorized into block, convolutional not by the reduction in the bit error rate, but by the reduction
and a combination of these codes. To be more specific, FEC in the Eb /N0 needed to ensure the specified bit error rate.
codes with finite- and constant-length codewords are called The reduction in the required Eb /N0 at the same bit error
block-codes. Codewords of length n are formed by associating rate is called the coding gain. For example, a simple binary
n − k parity code-symbols with k input code-symbols. On communication system on an additive white Gaussian-noise
the other hand, convolutional codes apply over input-data in channel using the bipolar signal constellation operates at a
a continuous manner. Therefore, the concept of codewords is bit error rate of 10−5 at an Eb /N0 of 9.6 dB. By adding a
not as straightforward in this case. To be more specific, input sufficiently strong code to the communication system, the ratio
 3

Eb /N0 could be reduced. If the code requires only 6.6 dB for FEC codes and Optical Transport Network (OTN) standards
a bit error rate of 10−5 , then we say that the code has a coding in [7]–[12].
gain of 3 dB at a bit error rate of 10−5 (Figure 3) [9]. The
difference between coding gain and Net Coding Gain (NCG) III. FEC C ODES E VOLUTION
lies in the fact that the latter also takes into account the fact In this section the progress from first generation methods
that the bandwidth extension needed for the FEC scheme is to modern FEC schemes is briefly outlined. Generally, FEC
associated with increased noise in the receiver. For example, codes are classified in 3 generations and coding gains of
if there was a 7% rate expansion due to the FEC, the data rate approximately 6dB, 8dB and greater than 10dB characterize
had to increase by 7% in order to transmit both the data and them respectively. Figure 5 [13] depicts the FEC evolution over
the FEC [10]. the years and Table I [14] indicates their application fields.

− TABLE I
T YPICAL FEC S USED IN OTN.
Coded
Bit Error Rate (BER)

−
Capacity limit for rate R

Short-Reach Regional Long-Haul

Uncoded 2.5G G.709 or None G.709 or None G.709
−
10G G.709 or None G.975.1 2nd-Gen G.975.1 2nd-Gen
40G G.709 2nd- or 3rd-Gen 3rd-Generations
−
� �= � 100G G.709 3rd-Generations Soft FEC(18-22%OH)
�� −

8 As already mentioned, emphasis is given in this paper to

�� / � � 3rd-generation FEC codes with high correction abilities, cor-
responding to the needs of next-generation optical networks.
Fig. 3. Illustration of the notion of coding gain.
In high data rate optical communication systems, the challenge
is to implement codes with low redundancy that are capable of
Furthermore, the Q-factor (the logarithmic value of Q) correcting random and burst errors due to noise, dispersion and
is somewhat proportional to the optical signal-to-noise ra- inter-channel cross talk, with attention to complexity and cost.
tio (OSNR) for a binary optical communication system, as Table II [15] provides further information about the diversity
evidenced by the following equation Q(dB) = OSN R + in overhead and achieved Net Coding Gain (NCG) for both
10log(B0 /Bc ), where B0 is the optical bandwidth of the Hard-Decision and Soft-Decision decoding schemes. A brief
end device and Bc is the electrical bandwidth of the receiver description of each code generation follows as well.
filter. The form of the Q-factor is also given by the equation
Q = (VH −VL )/(σH +σL ) (Figure 4). Provided that the noise TABLE II
S HANNON ’ S THEORITICAL LIMITS FOR HD AND SD DECODING
follows Gaussian statistics, the Q-factor relates with√the BER ALGORITHMS .
via the following√relationship BER = erf c(Q/ 2)/2 ≈
exp(−Q2 /2)/(Q 2π). Overhead HD SD Additonal NCG
7% 10dB 11.10dB 1.10dB
15% 10.95dB 12.20dB 1.25dB
v(t)
25% 11.60dB 12.90dB 1.30dB

P[v(t) | vS = vH]
First-generation FEC: It uses conventional hard-decision
v(t) =Signal
+ Noise block codes, such as Hamming, BCH (Bose, Chaudhuri, and
σH vH Hocquenghem) and Reed-Solomon(RS) codes. RS codes [16],
which are the most common representatives of this era, are
Maximum Distance Separable (MDS), suitable to mitigating
γ burst-form errors due to their nonbinary structure. RS(255,
239) codes (each codeword contains 255 code word bytes, of
σL vL
which 239 bytes are data and 16 bytes are parity) have been
recommended for long-haul optical transmission as defined
P[v(t) | vS = vL] by ITU-T G.709 [17] and G.975 recommendations [18] on
their use for optical submarine communications. These codes
PROB[v(t)]
were successfully used in trans-Pacific and trans-Atlantic
communication systems and provided data rates as high as
Fig. 4. Probability of error for binary signaling. 5Gbit/s [13]. This code generation is generally expected to
γ S L yield a coding-gain near 6 dB at an output BER of 10−12 ,
Interested readers can find further introductory material on as evidenced by performance evaluation under ITU-T G.709.

γ
 4

This approach is necessary for any standards-compliant OTN expected to provide a net coding gain of over 10-11 dB at
framer but is not suitable for high data rates and longer reach a 10−15 output BER. Therefore, solid support is given to
applications, due to its limited correcting performance. ultra long-haul transmission of 40G, 100G, and even 400G
Second-generation FEC: Besides hard-decision based al- data. According to the most of the existing bibliography, the
gorithms, second-generation FEC codes achieve better coding 3rd generation of FEC codes includes only SD-FECs. Up to
gain with the use of concatenated codes alongside interleaving, date state-of-the-art methods are mainly based on either Turbo
iterative and convolutional decoding techniques. The concate- or Low-Density Parity-Check (LDPC) coding concepts and
nation scheme is based on the idea of increasing the Hamming iterative decoding. However, considering the fact that the codes
distance by forming inner and outer loops in the coding are usually judged for effectiveness based on their net coding
scheme and can be done in either a serial or parallel way. gain, it should be noted that there are some HD-FEC codes that
Namely, if the inner code loop has the minimum distance d, although their correcting performance is inferior compared to
the inner encoder, the channel, and the inner decoder can be this of SD-FECs, they are still suitable for 100G systems (they
considered as elements of the inner loop, and as such subject can be classified as 2.5th generation).
to the outer encoder/decoder. If the outer encoder enabled
the minimum distance D, the concatenated scheme results in
the minimum distance of at least D × d. This improvement
allows technology to support 10G and even 40G transmission · SD FEC
10
3 · Iterative

(Defined at post-FEC BER 10E-15)

systems [19]. In many cases, second-generation FECs yield a
· 100G+
decoding

NCG-Bit rate product (Gb/s)

· OH: up to 20%
net coding gain higher than 8 dB at an output BER equal
to 10−15 . Various Enhanced FEC (EFEC) techniques built · HD FEC · Gain> 10-11 dB
· Concatenated, · 40 nm ASIC
for higher gain found their way to standardization as ITU- 10
2
(15M Gates)
· 10G
iterative
T recommendation G.975.1 in 2004 [20]. G.975.1 describes
· OH < 7%
· Gain: 8-9 dB
nine techniques (I.1 through I.9), which can be used in
·
· · FPGA & 65 nm
HD FEC
transponders, regenerators, muxponders and switches at OTU-
·
BCH, RS
ASIC (< 5M
10 1
·
2 (10G) and OTU-3 (40G). However, equipment deployed at 2.5G
Gates)
·
OH < 7%
OTU-4 (100G) must properly utilize advanced FEC techniques
·
Gain < 8 dB
FPGA (0.1 M
[21]. LUTs)
Third-generation FEC: The use of coherent detection in
Year
optical communication systems and the rapid growth in in-
86 88 90 92 94 96 98 00 02 04 06 08 10 12 14 16
tegrated circuit technology make the application of Soft-
Decision FECs possible. While the mathematics behind soft-
Fig. 5. FEC evolution for optical networks.
decision FEC algorithms have been known for many years
and these codes are already popular in the wireless indus-
try, they are not yet widely used in optical communica- IV. S TATE - OF - THE - ART FEC CODES FOR N EXT
tions. The main reason for their limited use in optical net- G ENERATION O PTICAL N ETWORKS
works is that until recently numerous technology and ASIC
In current and next generation optical communications very
(Application-Specific Integrated Circuit) limitations prevented
powerful FEC codes are essential to enhance the transmission
their widespread hardware implementation. In other words,
reach. A minimum post-FEC BER of 10−12 or preferably
the computational intensive nature of these codes and the
10−15 is generally required. Currently, the most popular
technological constraints of the past did not allow the re-
schemes for FEC codes targeting 100G systems are based on
alization of such schemes for the very high transmission
Turbo, LDPC and interleaved-concatenated coding concepts.
rates of optical networks. Another inhibiting factor was the
We note that the construction of FEC codes has been a highly
unavailability of the required Analog-to-Digital (A/D) con-
active research area for a very long time and therefore we will
verters. The A/D converters appeared after the introduction of
describe only the most recent and efficient codes available
coherent detection systems and still remain costly. However, as
in the open literature. Information about the status of com-
micro-electronic technologies advance, research matures and
mercialization, patented solutions and the relative academic
new digital coherent receivers that integrate A/D converters
research is provided as well.
as a front end for demodulating signals are developed, it is
becoming more and more reasonable to consider SD-FEC
codes a rising and promising solution for next generation A. Two-iteration Concatenated BCH code:
optical networks [22]. Thus, in recent years intensive research The described concatenated BCH code [23] consists of
has been conducted towards iterative soft-decision decoding an outer BCH(3904,3820) and an inner BCH(2040,1952),
of various codes, seeking the highest possible coding gain. and has approximately 6.81% redundancy. On this decoder
It should be noted here that the real-time character of optical a low-complexity syndrome computation architecture and a
networks requires that the algorithm should be terminated after high-speed dual-processing pipelined simplified inversionless
a fixed properly chosen number of iterations (a higher number Berlekamp-Massey key equation solver architecture is applied.
of decoding iterations lead to lower throughput and larger High throughput, low complexity and high correction ability
delay). A SD-FEC scheme with 20% overhead is generally are achieved with the use of block interleaving methods and
 5

the development of the two-parallel processing method by con- • use the shortened bits for further checks.
verting the frame format. The two-parallel architecture needs As regards its hardware implementation, the algorithm used
the frame converter in order to parallelize two serial frames for the decoding of the individual BCH codes takes advantage
at input and output port of the two-iteration concatenated of the property that the shift of a BCH codeword is also a
BCH decoder. Additionally, in order to keep the hardware codeword. Therefore, for a codeword of length n, n rounds are
complexity low the number of iterations was selected to be required to get the decoding result. Interested readers can find
two, since the two-iteration scheme requires a lower number of more information about this code’s implementation complexity
inner and outer decoders as well as interleavers/deinterleavers in [24].
than the three-iteration scheme. Figure 6 depicts a block
diagram of the described two-iteration concatenated BCH
scheme that consists of BCH encoders, BCH decoders and
interleavers/deinterleavers.

Fig. 7. Turbo product code structure.

C. LDPC-Based Codes:
Fig. 6. Concatenated BCH Super FEC block diagram. In coding theory, a parity-check matrix of a linear block
code C is a matrix which describes the linear relations that
From post-layout simulation, the achieved NCG is 8.91dB at the components of a codeword must satisfy. If the parity-
an output BER of 10−15 and the latency is 11.8 µs. The maxi- check matrix has a low density of 1’s and the number of
mum clock frequency at which this architecture can operate is 1’s per column (wc : column weight) and per row (wr : row
430MHz in 90-nm CMOS technology and the data processing weight) are both constant, the code is said to be a regular
rate is 110 Gb/s. The total number of gates and area usage Low-Density Parity-Check (LDPC) code. If the parity-check
for the proposed two-iteration concatenated BCH decoder are matrix has low density, but the number of 1’s per row or
1,928,000 and 6.3mm2 respectively, excluding the RAM used column varies, the code is said to be an irregular LDPC
in the interleavers/deinterleavers, frame converters and FIFOs. code. The code rate R is given by the following equation:
The required memory size for the two-iteration concatenated R = (n − m)/n = 1 − wc /wr . The graphical representation of
BCH decoder is approximately 155kbytes including all FIFOs, LDPC codes, known as bipartite (Tanner) graph representation,
2 frame converters, 1 interleaver and 2 deinterleavers. is helpful in efficient description of LDPC decoding algorithms
(Figure 8). A bipartite (Tanner) graph is a graph whose nodes
may be separated into two classes (variable and check nodes),
B. Turbo Product Code with shortened BCH component
and where undirected edges may only connect two nodes not
codes:
residing in the same class. The Tanner graph of a code is
The HD-based ”Turbo Product Code” scheme, proposed drawn according to the following rule: check (function) node
in [24], has an overhead of 20% as recommended by OIF c is connected to variable node u whenever element hcu in
(Optical Internetworking Forum) and achieves 10dB NCG a parity check matrix H is an 1. In an m × n parity-check
after 8 iterations. Its structure is shown in Figure 7. For its matrix, there are m = n−k check nodes and n variable nodes.
construction, shortened BCH(391, 357) component codes in A closed path in a bipartite graph compromising l edges that
GF (211 ) are used. In each BCH component code, the first closes back on itself is called a cycle of length l. The shortest
1656 bits are fixed to 0’s, the middle 357 bits are information cycle in the bipartite graph is called the girth. The girth in-
bits and the last 34 bits are parity check bits. The product code fluences the minimum distance of LDPC codes, correlates the
is then shortened by removing all fixed 0’s and this returns a extrinsic log-likelihood ratios (LLRs) and, therefore, affects
product code with shortened BCH component codes. For the the decoding performance. Hence, the use of large girth LDPC
decoding, each shortened component code aims to correct up codes is generally preferable. The iterative schemes used for
to 3 errors. During one iteration both rows and columns are their decoding engage passing the extrinsic information back
decoded once. The standard procedure for the component code and forth among the check and the variable nodes over the
decoding algorithm consists of three steps: edges to update the distribution estimation. Conventionally,
• restore the BCH code, the sum-product algorithm (SPA) [25] or the modified min-
• decode BCH code, and sum algorithm (MSA) [26] is used. However, layered LDPC
 6

decoding schemes have recently attracted much attention in resulting in large circuits with high latency. Especially for
both academy and industry because they can effectively speed implementations according to the OTU4 framer, huge intercon-
up the convergence of LDPC decoding and thus reduce the nection speed between the OTU4 framer LSI and the coherent
required maximum number of decoding iterations. At present, ASIC is required [33]. Recently, D. Chang et al. [34] and D.
two kinds of layered decoding approaches have been proposed: A. Morero et al. [35], [36] have made significant progress in
row-layered decoding [27]–[30] and column-layered decoding the development of efficient single/non-concatenated LDPC
[30]–[32]. In row-layered decoding, the rows of the parity codes with low error floor and tolerable latency. In more
check matrix are grouped into layers and the message updating detail, Huawei’s D. Chang et al. proposed in 2011 a non-
is performed row layer by row layer, whereas in column- concatenated girth-8 QC-LDPC(18360, 15300) code exceed-
layered decoding this matrix is partitioned into column layers ing a net coding gain up to 11.3dB, Q-limit of 5.9dB and
and the update happens column layer by column layer. no error floor at a post-FEC BER of 10−15 . Influenced by
the compromise of performance and complexity , wc = 4
Variable nodes
(column weight) and wr = 24 (row weight) were selected.
�� � � � � � Moreover, progressive edge growth (PEG) algorithm was used
for the search of high girth QC-LDPC codes. Thanks to the use
of modified offset min-sum decoding algorithm with multi-
�= thresholds and modified layered decoding algorithm with 4
quantization bits the implementation complexity was kept
low [34]. Additionally, D. A. Morero et al. presented a non-
�� � � � concatenated QC-LDPC code with a standard 20% or better
Check nodes overhead providing a net effective coding gain greater than
10dB at a BER of 10−15 . In [35], [36] a design method of
Fig. 8. H-matrix and its corresponding Tanner graph. Rate R = (6 − 4)/6, parity check matrices with reduced number of short cycles,
row weight wr = 3, column weight wc = 2. a parallel decoder architecture and an adaptive quantization
post-processing technique are described. Besides these codes,
LDPC codes and especially Quasi-Cyclic LDPCs (QC- large girth block-circulant LDPCs with 20% redundancy were
LDPC) seem to be strong candidates for SD-FEC codes presented in [37], providing a net effective coding gain of
in next generation optical networks, due to their efficient 10.95dB at post-FEC BER of 10−12 , whereas Q. Yang et
parallelization and low complexity (required for 100G and al. showed in [38] an error free beyond 1 Tb/s QC-LDPC-
beyond optical communication). Despite their advantages, coded 16-QAM CO-OFDM transmission over 1040km stan-
these codes have a major drawback, which is the appearance dard single-mode fiber and proved its better performance
of error floor. Thus various approaches have been proposed compared to common 4-QAM transmission. However, the
for the elimination of this phenomenon. Figure 9 depicts three routing congestion problem and the increase of the global
different ways (no code concatenation, regular concatenation, wiring overhead (due to the feedback-loop architecture of
triple concatenation) of using LDPC codes for the construction an LDPC block code (LDPC-BC) decoder) should still be
of FEC frames suitable for 100 Gb/s digital coherent systems, considered for the implementation of such long codes (both of
with a 20% overhead, as recommended by the OIF. them limit the clock frequency and require larger space and
power consumption than the initial estimation). Nevertheless,
these two implementation drawbacks can be overcomed with
the use of LDPC convolutional codes (LDPC-CCs). As can
be seen in [39], the LDPC-CCs are suitable for pipelined
implementation and additionally their coding performance is
similar to this of longer LDPC-BCs. To be more specific,
the LDPC-CC(10032,4,24) achieves a Q-factor of 5.7dB and
a NCG of 11.5db at a post-FEC BER of 10−15 , as proved
by FPGA (Field-Programmable Gate Array) emulation (the
maximum number of iterations was set to 12).
Figure 9b presents another way to supress the unwanted
error floor by concatenating a SD-FEC with a HD code. In
their paper [40], T. Mizuochi et al. presented the concatenation
of LDPC(9216,7936) and RS(992,956) codes, achieving a
NCG of 9db at 10−13 with only 2-bit soft-decision and 4
Fig. 9. Types of FEC frame structure, including LDPC codes, for 100 Gb/s
iterations. In order to guarantee low circuit complexity and
digital coherent systems. high error correction performance, cyclic approximated δ-
minimum algorithm is proposed for the decoding procedure.
Figure 9a shows a single 20% LDPC implementation. In The value of row and column weight is 36 and 5, respec-
that case, while a good performance is expected, the effort to tively, whereas the girth of the LDPC code is 6. Under this
eliminate the error floor usually leads to very long codewords, concept, another high-performance low-complexity approach
 7

based on LDPC codes are the ”Concatenated QC-LDPC and ability of forming short cycles when compared to their binary
SPC Codes“, introduced by N. Kamiya and S. Shioiri (NEC counterparts and the increased number of nonbinary check
Corporation) [41]. The construction of these codes rely on and variable nodes, which ultimately improves the achievable
the concatenation of single-parity check (SPC) codes and decoding performance. Their main drawback though, is that
QC-LDPC codes of shorter lengths. According to the OTU4 they are characterized by increased decoding complexity, due
framer, an implementation with 20.5% OH is proposed. The to the large number of values [53]. For the construction of NB-
expected Q-limit and NCG of these codes, with 4 quantized QC-LDPC codes firstly finite fields are used for the generation
bits and 15 iterations are 5.8 dB and 10.4 dB at a BER of a large girth parity-check matrix for binary QC-LDPC
of 10−12 ( NCG=11.3 dB at a BER of 10−15 ), respectively. and then with the application of certain design criteria non
Naturally, a small degradation in the performance is noticed zero elements from the Galois field GF(q) replace the ”1“s.
with the reduction in the number of quantization levels or With the use of these codes (20% overhead) a net effective
in the maximum number of iterations. ”Spatially-coupled coding gain of 10.8 dB at a post-FEC BER of 10−12 can
codes“ is another class of LDPCs, which can be derived from be achieved [49]. Furthermore, in most recent publications,
QC-LDPC design [42]. Numerical simulation (Monte Carlo e.g. [54], NB-QC-LDPC based coded modulation schemes
simulation in an additive white Gaussian noise channel with are presented. Compared to binary interleaved LDPC based
QPSK modulation) [43] indicate a NCG of 12.0 dB at a BER coded modulation, the non-binary scheme provides higher
of 10−15 achieved by the code concatenation of spatially- coding gains and is advantageous due to the reduced system’s
coupled type irregular LDPC(38400, 30832) and BCH(30832, complexity and latency. In more detail, nonbinary LDPC-
30592), when the number of iterations was set to 32. This coded modulation provides several advantages compared to
scheme has a 25.5% redundancy and for its decoding the binary counterparts, when decoding is based on modified FFT-
simplified δ-min algorithm with 4 soft-decision bits was used. based q-ary SPA (MD-FFT-QSPA), as shown in [55]. Namely,
Another promising FEC scheme for 100Gb/s Optical Transport with MD-FFT-QSPA, the trade-off between the computational
Systems is the recently presented ”Concatenated Non-Binary complexity and coding gain improvement can be adjusted
LDPC and HD-FEC Code“ [44]. The proposed concatenated to suit the needs of the system under consideration. This
NB-LDPC(2304,2048) over GF (24 ) and RS(255,239) is com- particular scheme is also suitable for rate adaptation.
patible with OTU-4 frame structure and can provide a NCG
performance over 10.3 dB at a post-FEC BER 10−15 and over
D. Staircase Codes:
10.8 dB with enhanced HD-FEC in the outer code, with the
number of maximum iteration limited to 16. As far as its B. P. Smith et al. presented in their paper “Staircase Codes:
architecture modeling is concerned, between NB-LDPC and FEC for 100 Gb/s OTN” [56] a new class of high-rate
RS codes 2D-interleaving/deinterleaving buffers are located binary error correcting codes, whose construction combines
and Min-Max algorithm is preferred for decoding due to ideas from recursive convolutional and block coding. These
its advantageous VLSI implementation compared to FFT-BP codes are characterized by the relationship between successive
algorithms. matrices of symbols and can be interpreted as generalized
Figure 9c illustrates the concept of the so-called ”triple- LDPC codes with a systematic encoder and an indeterminate
concatenated FEC“ [45]–[48]. Unlike conventional concate- block length, which admits decoding algorithms with a range
nated codes, the proposed one combines an inner LDPC code of latencies. The low latency of their encoding process is
with a pair of concatenated hard decision based block codes guaranteed by the use of a frame mapper, whereas a range of
having 7% redundancy. The expected net coding gain at a strategies with varying latencies can be used for their decoding
10−15 output BER is 10.8 dB. Generally, these codes are due to the fact that these codes are naturally unterminated (i.e.
characterized by the following: their block length is indeterminate). That is, their decoding
can be accomplished in a sliding-window fashion, in which
• Inner Codes: Irregular QC-LDPC(4608,4080) the decoder operates on the received bits (binary case) corre-
• 20.5% total redundancy compliant with OIF standards, sponding to L consecutively received blocks Bi , Bi+1 ....Bi+L ,
which results in a transmission rate of 127.156 Gb/s. (Bi denotes an m-by-m matrix with elements either in GF(2)
• an OTU4V frame format compliant with ITU-T G.709. (binary case) or in Galois fields of higher orders (non-binary
• Decoding algorithm: Variable Offset Belief Propagation case)). A more detailed explanation of the encoding and
• 16 iterations decoding of these codes is provided in [56].
• straightforward circuit implementation via a well de- Generally, the relationship between successive blocks in a
signed parallelized pipelined architecture. staircase code satisfies the following relation: for any i >= 1,
T
Recently, nonbinary approaches are also attracting more each of the rows of the matrix [Bi−1 , Bi ] is a valid codeword.
and more attention. These codes are designed over higher- Figure 10 represents a “Staircase” visualization of staircase
order fields and achieve coding gains similar to or even better codes, in which the concatenation of the symbols in every
than binary LDPC codes, but for shorter codeword lengths row and every column in the staircase is a valid codeword.
[49], [50]. The higher performance of Nonbinary LDPC (NB- The expected NCG from the proposed ITU-T G.709-
LDPC) codes in comparison to binary ones was at first demon- compatible staircase code, with rate R = 239/255 is 9.41dB at
strated by Davey and Mackay in [51] and [52]. The main an output error rate of 10−15 as evidenced by a FPGA-based
factors that led to improved performance are the reduced prob- simulation.
 8

hough those shown in Fig. 1.

, they
are still not Layer nz


ack of y
Layer kz
, we propose 1 2 ky ny Layer k2
based on 1 RS code RS code … RS code … Layer 1

ponent Reed- x
2 … …
zed LDPC
TPCs
ons only,
kx RS code … … RS code
…
nz

ment of Electrical and Computer …

kz

Blvd., nx RS code … … RS code 2 z

il: ivan@ece.arizona.edu 1

erica,
Fig. 10. The “Staircase“ visualization of staircase codes. Fig. 1. A multidimensional TPC codeword example
Fig. 11. A 3-dimensional TPC, with RS component codes.

E. Multidimensional TPCS and GLPDC Codes with Compo-

nents RS Codes: the GLDPC code. Each sub-matrix Hj is derived from H1 by
random permutations πj−1 as given by Eq.3.
In “Multidimensional Turbo Product and Generalized
LDPC Codes with Component RS Codes Suitable for use in [H1T , ..., HW
T T
] (1)
Beyond 100 Gb/s Optical Transmission“ paper [57], two hard-
H1M T P C 0 0 ··· 0
 
decision decoding FECs suitable for next generation optical  0 H1M T P C 0 ··· 0 
networks are presented. The first scheme is based on mul- H1 = 

.. ..

 (2)
tidimensional turbo product codes (MTPCs) with component  . . 
MT P C
Reed-Solomon (RS) codes and the second one is based on 0 0 0 ··· HN t /N
generalized low-density parity-check (GLDPC) codes with
component RS or MTPC codes. Hj = πj−1 (H1 ), j = 2, ..., W (3)
The multidimensional turbo-product codes (MTPCs) are a The GLDPC code of rate 0.82, based on (255,239) and
generalization of the original turbo-product codes. The various (255,223) RS codes as components provides the net effective
methods to perform their encoding and decoding are divided coding gain of 9.6 dB at BER of 10−15 .
in the following three categories: Interested readers can find more information about how
• serial, these schemes are implemented and can be used along with
• fully parallel, and multilevel modulation formats in [57].
• partially parallel.
In serial version, only three different encoders/decoders are F. Super-Product BCH:
needed, each performing encoding/decoding in corresponding The super-product BCH (SP-BCH) code [58] is a true
dimension. The encoding/decoding latency of this scheme is product code designed for OTU4 100 G applications and
high, but the complexity is low. In fully parallel implemen- was originally introduced by Broadcom Corporation. It has a
tation, we need ny × nz encoders/decoders performing the standard 7% overhead and is based on hard decision decoding.
encoding/decoding in x-direction, nx × nz encoders/decoders The code consists of 960 BCH(987,956, t=3) (1-bit extended)
performing the encoding/decoding in y-direction; and nx × ny codes as row codes and 987 BCH(992, 960, t=3) (2-bit
encoders/decoders performing the encoding/decoding in z- extended) codes as column codes. The most likely dead pattern
direction. The encoding/decoding latency of this scheme is is the 4x4 square error pattern shown in Fig. 12, where 16 bit
low, while the encoding/decoding complexity is high. Thus, errors are located in the cross points between 4 arbitrary row
the partially parallel scheme was finally proposed for imple- codes and 4 arbitrary columns codes. A maximum number of
mentation, as a middle ground solution between these two 7 iterations are allowed at the decoding procedure.
schemes. The three-dimensional (3D)-TPC of rate 0.8, based Due to an advanced decoding method used for its decoding,
on (255,237) RS code as a component code, provides the net called “dynamic reverting”, it is expected to provide a net
effective coding gain of 9.3 dB at BER of 10−15 and is also coding gain up to 9.4 dB for an output BER of 10−15 . The
very efficient in dealing burst of errors due to intra-channel proposed code seems to have advantages, such as lower com-
nonlinearities. An example of 3-dimensional TPC, with RS putational complexity, better burst error correction capacity
component codes, is shown in Figure 11. and less required maximum iterations compared to other super
The GLDPC codes are either constructed using MTPC or FEC schemes [20]. However, its main drawback is that it has
RS components for less complex designs. The parity-check a long decoding latency due to large block size.
matrix H of a Boutros-like nonbinary GLDPC codes can be
partitioned into W sub-matrices H1 , ..., HW (Eq.1). H1 is a
block-diagonal matrix generated from an identity matrix by G. CI-BCH:
replacing the ones by the parity-check matrices HiM T P C of CI-BCH stands for Continuously Interleaved BCH and was
the constituent MTPCs of codeword-length N and dimension introduced by Vitesse Semiconductor Corp in 2010 [59]. It
Ki , i=1,2,...,Nt /N (Eq.2). Nt denotes the code word length of is an enhanced HD based FEC (eFEC) code relying on
 9

992 bits
32 bits
Row code 0: BCH(992, 960)
Row code 1: BCH(992, 960)
.....

.....
987 bits

.....

.....

.....
Row code 955: BCH(992, 960)
31 bits

C-990
C-991
C-0
C-1

Parity bits of column codes

Fig. 13. UEP-BCH FEC Frame Structure.

Fig. 12. SP-BCH Structure.

I. “Swizzle”:
PMC-Sierra introduced the “Swizzle“ Spiral Interleaved
interleaved BCH(1020,988) codewords and originally, it has Turbo Forward Error Correction code in order to provide
a standard 7% redundancy. Due to its structure, it is able to an efficient hard-decision FEC code suitable for 40G and
handle up to 1500 consecutive burst errors. Moreover, it is 100G DWDM systems. It offers 9.45dB of net efficient coding
characterized by low complexity decoding, as no Chien search gain with a 6.7% OTN overhead, 1.35dB better than the
or matrix inversion techniques are used and flaring correction second-generation FECs captured in G.975.1. In addition to
in most applications is not necessary. its great performance, the small overhead makes this solution
A net electrical coding gain, for bursty-error channel (not appealing. It can correct up to a random BER of 4.8E-3,
for AWGN channel model only), of 9.35 dB and 10.5 dB at corresponding to 9.45dB of net effective coding gain(2048
output BER of 10−15 is expected for 7% and 20% overhead consecutive errors at 40G and up to 6000 consecutive errors
respectively. The latency of the proposed codes varies from at 100G) and offers low latency.
1Mbits to 8Mbits (decoding latency in time is equal to Its design is inspired by LDPC and the codewords interlace
the decode latency in bits divided by the OTN line rate), in a spiral pattern(Figure 14 [14]), so that each codeword is
depending on the error correction capabilities of the used BCH covered by almost all the others nearby(maximum overlap
components (3- and 4-error correcting BCH respectively) [60]. of each pair of codewords is only 2 bits). This approach
makes trapping sets rare and eliminates the error floor, while
keeping the latency low. Moreover, it is characterized by tight
H. UEP-BCH: interleaving, parallel decoding and the use of an intelligent
In 2012 Mitsubishi Electric Corporation proposed a novel scheduler to allocate decode resources.
HD-FEC based on an unequal error protection (UEP) BCH
product code for OTU4 framers. Figure 13 [61] shows the
suggested FEC frame format for the UEP-BCH product code.
Their code consists of a BCH(1632,1588) x BCH(1280,1236)
+ BCH(1280,1225) with 7% overhead. According to simu-
lations a Q-limit of 8.35 dB and a NCG of 9.35 dB for a
post-FEC BER of 10−15 are expected, with no error floor
[61].
Generally, an enhanced FEC (EFEC) scheme for 100 Gb/s
OTN is a product code, constructed by two or more types of
element code and uses iterative HD decoding. The encoding
procedure of the proposed code succeeds in adjusting the
codeword and payload length to fit OTU4 and is summarized
in the following steps: Fig. 14. Swizzle interleave.
• use of a systematic code for wrapping by the OTUk
Frame, In 2011 PMC-Sierra published a white paper, called ”Swiz-
• removal of unequal parity-check bits, zle FEC for 40G and 100G Optical Transmission” [14],
• use of row-wise code as parity bits in order to reduce providing extended information about the construction and the
burst-error. performance of this code.
 10

J. TPC FEC IP Cores: efficient realization of such high-performance SD-FEC codes

Viasat has developed and offers third generation FEC codes remains a ’hot’ topic for research [65], [66].
exceeding ITU-T G.709 and G.975 submarine standards for Despite their weaker performance, HD-FEC codes are still
long haul (LH) and ultra long haul (ULH) link performance a reliable solution. As shown above, these codes meet the
requirements, providing a net coding gain ranging from 9.3dB needs of 100G and beyond systems, typically have a smaller
to 11.4 dB at a 10−15 output BER, depending on code type overhead and no costly A/D converters are required for their
(HD or SD) and overhead (7%-20%). In accordance with their implementation. From this family of codes, the best NCG at
research [62], [63], TPCs are considered the most efficient a 10−15 post-FEC BER is provided by CI-BCH 4 with a 20%
FEC codes for 100G systems, because of the following fea- redundancy [59], [60] and Turbo Product code with shortened
tures: BCH component codes [24], whereas CI-BCH 4 (7% OH),
Swizzle [14] and Staircase codes [56] achieve the greatest
• high coding gain, performance for a standard 7% overhead.
• high and deterministic minimum distance / excellent From the class of SD-FEC codes, the spatially-coupled type
asymptotic performance / no error floors down to 10−15 LDPC code [43] exhibits the highest NCG at a 10−15 post-
operational BERs, FEC BER. However, its overhead is at least 5% higher than
• fast convergence/small number of decoding iterations this of the other described FEC codes. LDPC-CCs [39] and
leading to lower complexity and lower latency, and Viasat’s TPCs [62], [63] are the two implemented schemes
• high tolerance to soft-input resolution, so few bits of ADC with the greatest correcting performance with a 20% overhead
input resolution are required. at a post-FEC BER of 10−15 . Some of the other proposed
As far as decoder’s architecture is concerned, its top-level LDPC-based codes have also similar or even better perfor-
block diagram consists of a deinterleaver, a pre-processor, mance (e.g. Large-Girth LDPC [37], [49] or Non-Binary QC-
SISO iterations, and a post-processor. More specifically, the LDPCs [49], [64]), as evidenced by Table III, but they are
proposed decoder uses four copies of the SISO decoding not yet sufficiently implemented onto hardware. Especially
engine and is built taking advantage of pipelined architecture for the case of Soft-Decision codes, besides coding gains,
and high parallelism. The decoding procedure terminates after attention should be paid to both latency and complexity
four iterations, keeping latency and complexity low, while of the proposed schemes. These factors are implementation
providing the required NCG. dependant and affect the delay and the power consumption of
the system, thus they are considered critical. For this reason,
LDPC and mostly QC-LDPC codes have recently started to
V. C OMPARISON
attract more and more interest, as they come along with an
In the previous sections, not only we introduced the reader efficient architecture and are characterized by parallelism in
to error control coding and FEC codes, but also described their decoding and computational simplicity. Towards this direction,
evolution and standardization through the years, and presented there is a high motivation to use single LDPCs with low
the state-of-the-art. In this section, we summarize the benefits error floor (e.g. [34]–[36]), instead of concatenated codes.
and drawbacks of each scheme and provide a qualitative As compared to non-concatenated solutions, the latter brings
comparison between them. Table III forms a synopsis of the on additional drawbacks, such as increased complexity and
FEC codes described above and includes statistics about their latency, since the concatenation scheme requires an outer code
Net Coding Gain, Overhead (OH), post-FEC BER and the and an additional interleaver (deinterleaver) to de-correlate the
number of quantized bits in case of Soft-Decision decoding, data sequences between the component codes. However, the
whether they are available. Additionally, Figure 15 depicts length of these “single” codes has to be selected carefully,
this table for better understanding, where Hard-Decision based considering both the elimination of the unwanted error floor
FECs are represented with circles and Soft-Decision based and the routing and latency of the implemented design. Having
FECs with rhombuses. As already mentioned, all the included this trade-off in mind non-binary approaches were recently
solutions target at 100G transmission and beyond. As far proposed as they come along with an efficient hardware
as post-FEC BER is concerned, a minimum of 10−12 or implementation and an effective integration with advanced
preferably 10−15 is generally required. modulation formats (coded-modulation) [54], [55]. Definitely,
A first conclusion from this comparison is the confirmation in the case of SD-based FECs another factor that should be
of the greater correcting performance of SD-FEC codes. The considered is the number of quantization bits. Typically, an
SD-FECs take advantage of the additional confident bits increase in the number of quantization levels leads to more
provided by the A/D converters and manage to outperform expensive solutions, while we have noticed that their reduction
the conventional HD-FECs. Such an improvement in NCG is causes degradation in the correcting performance. Considering
very important since it gives us the opportunity to increase this trade-off, SD-FEC codes with only 2 quantization bits,
the un-regenerated optical propagation distance. In practice, such as the one presented in [40], are in many cases a favorable
the 1-2 dB of coding gain translates into 20-40% rise in total solution. It should be also noticed here that the implementation
achievable distances, which is a substantial improvement at of SD-FEC codes under this concept is possible even without
100Gps. However, this happens at the expense of resources the use of A/D converters by taking advantage of the soft-
as the SD-FECs are generally characterized by higher imple- decision optical front-end proposed in [67], [68], leading to
mentation complexity than HD-FECs. Hence, the hardware- low-power solutions.
 11

TABLE III
S TATE - OF - THE - ART AND BEYOND FEC CODES C OMPARISON

Name Ref. HD SD Appr. Overhead NCG(dB) post-FEC BER Implementation

FPGA ASIC
Swizzle [14] X 6.7% 9.45 10−15 X NA
Staircase [56] X 7% 9.41 10−15 X NA
MTPC [57] X 20% 9.30 10−15 NA NA
GLDPC [57] X 20% 9.60 10−15 NA NA
SP-BCH [58] X 7% 9.40 10−15 X 40 nm
Two-iter. conc. BCH [23] X 6.81% 8.91 10−15 NA NA
UEP-BCH [61] X 7% 9.35 10−15 NA 40 nm
TPC with shortened BCH comp. [24] X 20% > 10 10−15 NA NA
CI-BCH 3 [59], [60] X 6.7%/12%/20% 9.35/9.90/10.30 10−15 X NA
CI-BCH 4 [59], [60] X 6.7%/12%/20% 9.55/10/10.50 10−15 X NA
TPC [62], [63] X 7%/15% 9.30/9.80 10−15 X 150-40 nm
TPC [62], [63] X 7%/15%/20% 10.30/11.10/11.40 10−15 X 150-40 nm
Conc. QC-LDPC and SPC [41] 4 bits 20.5% 10.4/11.3 10−12 /10−15 X NA
Single QC-LDPC [34] 4 bits 20% 11.3 10−15 X NA
LDPC-CC. [39] 4 bits 20% 11.5 10−15 X NA
Non-Conc. FEC [35], [36] 5 bits 20% 11,3 10−15 X NA
Conc. LDPC and RS [40] 2 bits 20% 9 10−13 X NA
Spatially-coupled LDPC [43] 4 bits 25.5% 12 10−15 NA NA
Conc. NB-LDPC and RS [44] 5 bits 20.5% 10.8 10−15 NA NA
Large-Girth LDPC [37], [49] 4 bits 20% 10.95 10−12 NA NA
NB-QC-LDPC [49], [64] X 20% 10.80 10−12 NA NA
Triple Conc. FEC [45]–[48] 3 bits 20.5% 10.80 10−15 X NA

VI. C ONCLUSIONS AND F UTURE O UTLOOK to-noise ratio it requires to achieve a certain bit error rate.
Hence, the development of integrated solutions (e.g. irregular
In this paper we have provided a thorough survey of the structured LDPC codes to further improve NCG) suitable to
associated open literature that is related to high-performance improve the spectral efficiency of these channels with less
forward error correction codes suitable for next generation power requirements (for the same amount of redundancy and
optical networks targeting 100G and above. We have com- the same BER) will be greatly needed in the near future.
menced our discourse by outlining the fundamentals and the Finally, considering the dynamic structure of next generation
basic principles of error correction codes. Furthermore, we flexible networks [72], attention should also be paid to the
gave a historical overview of their progress, standardization hardware realization of these schemes both due to their high
and application fields. Following this preliminary foundation, implementation complexity and the need to adapt effectively
we proceeded to provide a description of state-of-the-art FEC in different signal qualities, power requirements and expected
codes recommended both by academia and industry. Because transmission rates.
different application systems have different decoding perfor-
mance, latency, power and cost requirements, FEC systems
with various transmission overhead, implementation complex- R EFERENCES
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 12

25 *post-FEC BER 10E-15

*post-FEC BER 10E-13 Spatially-coupled LDPC
*post-FEC BER 10E-12 NB-LDPC&RS
HD-FEC Triple Conc. QC-LDPC&SPC
SD-FEC CI-BCH4 Non-Conc.
MTPC
20 LDPC-CC

LDPC&RS GLDPC CI-BCH3 TPC-SD

Single QC-LDPC
TPC - short BCH
Overhead (%)

Large- girth LDPC

NB-QC-LDPC
TPC-HD TPC-SD
15

CI-BCH4
CI-BCH3

10 UEP-BCH
Two-iter. conc BCH SP-BCH
TPC-HD Staircase
TPC-SD
CI-BCH3 Swizzle CI-BCH4
5
7 8 9 10 11 12 13
NCG (dB)
Fig. 15. State-of-the-art and beyond FEC codes comparison

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 13

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[65] G. Tzimpragos, C. Kachris, D. Soudris and I. Tomkos, “A Low- Ivan B. Djordjevic is a tenured Associate Professor
Complexity Implementation of QC-LDPC Encoder in Reconfigurable in the ECE Department of College of Engineering of
Logic,” in Field Programmable Logic and Applications (FPL), 2013 University of Arizona, with a joint appointment in
23rd International Conference on, Sept 2013, pp. 1–4. the College of Optical Sciences. Prior to joining the
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Algorithm and FPGA Design for the Min-Search of LDPC Decoders,” West of England and University of Bristol, Bristol,
in the 28th IEEE International Symposium on Parallel Distributed UK; Tyco Telecommunications, Eatontown, USA;
Processing (IPDPS), May 2014, to appear. National Technical University of Athens, Athens,
[67] M. N. Sakib, V. Mahalingam, W. J. Gross, and O. Liboiron-Ladouceur, Greece; and State Telecommunication Company
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nication Systems,” J. Opt. Commun. Netw., vol. 3, no. 6, pp. 533–541, he was also with Technische Universitt Darmstadt,
Jun 2011. Darmstadt, Germany. Dr. Djordjevic is an author/co-author of four books,
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ings of the IEEE, to appear.
Milorad Cvijetic is currently Professor at University
of Arizona - College of Optical Sciences in Tuc-
son, Arizona. Prior joining University of Arizona
he served as Vice President and Chief Technol-
ogy Strategist at NEC Corporation of America in
Herndon, Virginia. In his 30+ years long career
mostly in the area of optical communications and
networking, Dr. Cvijetic has been one of pioneers
Georgios Tzimpragos earned his Diploma degree in the area of high-speed optical systems and coher-
in Electrical and Computer Engineering from Na- ent detection technologies, as well as the industry
tional Technical University of Athens (NTUA) in leader responsible for advanced optical networking
2012. Since then, he has been a member of the technologies. He published numerous technical papers, and is the author of
”High Speed Networks and Optical Communica- four books and author/coauthor of twelve US patents, all related to optical
tions” group of Athens Information Technology communications and networking. His current interests include high-speed
(AIT) and NTUA’s Microprocessors and Digital Sys- DWDM optical transmission systems and networking, optical access networks,
tems Lab, working under EU-funded projects as a optical-wireless systems, and quantum communications.
research engineer. His research interests include em-
bedded systems, reconfigurable computing (FPGAs),
network processing and computer architecture.

Christoforos Kachris is a senior researcher at

Athens Information Technology (AIT), Greece. He
obtained his Ph.D. in Computer Engineering from
Delft University of Technology, The Netherlands
in 2007, and the diploma and the M.Sc. in Elec- Dimitrios Soudris received the Diploma and Ph.D.
tronic and Computer Engineering from the Techni- degrees in electrical engineering from the University
cal University of Crete, Greece in 2001 and 2003 of Patras, Patras, Greece, in 1987 and 1992. Since
respectively. From February 2009 till August 2010 1995 and for 13 years, he has served as a Professor
he was a visiting assistant professor at the University with the Department of Electrical and Computer En-
of Crete, Greece and associate researcher at the gineering, Democritus University of Thrace, Avdira,
Institute of Computer Science in the Foundation for Greece. He is currently working as an Associate
Research and Technology (FORTH) working in the HiPEAC NoE and the Professor with the School of Electrical and Com-
SARC IP European research projects. In 2006 he was a research intern at puter Engineering, National Technical University of
Xilinx Research Labs, San Jose, CA, working at the Networks Group. His Athens, Athens, Greece. His research focuses on
research interests are in the area of reconfigurable computing, multi-core embedded systems design, low power VLSI design,
FPGAs, network processing, computer architecture and embedded systems and reconfigurable architectures. He has published more than 300 papers
and is the coauthor/coeditor of six Kluwer/Springer books. He has served
as a General/Program Chair for PATMOS 1999 and PATMOS 2000 and
IFIP-VLSISOC 2008. Dr. Soudris is a member of the VLSI Systems and
Applications Technical Committee of IEEE CAS and HiPEAC
 15

Dr. Ioannis Tomkos is with the Athens Information

Technology Center (AIT), since Sep 2002. He was
elected as Adjunct Faculty at the College of Optical
Sciences of University of Arizona (2013 - now), at
the Department of Electrical and Computer Engi-
neering at University of Cyprus (2013 - now) and at
the Information Networking Institute of Carnegie-
Mellon University, USA (2002 - 2010). At AIT
his Research Group was/is involved in over 25 EU
funded research projects and in national and industry
projects, within which Dr. Tomkos has a consortium-
wide leading role (including Project Leader/Technical Manager of 8 major
EU projects). Based on his innovative research ideas, he has attracted for
AIT an amount of funding in excess of 7.5M Euros. He is a Fellow of the
IET (2010) and OSA (2012) for ”outstanding contributions to the field of
transparent optical networking”. He was also elected Distinguished Lecturer of
IEEE Communications Society (2007). He has co-authored over 550 articles
(including over 330 archival through IEEE Xplore) and has received over
4000 citations to his work. He is the co-recipient of the 2014 IEEE/OSA
JLT Best Paper Award. He served as the Chair of the ”Optical Networking”
Technical Committee of IEEE Communications Society and a member of
the IEEE ComSocs Techical Activities Council. He was also Chairman of
the IFIP Group on Photonic Networking and the Chairman of the ”Optical
Communications” Group at OSA. He is currently the Chair of the Greek
chapter of IEEE Photonics Society.