AS4LC1M16E5

3V 1M×16 CMOS DRAM (EDO)

Features
• Organization: 1,048,576 words × 16 bits • Read-modify-write
• High speed • TTL-compatible, three-state DQ
- 50/60 ns RAS access time • JEDEC standard package and pinout
- 20/25 ns hyper page cycle time - 400 mil, 42-pin SOJ
- 12/15 ns CAS access time - 400 mil, 44/50-pin TSOP 2
• Low power consumption • 3V power supply (AS4LC1M16E5)
- Active: 500 mW max (-60) • 5V tolerant I/Os; 5.5V maximum VIH
- Standby: 3.6 mW max, CMOS DQ • Industrial and commercial temperature available
• Extended data out
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh

Pin arrangement
62- 7623 Pin designation
V&& 1 50 V66 Pin(s) Description
Vcc 1 42 V66 DQ1 2 49 DQ16
DQ1 2 41 DQ16 DQ2 48 DQ15
DQ2 3 40 DQ15 3 A0 to A9 Address inputs
DQ3 4 39 DQ14 DQ 4 47 DQ14
'4 5 38 DQ13 DQ4 5 46 DQ13 RAS Row address strobe
Vcc 6 37 V66 V&& 6 45 V66
DQ5 7 36 DQ12 DQ5 7 44 DQ12
DQ6 8 35 DQ11 DQ6 8 43 DQ11
DQ1 to DQ16 Input/output
DQ7 9 34 DQ10 DQ7 9 42 DQ10
DQ8 10 33 DQ9 DQ8 10 41 DQ9
OE Output enable
NC 11 32 NC
NC 11 40 NC
NC 12 31 LCAS WE Write enable
WE 13 30 UCAS
RAS 14 29 OE
NC 15 28 A9
UCAS Column address strobe, upper byte
NC 16 27 A8 NC 15 36 NC
A0 17 26 A7 NC 16 35 LCAS LCAS Column address strobe, lower byte
A1 18 25 A6 WE 17 34 UCAS
A2 19 24 A5
RAS 18 33 OE VCC Power
A3 20 23 A4
Vcc 21 22 V66 NC 19 32 A9
NC 20 31 A8 VSS Ground
A0 21 30 A7
A1 22 29 A6
A2 23 28 A5
A3 24 27 A4
V&& 25 26 V66

Selection guide
Symbol -50 -60 Unit
Maximum RAS access time tRAC 50 60 ns
Maximum column address access time tAA 25 30 ns
Maximum CAS access time tCAC 12 15 ns
Maximum output enable (OE) access time tOEA 13 15 ns
Minimum read or write cycle time tRC 80 100 ns
Minimum hyper page mode cycle time tHPC 20 25 ns
Maximum operating current ICC1 140 130 mA
Maximum CMOS standby current ICC5 1.0 1.0 mA
.

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Functional description
The AS4LC1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16
bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia and router switch applications.
The AS4LC1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column
addresses prior to xCAS assertion. The AS4LC1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access.
Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains
active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance
and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and xCAS going high.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
• RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
• CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4LC1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP 2 packages, respectively. The AS4LC1M16E5 device
operates with a single power supply of 3V ± 0.3V and provides TTL compatible inputs and outputs.

Logic block diagram

controller

VCC Data
Refresh

Column decoder
DQ DQ1 to DQ16
GND buffers
Sense amp

RAS RAS clock

generator A0
A1 OE
Address buffers

A2
Row decoder

A3 1024 × 1024 × 16
CAS clock A4
UCAS A5 Array
generator
LCAS A6 (16,777,216)
A7
A8
A9 Substrate bias
WE clock generator
WE generator

Recommended operating conditions1

Parameter Symbol Min Nominal Max Unit
VCC 3.0 3.3 3.6 V
Supply voltage
GND 0.0 0.0 0.0 V
VIH 2.0 – 5.5 V
Input voltage 2
VIL –0.5 – 0.8 V
Commercial 0 – 70
Ambient operating temperature TA °C
Industrial -40 – 85

1 Recommended operating conditions apply throughout this document unless otherwise specified.
2 VIL min -3.0V for pulse widths less than 5 ns.

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Absolute maximum ratings

Parameter Symbol Min Max Unit
Input voltage VDQ -1.0 +5.5 V
Power supply voltage VCC -1.0 +4.0 V
Storage temperature (plastic) TSTG -65 +150 °C
Soldering temperature × time TSOLDER – 260 × 10 oC × sec
Power dissipation PD – 0.6 W
Short circuit output current Iout – 50 mA

Truth table
Addresses
Operation RAS LCAS UCAS WE OE tR tC DQ0 to DQ15 Notes
Standby H H to X H to X X X X X High-Z
Word read L L L H L ROW COL Data out
Lower byte,
Lower byte read L L H H L ROW COL
Upper byte, Data out
Lower byte,
Upper byte read L H L H L ROW COL
Data out, Upper byte
Word (early) write L L L L X ROW COL Data in
Lower byte, Data in,
Lower byte (early) write L L H L X ROW COL
Upper byte, High-Z
Lower byte, High-Z,
Upper byte(early) write L H L L X ROW COL
Upper byte, Data in
Read write L L L H to L L to H ROW COL Data out, Data in 1,2
1st cycle L H to L H to L H L ROW COL Data out 2
EDO read 2nd cycle L H to L H to L H L n/a COL Data out 2
Any cycle L L to H L to H H L n/a n/a Data out 2
1st cycle L H to L H to L L X ROW COL Data in 1
EDO write
2nd cycle L H to L H to L L X n/a COL Data in 1
1st cycle L H to L H to L H to L L to H ROW COL Data out, Data in 1,2
EDO read write
2nd cycle L H to L H to L H to L L to H n/a COL Data out, Data in 1,2
RAS only refresh L H H X X ROW n/a High Z
CBR refresh H to L L L H X X X High Z 3
Self refresh H to L L L H X X X High Z 3

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DC electrical characteristics
-50 -60
Parameter Symbol Test conditions Min Max Min Max Unit Notes
0V ≤ Vin ≤ VCC (max)
Input leakage current IIL -2 +2 -2 +2 µA
Pins not under test = 0V
Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ VCC (max) -2 +2 -2 +2 µA
Operating power RAS, UCAS, LCAS, Address cycling;
ICC1 – 140 – 130 mA 4,5
supply current tRC=min
TTL standby power RAS = UCAS = LCAS ≥ VIH,
ICC2 – 2.0 – 2.0 mA
supply current all other inputs at VIH or VIL
Average power supply
RAS cycling, UCAS = LCAS ≥ VIH,
current, RAS refresh ICC3 – 130 – 120 mA 4
tRC = min of RAS low after XCAS low.
mode or CBR
EDO page mode average RAS = VIL, UCAS or LCAS,
ICC4 – 100 – 90 mA 4, 5
power supply current address cycling: tHPC = min
CMOS standby power RAS = UCAS = LCAS = VCC - 0.2V,
ICC5 – 1 – 1 mA
supply current F=0
VOH IOUT = -2.0 mA 2.4 – 2.4 – V
Output voltage
VOL IOUT = 2.0 mA – 0.4 – 0.4 V
CAS before RAS refresh
ICC6 RAS, UCAS or LCAS cycling, tRC = min – 130 – 120 mA
current
RAS = UCAS = LCAS ≤ 0.2V,
WE = OE ≥ VCC - 0.2V,
Self refresh current ICC7 – 0.5 – 0.5 mA
all other inputs at 0.2V or
VCC - 0.2V

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AC parameters common to all waveforms

-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tRC Random read or write cycle time 80 – 100 – ns
tRP RAS precharge time 30 – 40 – ns
tRAS RAS pulse width 50 10K 60 10K ns
tCAS CAS pulse width 8 10K 10 10K ns
tRCD RAS to CAS delay time 15 35 15 43 ns 9
tRAD RAS to column address delay time 9 25 10 30 ns 10
tRSH CAS to RAS hold time 10 – 10 – ns
tCSH RAS to CAS hold time 40 – 50 – ns
tCRP CAS to RAS precharge time 5 – 5 – ns
tASR Row address setup time 0 – 0 – ns
tRAH Row address hold time 8 – 10 – ns
tT Transition time (rise and fall) 1 50 1 50 ns 7,8
tREF Refresh period – 16 – 16 ms 6
tCP CAS precharge time 8 – 10 – ns
tRAL Column address to RAS lead time 25 – 30 – ns
tASC Column address setup time 0 – 0 – ns
tCAH Column address hold time 8 – 10 – ns

Read cycle
-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tRAC Access time from RAS – 50 – 60 ns 9
tCAC Access time from CAS – 12 – 15 ns 9,16
tAA Access time from address – 25 – 30 ns 10,16
tRCS Read command setup time 0 – 0 – ns
tRCH Read command hold time to CAS 0 – 0 – ns 12
tRRH Read command hold time to RAS 0 – 0 – ns 12

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Write cycle
-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tWCS Write command setup time 0 – 0 – ns 14
tWCH Write command hold time 10 – 10 – ns 14
tWP Write command pulse width 10 – 10 – ns
tRWL Write command to RAS lead time 13 – 15 – ns
tCWL Write command to CAS lead time 8 – 10 – ns
tDS Data-in setup time 0 – 0 – ns 15
tDH Data-in hold time 8 – 10 – ns 15

Read-modify-write cycle
-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tRWC Read-write cycle time 113 – 135 – ns
tRWD RAS to WE delay time 67 – 77 – ns 14
tCWD CAS to WE delay time 32 – 35 – ns 14
tAWD Column address to WE delay time 42 – 47 – ns 14

Refresh cycle
-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tCSR CAS setup time (CAS-before-RAS) 5 – 5 – ns 6
tCHR CAS hold time (CAS-before-RAS) 8 – 10 – ns 6
tRPC RAS precharge to CAS hold time 0 – 0 – ns
CAS precharge time
tCPT 10 – 10 – ns
(CBR counter test)

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Hyper page mode cycle

-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tCPWD CAS precharge to WE delay time 45 – 52 – ns
tCPA Access time from CAS precharge – 28 – 35 ns 16
tRASP RAS pulse width 50 100K 60 100K ns
tDOH Previous data hold time from CAS 5 – 5 – ns
tREZ Output buffer turn off delay from RAS 0 13 0 15 ns
tWEZ Output buffer turn off delay from WE 0 13 0 15 ns
tOEZ Output buffer turn off delay from OE 0 13 0 15 ns
tHPC Hyper page mode cycle time 20 – 25 – ns
tHPRWC Hyper page mode RMW cycle 47 – 56 – ns
tRHCP RAS hold time from CAS 30 – 35 – ns

Output enable
-50 -60
Symbol Parameter Min Max Min Max Unit Notes
tCLZ CAS to output in Low Z 0 – 0 – ns 11
tROH RAS hold time referenced to OE 8 – 10 – ns
tOEA OE access time – 13 – 15 ns
tOED OE to data delay 13 – 15 – ns
tOEZ Output buffer turnoff delay from OE 0 13 0 15 ns 11
tOEH OE command hold time 10 – 10 – ns
tOLZ OE to output in Low Z 0 – 0 – ns
tOFF Output buffer turn-off time 0 13 0 15 ns 11,13

Self refresh cycle

-50 -60
Std Symbol Parameter Min Max Min Max Unit Notes
RAS pulse width
tRASS 100 – 100 – µs
(CBR self refresh)
RAS precharge time
tRPS 90 – 105 – ns
(CBR self refresh)
CAS hold time
tCHS 8 – 10 – ns
(CBR self refresh)

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AC test conditions
- Access times are measured with output reference levels of +3.3V
VOH = 2.0V and VOL = 0.8V,
VIH = 2.0V and VIL = 0.8V R1 = 828Ω
- Input rise and fall times: 2 ns Dout
50 pF* R2 = 295Ω

GND
Equivalent output load
*including scope
and jig capacitance

Notes
1 Write cycles may be byte write cycles (either LCAS or UCAS active).
2 Read cycles may be byte read cycles (either LCAS or UCAS active).
3 One CAS must be active (either LCAS or UCAS).
4 ICC1, ICC3, ICC4, and ICC6 are dependent on frequency.
5 ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
6 An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
7 AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load as described in AC test conditions below.
8 VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
9 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the speci-
fied tRCD (max) limit, then access time is controlled exclusively by tCAC.
10 Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the spec-
ified tRAD (max) limit, then access time is controlled exclusively by tAA.
11 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
12 Either tRCH or tRRH must be satisfied for a read cycle.
13 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from ris-
ing edge of RAS or CAS, whichever occurs last.
14 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected
cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
15 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
16 Access time is determined by the longest of tCAA or tCAC or tCPA
17 tASC ≥ tCP to achieve tPC (min) and tCPA (max) values.
18 These parameters are sampled and not 100% tested.

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Key to switching waveforms

Rising input Falling input Undefined output/don’t care

Read waveform
tRC
tRAS
tRCD tRSH tRP
RAS
tCSH
tCRP tASC tCAH
tRCS tCAS
UCAS
LCAS
tRAD tRAL
tASR tRAH
Address Row address Column address
tRRH
tRCH
WE
tWEZ
tROH tROH
OE
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC tREZ
tCLZ
DQ Data out
tOLZ

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Upper byte read waveform

tRC
tRAS tRP
RAS
tRCD tRSH
tCSH tCRP
tCRP tCAS
UCAS
tCRP tRPC

LCAS
tRAH
tRAD tRAL
tASR tASC tCAH
Address Row Column
tRCH
tRCS tRRH
WE
tROH tWEZ
OE
tOEA tREZ
tOLZ
tRAC
tOEZ
tAA
tCAC
tCLZ tOFF
Upper DQ Data out

Lower DQ

Lower byte read waveform

tRC
tRAS tRP
RAS
tRCD tRSH
tCSH tCRP
tCRP tCAS
LCAS
tCRP tRPC
UCAS
tRAH tASC
tRAD tRAL
tASR tCAH
Address Row Column
tRCH
tRCS tRRH
WE
tROH tWEZ
OE
Upper DQ
tOEA tREZ
tOLZ
tRAC
tOEZ
tAA
tCAC
tCLZ tOFF
Lower DQ Data out

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Early write waveform

tRC
tRAS tRP
RAS
tCSH
tRSH
tCRP tRCD tCAS
UCAS,
LCAS tRAD tRAL
tASC
tASR tRAH tCAH
Address Row address Column address

tCWL
tRWL
tWP
tWCS tWCH
WE

OE

tDS tDH
DQ Data in

Upper byte early write waveform

tRC
tRAS tRP
RAS
tASR tRAD
tRAH tRAL
Address Row address Column address
tASC tCAH
tRCD tRSH
tCSH
tCRP tCAS tCRP
UCAS
tCRP tRPC
LCAS
tCWL
tWCS tWCH
tRWL

tWP
WE
OE
tDS tDH
Upper DQ Data in

Lower DQ

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Lower byte early write waveform

tRC
tRAS tRP
RAS
tRAD tRAL
tASR tRAH
Address Row address Column address
tCRP tRPC
UCAS
tASC tCAH
tRCD tCAS
tCSH
tCRP tRSH tCRP
LCAS
tRWL
tCWL
tWCS tWCH
tWP
WE
OE
Upper DQ

tDS tDH
Lower DQ Data in

Write waveform OE controlled

tRC
tRAS tRP

RAS
tCSH
tRSH
tCRP tRCD tCAS
UCAS,
LCAS tRAL

tRAD tASC
tASR tRAH tCAH
Address Row address Column address

tRWL
tCWL
tWP

WE
tOEH

OE
tDS
tOED tDH

DQ Data in

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Upper byte write waveform OE controlled

tRC
tRAS tRP
RAS
tRAD tRAL

tASR tRAH
Address Row address Column address

tCSH
tRCD tRSH
tCAH
tCRP tASC tCAS tCRP
UCAS
tCRP tRPC
LCAS
tCWL
tRWL
tWP
WE
tOEH
OE
tDS tDH
Upper DQ Data in
tOED
Lower DQ

Lower byte write waveform OE controlled

tRC
tRAS tRP

RAS
tRAD
tASR
tRAH tRAL

Address Row address Column address

tCAH
tRCD tCAS
tCSH
tCRP tACS tRSH tCRP
LCAS
tCRP tRPC
UCAS
tCWL
tRWL
tWP

WE
tOEH

OE
Upper DQ
tDS tDH
Lower DQ Data in

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Read-modify-write waveform
tRWC
tRAS tRP

RAS
tCAS
tCRP tRCD tRSH
tCSH

UCAS
tAR
LCAS
tRAL
tRAD tASC
tASR tRAH tCAH

Address Row address Column address

tRWD tRWL
tAWD tCWL
tRCS tCWD tWP

WE tOEA tOED
tOEZ

OE
tRAC
tAA
tCAC tDS
tCLZ tDH

DQ Data out Data in

tOLZ

Upper byte read-modify-write waveform

tRWC
tRAS tRP
RAS
tCSH
tRCD tCAS
tCRP tRSH tCRP
UCAS
tCRP tRPC
LCAS
tRAD tACS
tASR tRAL
tRAH tCAH
Address Row Column address
tRWD tCWL
tAWD tRWL
tRCS tCWD tWP
WE tOEA
OE tDH
tOED tDS
tOLZ
Upper input
tCLZ Data in
tCAC
tAA
tRAC tOEZ
Upper output
Data out tOED
Lower input
Lower output

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Lower byte read-modify-write waveform

tRWC
tRAS tRP
RAS
tCRP tRPC
UCAS
tCSH
tRCD tCAS
tCRP tRSH tCRP
LCAS
tRAD tRAL
tASR tACS tCAH
tRAH
Address Row Column address
tRWD tCWL
tAWD tRWL
tRCS tCWD tWP
WE
tOEA
OE
tOLZ tOED
Upper input
Upper output
tDH
tOED tDS
Lower input
tRAC Data in
tAA
tCAC
tCLZ tOEZ
Lower output
Data out

Hyper page mode read waveform

tRASP tRP
RAS
tRHCP
tCSH tRSH
tCRP tRCD tCAS tCP tHPC
UCAS,
LCAS
tAR
tRAD tRAL
tASR tRAH tASC tCAH
Address Row Col address Col address Col address
tRRH
tRCS
tRCH
WE
tOEA tOEA
OE
tRAC tCPA tOEZ
tCLZ
tOEZ tOFF
tCAC tCPA
tAA
DQ Data out Data out Data out

tOLZ tCLZ tCLZ

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Hyper page mode byte write waveform

tRASP tRP
RAS
tCSH tRSH tCRP
tCRP tRCD tCAS tCAS
UCAS
tCP tHPC
tHPC
tCRP tCAS tCP tRPC
LCAS
tRAH tCAH tRAL
tASR tRAD tASC tCAH
tASC tCAH tASC
Address Row Column 1 Column 2 Column n

tRCS tRCH

WE
tOEA tOEA tOEA tRRH
OE
tCAC
tCLZ tOLZ
tAA
tCPA tOEZ
Lower DQ Data out 2
tAA tOLZ tAA
tRAC tCPA
tCAC tCAC tOFF
tCLZ tOEZ tCLZ tOEZ
Upper DQ
Data out 1 Data out n
tOLZ

Hyper page mode early write waveform

tRASP
tRAH tRWL
RAS
tCRP tRCD tPC
tCSH tASC tCAH
tCAS tWCS tCP tRSH
UCAS,
LCAS tAR tRAL
tASR tRAD
Address Row address Col address Col address Col address
tCWL
tWP
tWCH tOEH
WE

OE
tHDR tOED
tDS tDH
DQ Data in Data In Data in

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Hyper page mode byte early write waveform

tRASP tRP
RAS
tCSH tRSH
tCRP tRCD tCAS tCAS tCRP
UCAS
tCP tCP
tPC tPC
tCRP tCAS tRPC
LCAS
tRAD tRAL
tRAH tCAH tCAH tCAH
tASR tASC tASC tASC
Address Row Column 1 Column 2 Column n

tRWL
tWCH tWCH tWCH
tWCS tWCS tWCS
tWP tWP tWP
tCWL tCWL tCWL
WE

OE
tDS tDH
Lower DQ Data In 2

tDS tDH tDS tDH

Upper DQ
Data in 1 Data in n

Hyper page mode read-modify-write waveform

tRASP tRP
RAS
tHPRWC
tCSH
tRCD tCAS tCP tCRP
UCAS,
tRAD
LCAS tASR tRAH tRAL
tASC
tASC tCAH tASC tCAH tCAH
Address Row ad Col ad Col ad Col address
tRWD tCWL tCPWD tRWL
tRCS tCWD tCWD tCWD tCWL
tAWD tAWD tWP
WE
tOEA tOEZ tOED tOEA
OE
tAA tDH
tRAC tDS tDS tCPA
tCLZ tCLZ tCLZ
tCAC tCAC tCAC
DQ Data in Data in Data in
Data out Data out
Data out

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CAS before RAS refresh waveform WE = VIH

tRC
tRP tRAS
RAS

tRPC tCHR
tCP
tCSR
UCAS,
LCAS
OPEN
DQ

RAS only refresh waveform WE = OE = VIH or VIL

tRC
tRAS tRP
RAS
tCRP tRPC
UCAS,
LCAS
tASR tRAH

Address Row address

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Hyper page mode byte read-modify-write waveform

tRASP tRP
RAS
tCSH
tRCD tRSH
tCRP tCAS tCAS tCRP
UCAS

tCP tCP
tCAS
LCAS
tRAL
tRAD tCAH tCAH tCAH
tRAH tAWD tAWD
tASR tASC tASC tASC
Address R C1 C2 Cn
tCPWD tAWD
tAWD tRWL
tCPWD
tCAH tCWD tCWD tCWD
tRWD tCWL tCWL tCWL
tWP tAWD tWP tWP
WE
tOEA tOEA tOEA
OE
tOED tDH tOED tDH
tDS tDS
Upper input
Data in 1 tCPA Data in n
tRAC
tAA tOEZ tAA tOEZ
tCAC tCAC
tCLZ tCLZ
Upper output
Data out 1 tOED tDH Data out n
tDS
Lower input
tCPA Data in 2
tAA tOEZ
tCAC
tCLZ
Lower output
Data out 2

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Hidden refresh waveform (read)

tRC tRC
tRAS tRP tRAS tRP

RAS
tCRP tCHR
tRCD tRSH tCRP

CAS
tAR
tRAD
tCAH
tRAH
tASR tASC

Address Row Col address

tRCS tRRH

WE
tOEA

OE
tRAC tOFF
tAA
tCAC
tCLZ tOEZ

DQ Data out

Hidden refresh waveform (write)

tRC
tRAS tRP
RAS
tCRP tRCD tRSH tCHR

UCAS,
LCAS tAR
tRAD
tRAH tRAL
tASR tASC tCAH
Address Row address Col address
tRWL
tWCR
tWP
tWCS tWCH
WE
tDS tDH
tDHR
DQ Data in

OE

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CAS before RAS refresh counter test waveform

tRAS
tRSH tRP
RAS
tCSR tCPT
UCAS, tCHR tCAS

LCAS
tRAL
tASC
tCAH

Address Col address

tAA
tCAC tOFF
tCLZ tOEZ
DQ Data out

tRRH
Read cycle

tRCS tRCH
WE
tROH
tOEA
OE
tRWL
tCWL
tWP
tWCH
tWCS
WE
Write cycle

tDH
tDS
DQ Data in

OE
tRCS
tRWL
tWP
tCWD
tAWD tCWL
WE
Read-Write cycle

tOEA
tOED
OE
t AA tDH
tCLZ tOEZ
tCAC tDS
DQ Data out Data in

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CAS-before-RAS self refresh cycle

W53 W5$66 W536

5$6

W53& W53&
W&3
W&65 W&+6
8&$6
/&$6
W&(=
'4

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Package dimensions

42-pin SOJ
Min Max
'
H
A 0.128 0.148
F A1 0.025 -
SOJ ( (
A2 0.105 0.115
B 0.026 0.032
3LQ b 0.015 0.020
(

c 0.007 0.013
% D 1.070 1.080

$ $ E 0.370 NOM
$
E1 0.395 0.405
E Seating
Plane E2 0.435 0.445
e 0.050 NOM

50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26
c 50-pin TSOP 2
Min Max
(mm) (mm)
A 1.2
TSOP 2 E He A1 0.05
A2 0.95 1.05
b 0.30 0.45
c 0.12 0.21
1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25

d 20.85 21.05
d
E 10.03 10.29
l
He 11.56 11.96
e 0.80 (typical)
A2
A l 0.40 0.60
A1 0–5°
b e

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Capacitance  ƒ = 1 MHz, Ta = Room temperature
Parameter Symbol Signals Test conditions Max Unit
CIN1 A0 to A9 Vin = 0V 5 pF
Input capacitance
CIN2 RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF
DQ capacitance CDQ DQ0 to DQ15 Vin = Vout = 0V 7 pF

AS4LC1M16E5 ordering information

Package \ RAS access time 50 ns 60 ns
AS4LC1M16E5-50JC AS4LC1M16E5-60JC
Plastic SOJ, 400 mil, 42-pin
AS4LC1M16E5-50JI AS4LC1M16E5-60JI
AS4LC1M16E5-50TC AS4LC1M16E5-60TC
TSOP 2, 400 mil, 44/50-pin
AS4LC1M16E5-50TI AS4LC1M16E5-60TI

AS4LC1M16E5 part numbering system

AS4 LC 1M16E5 –XX X X
Package: Temperature range
C = 5V CMOS
DRAM prefix Device number RAS access time J = 42-pin SOJ 400 mil C=Commercial, 0°C to 70°C
LC = 3.3V CMOS
T = 44/50-pin TSOP 2 400 mil I=Industrial, -40°C to 85°C

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